JP2003323352A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an efficient and quick defect substitution method in a nonvolatile memory and a volatile memory including a defective area. <P>SOLUTION: The nonvolatile or volatile memory, which mounts thereon a memory cell for recording values, a function of recording and managing a defect status included in the memory cell, and a function of interfacing the function with a host system, has a means for partitioning the memory cell into a plurality of areas and managing defects separately in each area, a means for referring to the management information to access a substitute for a defective area upon access by the host system, and a means for using the means to make the memory cell including defects apparently indefectible to the host system. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of a highly reliable, high-speed and inexpensive memory system in a memory using a volatile or non-volatile recording portion including a defective area.

[0002]

2. Description of the Related Art In a memory device, when an access unit to an internal memory cell is accessible in a block unit in which a plurality of bytes are collected and includes a defective block,
In order to manage them, as described in JP-A-2000-11677, a normal area and a spare area for substituting a defective area included in the area are provided in the memory, and each block on the spare area is provided. And defective management information for managing the association of defective blocks on the data area that it substitutes. With this, when the data area is accessed, the defect management information is referred to determine whether the access address is a defective block, and if the block is a defective block, the block on the corresponding spare area is accessed to perform defective replacement. .

Further, as described in Japanese Patent Laid-Open No. 6-124596, a physical address and a logical address are assigned to each block in the data area, and management information for associating them is prepared. Then, when the host specifies a logical address for writing data, the data is newly recorded in the erased block and the physical address and the logical address are associated with each other. The old data in the block corresponding to the physical address previously assigned to this logical address is erased.

[0004]

In the above conventional technique, it is necessary to refer to all the correspondence information with the spare area every time the normal area is accessed, and the defective blocks in the entire normal area are collectively referred to as the spare area. For example, when the normal area is huge, the spare area also becomes huge and the correspondence information becomes huge. Therefore, it takes time to search for defects.

Further, in the above-mentioned conventional technique, even if defective blocks are locally concentrated in the normal area, it is necessary to refer to all the correspondence information with the spare area when the normal area is accessed. The occurrence of such a defect affects the access time over the entire normal area. Furthermore, in the above-mentioned conventional technique, in order to disperse the number of times of erasing and writing data,
Since the correspondence information between the physical address and the logical address in all the data blocks is required, the table search time and management information become enormous. Therefore, the access time becomes slow and a large management area is required.

An object of the present invention is to provide a memory device capable of suppressing a decrease in access time to the normal area even when the normal area and the alternative area become huge and the management information amount increases.

Another object of the present invention is to provide a high-speed and efficient memory device which does not affect the access speed of normal areas other than the vicinity thereof even if defective blocks are locally concentrated in the normal area. To do.

Another object of the present invention is to reduce the management information for distributing the number of times of erasing and writing of data, and to reduce the management information search time at the time of access, thereby enabling efficient writing. A memory device is provided.

[0009]

In order to achieve the object of the present invention, in a memory device including a defective block, a segment in which a plurality of blocks which are access units of a normal area and an alternative area on the memory are grouped together A means for configuring and managing the segments in the normal area and the segments in the spare area in a one-to-one correspondence, and a means for providing a replacement segment in the spare area when a defect occurs in the entire segment and replacing each segment with the replacement segment And.

In order to achieve another object of the present invention, management information for collectively managing each data block of each segment having the same offset value a from the beginning of each segment, and erasing into individual data blocks. When the number of times of erasing and writing of a specific data block at the offset a in the segment m reaches a threshold value by using the number of times of erasing and writing recorded at each writing, the value of the previous management information corresponding to the offset a and a means for recording the contents to be written in the data block at the offset a of the segment m on the data block at the offset a of the segment n + m based on the management information, and the data at the offset a of the segment m. Offset a when reading the contents of the block
Offset of segment n + m using the value n of the management information of
and means for reading the contents of the data block of a.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a conceptual explanatory view of the defect replacement processing of the present invention. The flash memory 100 shows the data structure of the flash memory to which the present invention is applied. The host system 120 is a device that accesses the flash memory 100. The flash memory 100, as shown,
Data is held in the flash memory cell 113. In the flash memory cell 113, normally, erasing, writing and reading are performed in a unit called a block in which a plurality of bytes are integrated. There are good blocks that can be used normally and bad blocks that have become defective due to defects during manufacturing. In the present invention, the flash memory cell 1
13 is divided into two areas, a normal area 108 and an alternative area 109, and managed. The normal area stores data of the host system. The substitute area is used to replace the defective block in the normal area. In each area,
A combination of n blocks is defined as a segment, and each area is treated as consisting of multiple segments.

The memory physical address 102 is an address sequentially assigned to blocks from the beginning of the flash memory cell 113. The offset 101 is an address assigned with the head of each segment as 0, and indicates an offset value from the head of each segment.

The data segment in the normal area 108 and the alternative segment in the alternative area 109 have a one-to-one correspondence. That is, the data segment n corresponds to the alternative segment n.
This association information is stored in the defect management table 114.

The defect management table 114 holds correspondence information for each segment. That is, the correspondence information between the data segment n and the alternative segment n is the segment n.
The management information 111 is held in the defect management table 114.

The entry 117 in the segment management information is
The state of each block in the corresponding alternative segment is shown.
For example, the head entry indicates the status of the head block in the alternative segment. The information constituting the entry will be described. The good / bad flag 110 indicates whether the corresponding alternative segment is a good block or a bad block. The substitution source logical address 112 indicates the offset of the block in the normal area that the block corresponding to this entry substitutes. For example, since the head block of the alternative segment 0 replaces the bad block at offset 2 in the data segment 0, 0002h is recorded in the replacement source logical address of the head entry of the segment 0 management information in the failure management table 114. Usually, the offset 101 has a smaller address space than the physical address of the memory, and therefore the amount of information of the replacement source logical address is small. The alternative process is a process for ensuring a normal access by preparing a normal area corresponding to a defective area and making an access instead of the defective area.

The flash memory 100 having the above-mentioned structure is provided with a host system 120 through an address conversion process 107.
Host space 123 is provided. In this space, the host logical address 121 corresponds to the memory physical address 102 in the flash memory 100, but since the defective block is replaced by the address conversion processing 107, the host space 123 is entirely configured with good blocks. .

FIG. 2 is a flow chart showing the flow of the address conversion processing 107.

The host system 120 sends the access target host logical address to the flash memory 100.
(Step 201). The flash memory 100 calculates the data segment in the normal area corresponding to the host logical address and the offset value (step 202). As this method, for example, since the host logical address has a one-to-one correspondence with the memory physical address, a method of utilizing the relationship between the memory physical address, the data segment, and the offset can be considered. Next, referring to the defect management table, the segment management information of the target data segment is searched for whether or not the offset to be accessed is registered as a substitute (step 203, step 204). If the substitute registration is made, the corresponding block in the corresponding substitute segment is designated (step 206). If the block is not registered, the corresponding block in the data segment is designated (step 205), and the host system 120 accesses the block designated by the flash memory 100 (207). By performing the above processing, the host system 120 becomes the flash memory 1
It is possible to access 00 as a memory that does not include any defective block in a pseudo manner.

In the present invention, in addition to the above defect replacement processing, means for distributing erase / write from the host system 120 is provided. This will be described below. Figure 3
Is an explanatory view of this system concept.

In each block of the data segment, the number of times of erasing and writing is recorded. Then, the wear leveling management table 302 is prepared. This table manages data called the segment shift number for each same offset of the data segment in the flash memory logical space 300 which is the flash memory space after defective replacement. When the data that should correspond to the offset of a certain segment exists at the same offset of a different segment, this data records the difference in the number of segments.
That is, when the data that should be at the offset n of the segment N exists at the offset n of the segment N + M, the segment shift number becomes M. Further, since this value corresponds to the same offset of all the segments, for example, when the segment shift number of the offset n is 1, it indicates that the value of the offset n of all the segments is shifted by one segment.

The erase / write distribution utilizing these pieces of information will be described below.

The step 1 in FIG.
0 is a state before erasing and writing to the flash memory 100. Host system 120 is a data segment
Update the data B at offset 1 of 1 to flash memory 10
When the instruction is set to 0, the number of times of writing the data B is increased by 1. At this time, when the number of times of writing the data B reaches the threshold value m for activating the write distribution process, the flash memory 100 updates the value of the segment shift number 304 in the wear leveling management table 302. As a method of updating this value, a method of simply adding 1 or a method of calculating the offset value so that the data of the data B is stored in the block having the smallest number of times of writing in the same offset of all the segments can be considered. In this example, the case where 1 is added to the current value is shown. As a result, as shown in step 3, all the data existing at offset 1 of all the segments are shifted backward by one segment and re-recorded. As a result, even if the update of the data B is concentrated, the data is internally distributed and written in a plurality of blocks, so that the distributed processing of erase and write can be realized. Further, since it is only necessary to prepare one segment shift number for the same offset of all segments, it is possible to reduce the size of the wear leveling management table 302.

FIG. 4 shows a nonvolatile memory to which the present invention is applied.
An example of the internal structure of 400 is shown. The memory device 401 is connected to the host system 440 via the host I / F 441. The host I / F 441 can be switched by the I / F switching signal 437. Host I /
As an example of F441, a NAND type / AND type flash memory I
/ F, SRAM I / F SDRAM I / F is considered.

The nonvolatile memory 400 includes an I / F switching unit 437 for switching I / F with the host system 440 and an I / F control unit 43 for performing I / F control with the host system 440.
0, a memory cell unit 401 that records information, and a management unit 410 that manages a defective block in the memory cell unit 401. The management unit 410 may control the distributed writing process of the memory cell unit 401.

The I / F control unit 420 and the memory cell unit 401 are
It is connected by ND I / F-1 431 and AND I / F-2 432. Here, AND I / F indicates an I / F specification for controlling an AND type flash memory. It should be noted that this I / F can also be applied to other I / Fs such as NAND flash memory control I / F.

The memory cell section 401 is the host system 44.
It is also possible to control directly from 0 via AND I / F-1 431.

The management unit 410 includes an I / F control unit 430 and a dedicated I / F.
Connected with F 435. In addition, the memory cell unit 40
1 can be controlled via the AND I / F-3 433, and data on the buffer 405 of the memory cell unit 401 can be directly accessed via the SRAM I / F 434.

The control unit 403 further includes a flash memory cell 402, which is a non-volatile recording medium, a buffer 405 composed of SRAM for temporarily recording data to be written in the flash memory, and an external circuit via an AND I / F 407. The control unit 403 controls the buffer 405 and the flash memory cell 402, and the switching unit 404 switches a control signal to the control unit 403 according to the instruction.

FIG. 5 shows an example of the configuration of the management unit 410.

An ECC (Error correcting code) 506 generates and adds an ECC when writing data to the memory cell unit 401, and an E when writing data.
It is used to increase the reliability of data by performing CC calculation and error detection and correction.

The I / F register 505 is used for transmitting / receiving information to / from the I / F control unit 420.

The programmable sequencer 500 controls each circuit in the management unit 410 and executes sequence processing such as substitution processing.

The sequence ROM 501 records the sequence code executed by the programmable sequencer 500. Various processes can be added or changed by changing the sequence code recorded here. Further, instead of the sequence ROM 501, a sequence RAM is mounted so that the sequence code can be read from the memory cell portion when the nonvolatile memory 400 is started, so that the flash memory cell 4 can be manufactured even after the nonvolatile memory is manufactured.
It is possible to modify the sequence code recorded in 02.

In the work RAM 502, the programmable sequencer 500 temporarily stores a value and the memory cell unit 4
01 Used to hold management data for management.

The control register group 503 stores a control register group specialized for the above processing. It is used while the programmable sequencer 500 is in operation.

FIG. 6 shows an address configuration of the non-volatile memory 400.

The lowest address of the non-volatile memory 400 is defined as "0000", and the upper limit accessible by the host system 440 is defined as HMAX602. This area corresponds to the above-mentioned normal area 108. This area is composed of a plurality of data segments having the same size. The highest address of the non-volatile memory 400 is defined as FMAX603. HMAX
A management area 601 is defined between 602 and FMAX 603. The management area 601 is further divided into three areas.
The alternative area 612 is composed of a plurality of alternative segments. Since the size of each alternative segment is optimized for the number of bad blocks included in the data segment and the number of bad blocks predicted to occur, the size of each alternative segment is different. This area is commonly used for all data segments. The management table area 613 is an area for holding the defect management table 114 and the wear leveling management table 302 described above.

FIG. 7 shows an example of the structure of the management table.

The management table 701 comprises a defect management table 701 and a wear leveling management table 706. The defect management table 701 stores the defect management information shown in FIG. Segment swap information 702
Is used to store information when another segment replaces itself if all blocks in the segment have failed. It consists of the following information: Defective segment address 709: The number of the defective segment is recorded. Substitute destination segment address 710: Records the number of the segment that substitutes this segment.

The alternative segment offset 711 and the alternative segment information 715 manage the information of the alternative segment. Since the size of the alternative segment has a variable length for each alternative segment according to the number of defective blocks in the corresponding segment, the management data itself also has a variable length. Therefore,
The alternative segment offset information 711 indicates the start position of the defect management data for each segment on the alternative segment information 715, and the number of entries 714 indicates the number of defective replacement blocks included in the segment. Number of this entry 714
Uses the value calculated using the above-mentioned defective block number calculation means for each segment. The defect management data itself is
The data placed in the alternative segment information 715 and corresponding to each segment has the start address 71 of the alternative segment corresponding to this segment in the management address space at the beginning.
6. After that, the attribute of the block included in the alternative segment is recorded as an entry 717. For example, the information of the first block of the alternative segment is recorded in the entry 0. The content of the entry may be, for example, an offset value from the beginning of the alternative segment, a flag for determining whether the block itself is normal or defective, or the like.

The wear leveling management information 718 is stored in the wear leveling management table. This information is
Record the aforementioned segment shift number for each offset of all data segments.

An example of the basic operation of the non-volatile memory 400 having the above-mentioned configuration will be described.

FIG. 8 is a flowchart showing an operation example when the nonvolatile memory 400 is activated.

When the power supply is inserted, each circuit is initialized.
(Step 801). When the initialization is completed, the I / F control unit 42
0 issues an initialization command to the programmable sequencer 500 in the management circuit 410 (step 802). The programmable sequencer 500 initializes the setting information in the management unit 410 and sets the initial management table read position (step 803). When the initialization process ends, the programmable sequencer 500 issues a management table read command to the memory cell unit 401 (step 80).
5). The memory cell section 402 is a flash memory cell 40.
Data is read from 1 (step 806). Then, the programmable sequencer 500 of the memory cell unit 401 and the management unit 410 stores the management table information in the management unit 410.
The data is transferred to the WorkRAM 502 inside (step 807). The programmable sequencer 500 inspects the management table information (step 808), and if this table is usable, the processing ends. If the management table information is defective, the next access address is set, and the following procedure for reading the management table is repeated (step 804).

FIG. 9 is a flow chart showing an operation example at the time of reading data from the non-volatile memory 400. The host system 440 sends the read command to the nonvolatile memory 4
When issued to 00, the I / F control unit 420 receives the command (step 900). Similarly, the host system 440 issues the read address SA to the nonvolatile memory 400.
(Step 901). When the I / F control unit 420 receives the read address SA, the read command and the read address S
A is issued to the programmable sequencer 400 of the management unit 410 (step 902, step 903). Upon receiving the read command, the management unit 500 extracts the segment number and offset value from the read address SA and then performs wear leveling processing to calculate the access destination address.
(Step 904). Then, the corresponding segment information is selected from the management table 700 (step 905). Then, the alternative segment information 715 is compared with the previously calculated offset value to search for a bad block (step 9).
06). If SA indicates a bad block as a result of the comparison, the corresponding alternative address is set in SA '(step 907). If it indicates a normal block, SA is substituted for SA '(step 908). The management unit 410 issues a read command to the memory cell unit 110 (step 90
9), and then SA 'is issued to the memory cell unit 401 (step 910). The memory cell unit 401 reads data from the flash memory cell 401 using SA 'as an access address (step 911). When the data read is completed, the memory cell unit 401 notifies the I / F control unit 420 of the data read completion (step 912). As this method, for example, a method in which the memory cell unit 401 outputs a ready / busy signal, notifies busy during processing, and notifies ready when processing is completed is considered. Then, the I / F control unit 420 reads data from the memory cell unit 110 (step 913) and transfers data to the host system 440 as it is (step 914).

Host system 440 and non-volatile memory 4
01 access arbitration, if the nonvolatile memory 40
If the time between the issuance of a data read command to 1 and the start of data transfer is constant, the host system 4
40 can count the waiting time with a counter or the like. If it is variable, a method in which the non-volatile memory 40 outputs the ready / busy signal and the host system 440 monitors the signal may be considered.

FIG. 10 is a flow chart showing an operation example at the time of writing data to the non-volatile memory 400.

When the host system 440 issues a write command to the nonvolatile memory 400, the I / F control unit 420
Receives a command (step 1000). Similarly, the host system 406 issues the write address SA to the nonvolatile memory 400 (step 1001). Subsequently, the host system 440 transfers the write data to the nonvolatile memory 400.
(Step 1002). This data is transmitted to the memory cell unit 401 via the I / F control unit 420 and stored in the buffer in the memory cell unit 401 (step 10).
03). When the data transfer from the host system 440 is completed, the I / F control unit 420 issues a write command and a write address SA to the management unit 410 (step 100).
4, step 1005). Upon receiving the write command, the management unit 410 calculates the segment number and offset value from the write address SA, and then selects the corresponding segment information from the management table 700 (step 100).
6). Then, the segment information is compared with the offset value of the internal address to search for a defective block (step 10).
07). If SA indicates a bad block as a result of the comparison, the corresponding alternative address is set to SA '(step 1010). If it shows a normal block, SA to SA '
(Step 1009). The management unit 410 issues SA 'to the memory cell unit 110 (step 1011). Then, the management unit 410 sends the write command to the memory cell unit 40.
1 (step 1012). The memory cell unit 401 having received the write command writes the write data transferred from the host system 440 held in the buffer to the flash memory cell 401, using SA ′ as the write address (step 1013). if,
When a write error occurs, the memory cell unit 401 reports an error to the management unit 410 (step 1015), and the management unit 41
0 registers the block SA ′ indicated by this write address as a defective block in the management table (step 101).
4). Then, the management table is saved in the management area (step 1016), the address to be written next is calculated, and the data write process is re-executed. At this time, normally, the next address to be written is the address next to the address in which the write error has occurred, but the calculation may be performed by using some kind of prediction means.

After the memory cell section 401 executes data write
(Step 1017). In the case of normal termination, the write completion is notified to the host system 440 via the I / F control unit 420 (step 1017, step 1018). As a method of notifying the host system 440, there is, for example, a method of transmitting a status. Further, as a waiting control method between the host system 440 and the non-volatile memory 400 after the write command is issued to the non-volatile memory 400 until the notification of the write completion is returned, the ready / busy signal is transmitted as described above. A method in which the non-volatile memory 400 outputs the signal and the host system 440 monitors the signal can be considered.

The nonvolatile memory 40 shown in the present invention
0 is an example, and this method can be applied as an alternative processing method for a volatile memory including a defect. In this case, only the management information is separately managed by the management unit 410 when it is started from the outside.
It is possible to handle this by reading in or loading a non-volatile memory for management information. The present method can be applied not only to the semiconductor memory as the non-volatile memory 400 but also to, for example, a magnetic disk. Further, the configuration shown in the present invention can be applied to a product in which a volatile or non-volatile memory and a controller for controlling the same are packaged in one package.

[0052]

According to the present invention, since the memory is divided into a plurality of areas and the characteristics of each area are managed, the failure management of a memory having a large capacity and including a defective area can be efficiently managed by a small amount of management information. Will be possible.

Further, it becomes possible to shorten the time required for the search and comparison processing of the access address and the defective address performed at the time of access.

Further, even when a locally concentrated defect occurs, when an area other than the area including the defect is accessed, it is possible to reduce the time required for determining the defect of the access address and the normality. Further, it becomes possible to realize the function of managing the number of times of writing for each block and distributing locally intensive erase and write with a small amount of management data.

[Brief description of drawings]

FIG. 1 is a conceptual explanatory diagram of the present invention.

FIG. 2 is a flowchart showing a processing flow of the present invention.

FIG. 3 is a conceptual explanatory diagram of the present invention.

FIG. 4 is a diagram showing a configuration example of a nonvolatile memory to which the present invention is applied.

FIG. 5 is a diagram showing a non-volatile memory configuration example to which the present invention is applied.

FIG. 6 is a diagram showing an example of a memory map of a nonvolatile memory to which the present invention has been applied.

FIG. 7 is a diagram showing a configuration example of a management table of a nonvolatile memory to which the present invention has been applied.

FIG. 8 is a diagram showing an operation example of a nonvolatile memory to which the present invention is applied at initial startup.

FIG. 9 is a diagram showing an operation example during data reading of the nonvolatile memory to which the present invention is applied.

FIG. 10 is a diagram showing an operation example at the time of data writing of the nonvolatile memory to which the present invention is applied.

[Explanation of symbols]

100 ... Flash memory, 101 ... Offset, 10
2 ... Memory physical address, 103 ... Block, 104 ...
Block state, 105 ... Data segment, 106 ...
Alternate segment, 107 ... Address conversion process, 108 ...
Normal area, 109 ... Alternative area, 110 ... Good / bad flag,
111 ... Segment N management information, 112 ... Alternate source logical address, 113 ... Flash memory cell, 114 ... Fault management table, 117 ... Registration entry, 120 ... Host system, 121 ... Host logical address, 122 ... Block state, 123 ... Host space, 300 ... Flash memory logical space, 301 ... Rewrite count, 302 ... SR wear leveling management table, 303 ... Offset value, 3
04 ... Segment shift number, 400 ... Non-volatile memory,
401 ... Memory cell section, 402 ... Flash memory cell, 403 ... Control section, 404 ... Switching section, 405 ... Buffer, 406 ... SRAM I / F-3, 407 ... AND I / F, 408 ... S
RAM I / F-2, 410 ... Management unit, 420 ... I / F control unit, 43
0 ... I / F control unit, 431 ... AND I / F-1, 432 ... AMD I / F-2,
433 ... AND I / F-3, 434 ... SRAM I / F, 434 ... I / F switching signal, 440 ... Host system, 441 ... Host I / F,
Reference numeral 500 ... Programmable sequencer, 501 ... Sequence ROM, 502 ... WorkRAM, 503 ... Control register group, 505 ... I / F register, 506 ... ECC, 7
00 ... Management table configuration example

Continued front page    (72) Inventor Tsuyoshi Nakamura             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kenji Kosakai             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Motoyasu Tsunoda             1099 Ozenji, Aso-ku, Kawasaki City, Kanagawa Prefecture             Ceremony company Hitachi Systems Development Laboratory F-term (reference) 5B018 GA04 GA06 HA01 HA35 KA01                       KA14 NA06 QA14 QA15 RA03                 5B025 AA01 AD13 AE05 AE08                 5L106 AA10 BB12 CC16 CC32 FF04                       FF05 GG05

Claims (15)

[Claims] 1. A non-volatile or volatile recording unit including a defective area capable of accessing information in a specific unit, a recording unit control circuit for controlling the recording unit, and transmitting / receiving with the recording unit. A buffer memory for temporarily recording data, a volatile memory for storing information for managing the defective area in the recording unit, a defect management circuit for processing information in the volatile memory, and a host system In a memory device having an interface control circuit that processes an access and issues an operation instruction to the recording unit control circuit and the defect management circuit, means for individually managing the recording unit by virtually dividing it into a plurality of areas, A method for securing and managing a defective area included in the area for each division unit and an alternative area for replacing a defective area that may occur in the future, and to the defective area. When the serial host system has access,
A memory device having means for converting an access destination in order to access the alternative area. 2. The memory device according to claim 1, wherein each data block in each area having the same position a from the beginning of each area divided into a plurality of areas is
By using the management information for collectively managing each a and the number of erase writes recorded in each data block each time the erase write is performed, the erase write of the specific data block at the position a in the area m is performed. When the number of writes reaches a certain value, the value n of the previous period management information corresponding to the position a is changed, and based on the management information, the contents to be written in the data block at the position a in the region m are stored in the region n + m. A memory device having means for recording to a data block at location a. 3. The memory device according to claim 2, wherein when the contents of the data block at the position a in the area m are read, the value n of the management information at the position a is used and the position a in the area n + m is read. Memory device having means for reading the contents of a data block of the memory device. 4. The memory device according to claim 1, wherein the recording unit has a plurality of types of defect characteristics, and a circuit that performs a substitute process sequentially by a circuit according to each defect characteristic. 5. The memory device according to claim 1, wherein the defect management circuit includes a programmable sequencer and a ROM in which a sequence is recorded, and the sequence code can be changed by replacing the ROM. Memory device. 6. The memory device according to claim 1, wherein the defect management circuit includes a programmable sequencer and a RAM that holds a sequence, and a sequence code is read from the recording unit at the time of start-up and stored in the sequence RAM, and the sequence is stored. A memory device capable of changing the sequence code by having a means for executing a code by a sequencer. 7. The memory device according to claim 5, wherein the recording section has a plurality of types of defect characteristics, only a specific type among them is processed by a programmable sequencer, and other defect characteristics are processed by a dedicated circuit. Processing memory device. 8. A non-volatile or volatile memory cell section including a data area for storing data and an alternative area for substituting the data area, and a management section for managing the memory cell section. In the memory device, the alternative area replaces the data area in a segment unit in which a plurality of access units of the management unit or a host system that requests reading or writing of the data are collected. 9. The access unit is at least one of a data erase unit, a read request unit from the host system, and a write request unit from the host system.
The memory device according to claim 8, wherein the memory device is a memory device. 10. The memory device according to claim 8, wherein the access unit is a block including a plurality of sectors. 11. The memory device according to claim 8, wherein the memory cell unit includes a management information area for storing a correspondence relationship between the data area and the alternative area in the segment unit. 12. The management unit, when starting the memory device, generates management information including a correspondence relationship between the data area and the alternative area in the segment unit in another volatile memory. The described memory device. 13. The management unit according to claim 12, wherein the management unit uses the management information to determine whether to access the data area or the alternative area in response to a request from the host system. Memory device. 14. The management unit, using the management information,
The memory device according to claim 12, wherein an access address from the host system is converted into a physical address of the memory cell unit. 15. The management unit determines the segment unit when detecting a defect of a part or all of the segment in the data area or a defect of the data read from the data area. 13. The memory device according to claim 12, wherein the management information is updated by.