JP2003320670A - Inkjet recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact inkjet recorder of a high driving quality in which nozzles and driving circuits can be incorporated in a substrate even in the large-scale nozzle number and long substrate. <P>SOLUTION: The driving circuit in the inkjet recorder comprises switching elements for driving each of heating elements, a level shifter for driving the switching elements, an AND gate matrix circuit with AND gates over segment lines as printing data and common lines to be selected and scanned, segment circuits for taking printing data for every printing by the number of segment lines, and common circuits for generating selecting scanning signals of a divided number obtained by dividing a total nozzle number by the segment line number. The driving circuit which drives in a time sharing manner in a matrix configuration of the segment line and the common line generates an AND of the segment line and common line at the AND gate, and drives in the matrix configuration by the operation result as an application signal. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ink jet recording apparatus, and more particularly to an ink jet recording apparatus that heats and foams ink to eject it.

[0002]

2. Description of the Related Art Generally, a heating element in an ink jet which heat-foams and ejects ink is driven by a switching element such as a transistor which drives a heating element composed of a thin film or thick film resistor. Driving a large number of heating elements simultaneously causes a large current to flow, so a driving method is adopted in which all heating elements are divided into several groups and the currents that flow at the same time are made smaller by driving the heating elements at different times for each group. There is.

Conventional Example 1: The structure of this driving method is shown in FIG. In general, the drive circuit is provided with a shift register circuit and a latch circuit having the number of bits corresponding to the number of heat generating elements, and the print data transferred from the print data generating section is taken in by the shift register circuit in a manner corresponding to the heat generating elements and the print data is collected. When they are aligned, the latch signal is given and stored in the latch circuit, and at the same time, the print data is simultaneously given to the grouping circuit in the next stage. The grouping circuit groups a group of bits selected and defined by the wiring of the group selection signal, applies the applied signal of the corresponding group to the switch element group based on the group selection signal, and applies the group selection signal to the decoder circuit. It switches and drives sequentially for every group.

As another driving method, various matrix driving methods including diodes and transistors have been proposed. Since matrix driving may be performed in units of rows or columns, the driving circuit can be configured with a circuit scale having the number of bits corresponding to the number of columns or the number of rows.

Conventional example 2: The structure of the diode matrix system is shown in FIG. A composite element consisting of a heating element and a diode is placed at the intersection of a plurality of row selection lines and a column selection line, and applied to the column selection line group connected to one end of the heating element according to the print data. A specific heating element is driven by selecting an arbitrary row selection line connected to one end of. This diode is provided in order to cut off the distribution path of the current generated between the heating elements and suppress the power dissipation by the matrix circuit.

Conventional example 3: FIG. 11 shows the structure of a transistor matrix system. A composite element consisting of a heating element and a transistor is placed at the intersection of a plurality of row selection lines and column selection lines, and applied to the column selection line group connected to one end of the heating element according to the print data. A specific heating element is driven by selecting an arbitrary row selection line connected to. In this figure, the transistor is a FET. Due to the three-terminal element such as the transistor, the current of the heating element flows from the column selection line to the ground, and the crosstalk current generated between the heating elements does not occur. Further, since the control terminal of the transistor has a high input impedance, the row selection line is driven with low power.

[0007]

However, when the number of nozzles increases and the length of the substrate increases in accordance with the increase in the number of nozzles, some difficulties arise in the above-mentioned conventional example.
With a structure in which the nozzle and the drive circuit are integrated into the substrate,
For example, when nozzles of several thousands to more than 10,000 bits are arranged in rows at intervals of several tens of microns and the length of the substrate reaches a scale from 10 cm to 20 cm, it becomes difficult to handle.

Conventional example 1: Since switching elements and drive circuits for the number of heating elements are required, the circuit scale increases as the number of nozzles increases, and not only the number of nozzles and heating elements but also the yield in semiconductor manufacturing of drive circuits is increased. The decline will have an effect. The number of transistor elements in the drive circuit, such as the shift register circuit, the latch circuit, and various gates, is required to be, for example, several tens of elements per bit, so that the total number of elements is on the order of several hundreds of thousands. Generally, since the yield decreases as the number of elements and the board area increase,
If the number of nozzles and the substrate area exceed a certain level, it may be disadvantageous from the viewpoint of yield.

On the other hand, although it is possible to avoid the reduction in yield due to the drive circuit section by adopting a structure in which the drive circuit is separated, it is necessary to mount the drive IC member and mounting, so that the cost of the member surface and the manufacturing surface increases. Resulting in. Furthermore, the unit structure of the head becomes large and complicated.

Conventional Example 2-1: As one means for dealing with the problem of Conventional Example 1, application of the matrix driving method is effective. By driving the heating element group in a matrix in a time-division manner, the circuit scale of the drive circuit unit can be reduced by the number of time-divisions. For example, if matrix driving of 32 divisions is performed,
A new common circuit is required, but the drive circuit is 1/32
It can be significantly reduced with orders close to.

However, in the matrix drive of the conventional example 2-1, a high-power and high-speed switching drive circuit of a segment drive circuit and a common drive circuit for directly driving a heating element including a diode, and a low resistance for suppressing drive voltage loss. Wiring is required. In particular, since the wiring of the common line is wired from one end to the other of the heating elements arranged in a line, an extremely low resistance wiring and a power capacity capable of withstanding the amount of heat generation are required.

For example, the driving current of one heating element is 10
0mA, applied signal pulse width 2μs, segment line 1
When the length of the arrangement of all 00 heating elements (100 × 32 = 3200 elements) is 15 cm, the driving current per common line is 10 A, and a common driving circuit that switches this for about 0.1 μs and at least 15 cm2 Wiring resistances such that variations in applied voltage to each heating element are negligible must be provided for the number of common lines.

The transistors of the common drive circuit are at least 6 W (10 A, collector saturation voltage 0.6
Since more power is required (as V), it can be said that it is difficult to build the entire circuit on the substrate.

Further, the wiring width W where the common line has a film thickness of several thousand Å, which is generally the upper limit of Al material, and the voltage drop in which the applied voltage variation can be ignored is 0.5 V, is W = Al. Resistivity ρ × wiring length L / (wiring resistance R × film thickness T) = 3.37 × 10 −8 × 7.5 cm / (0.05
Ω × 2000Å) = 25 mm is required. It can be said that the wiring of this common line on the substrate is unrealistic. In this way, in the case of a long print width with hundreds or thousands of nozzles,
It can be said that the diode matrix of the conventional example 2-1 of the power driving matrix is an inappropriate matrix driving method.

Conventional Example 2-2: The problems of Conventional Example 2-1 are greatly improved in this example. A switch element is provided in each heating element, and a common line drives a control terminal having a high input impedance, resulting in low power driving. When the switch element is a transistor, it supplies a base current, and when the switch element is a FET, a voltage for charging the gate terminal is applied.

FIG. 11 shows a block diagram of the FET matrix. The common drive circuit for driving the common line and the wiring width can be remarkably reduced, and it becomes possible to form the wiring on the substrate. For example, considering the same case as described above, the number of nozzles is 3,200, and the length of arrangement of the heating elements is 15c.
m, 100 segment lines with 32 time divisions, and gate capacitance 10 per element when the switching element is an FET
When pF, the voltage of the applied signal pulse is 15V, and the 90% switching time of the applied signal pulse is 0.1 μs, the common drive circuit has a switching current I = 100 × 10p.
It is sufficient if it has an ability of F × 15 V / 0.1 μs = 0.15 A or more. Also, the wiring resistance R of the common line is R = 0.1 μs / (100 × 10 pF) over at least 15 cm2.
= 10 kΩ or less (the capacitance of the wiring itself is ignored as the distribution constant of resistance and capacitance).

However, when the number of nozzles is further increased and the nozzle arrangement becomes longer, or when the number of time divisions is decreased and the segment lines are increased to increase the repeated ejection speed, the same tendency as in the conventional example 2-1 is obtained. The issue of comes out.
In addition, the common drive circuit requires a high-power transistor of the order of several watts, which occupies a large area on the substrate.

Further, due to the long wiring lengths of the common line and the segment line, a difference Δt in the energizing pulse width corresponding to the delay time occurs at the output portion and the terminal portion. FIG. 12 shows a timing example. For example, when the common drive circuit is arranged in the center of the board, the wiring length and the wiring capacitance C are about 1/2 of the board length.
(Including gate input capacitance of switch element) and wiring resistance R
There is a difference of 90% arrival time t = CR [s] between the central portion of the substrate and the end portion of the substrate, regarding the wiring as a CR distribution constant.

On the other hand, when the common drive circuit is sandwiched between the segment drive circuits and the wirings on the segment line side are arranged adjacent to each other on the left and right sides, a delay time is generated similarly to the common line. The wiring length is about the same as the common line, but due to the difference in wiring resistance and wiring capacitance, a difference in delay time of Δt, that is, a phase shift occurs near the edge of the substrate, which is the edge of the wiring, and an applied signal pulse in the central portion of the substrate is generated. The pulse width of the applied signal at the end of the substrate is shorter than the width A by Δt. As a result,
In some cases, the applied signal pulse widths of the central portion of the substrate and the end portions of the substrate differ by Δt, and it may not be possible to obtain a uniform application time for all heating elements.

The present invention has been made in view of the above problems, and an object of the present invention is to drive a small number of nozzles and a driving circuit in a small size in which a driving circuit can be integrally formed on a substrate even in a long substrate. An object of the present invention is to provide a high quality inkjet recording device.

[0021]

To achieve the above object, the present invention is based on a nozzle for ejecting ink, an ink supply path for supplying ink, a heating element for heating and foaming ink, and print data. In an ink jet recording apparatus including a drive circuit that generates an applied signal that turns on / off a heating element, and a drive control circuit that generates print data and drive timing, the driving circuit includes a switch element that drives each of the heating elements, A level shifter for driving the switch element, an AND gate matrix circuit having an AND gate over a segment line which is print data and a common line for selective scanning, and a segment circuit which fetches print data for each print of the number of segment lines. , The total number of nozzles is divided by the number of segment lines, And a common circuit that generates a logical product of the segment lines and the common line in a time-divisional drive. The AND gate generates a logical product of the segment line and the common line, and the operation result is used as an applied signal. It is characterized by matrix driving.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a block diagram showing the overall construction of an embodiment of the present invention. Drive control circuit 101
Generates the print data rasterized in accordance with the nozzle arrangement of the inkjet recording head 102 and the drive timing of the drive circuit of the inkjet recording head 102. The inkjet recording head 102 includes a nozzle,
It has the functions of an ink supply path, a heating element, and a drive circuit, and performs printing operation under the control of the drive control circuit 101.

The appearance of the ink jet recording head 102 is shown in FIG. The silicon substrate 201 in which the nozzle 202 and the drive circuit 203 are built is fixed on the support substrate 205. Here, the nozzles are arranged in a line. A sub-tank 206 for accumulating ink via the support substrate 205 is positioned, and ink is supplied to the heating element formed on the silicon substrate through the ink supply port provided on the silicon substrate 201 via the support substrate 205, and ink is ejected from the nozzle. To be done. The ink supply tube 207 is a tube that supplies ink from a separately provided large ink tank. The cable 204 supplies a signal for the drive circuit from the drive control circuit 101, a power source, and a power source for the heating element.

Next, FIG. 3 shows a block diagram of the drive circuit 203.

A driving power supply for supplying a current is connected to one terminal of the heating elements H1 to 14080 arranged in 14080, and a switching element FET is provided for each heating element at one terminal.
Connect. The level converter 302 converts the applied signal processed by the AND gate matrix 301 at the preceding stage into a voltage amplitude for driving the switching element FET, and the voltage amplitude is changed from T1 to T14.
A gate signal is given to 080 to drive the heating element corresponding to the print data. Here, the switching element FET is NM
The gate signal is 0V / 15 because the OS enhancement type transistor is used and the driving power source is 15V.
The pulse has a voltage amplitude of V. On driving, heating element H
1 to H14080 are divided into 44 groups of 320 bits each in the order of arrangement and driven for each group. 320 × 44 grouping on this drive is AND
It is composed of a gate matrix 301.

FIG. 4 shows a block diagram of the AND gate matrix 301. A cell 401 including a heating element, a switch element, a level converter, and an AND gate has segment wiring lines S1 to S320 and common wiring lines C1 to C4.
4 matrix wirings. The common line corresponding to the print data is selected in synchronization with simultaneous output of 320 print data from the latch 306 in the previous stage to the segment lines S1 to S320 which are column wirings. The applied signal is turned on only in the cell group in which the AND conditions of the segment line and the common line are complete. This one operation is repeated by printing groups of 320 dots for 44 groups to print 14080 dots / line.

From the viewpoint of the nozzle arrangement, 320 heating elements for every 44 pitches are selected at the same time, and printing is performed sequentially from the end. More specifically, the first time. H1, H4
Common line C1 is selected when print data corresponding to 4, H89, ..., H14036 are aligned in the segment line group. Second time. H2, H45, H90, ... H14037
When the print data corresponding to is aligned in the segment line group, the common line C2 is selected. … Finally the 44th time. H
When the print data corresponding to 44, H87, H88, ... H14035 are aligned in the segment line group, the common line C44 is selected and one line printing is completed.

In the present embodiment, this 1-line printing is set to the repetition speed of 16 kHz. The shift register 305 that fetches print data so as to correspond to this speed arranges 20-bit registers in 16 pipes,
Shift clock 14.08 MHz × 16 pipe = 22
Print data is captured at a transfer rate of 5.28 MHz.

On the other hand, in driving the common line side, the common addresses for group selection are sequentially switched in synchronization with the segment line side, specifically, in accordance with the latch timing, and the decoder 303 selectively scans the common line.
At this time, the print pulse having the pulse width of the applied signal is set to AN.
It is input to the D gate 304, and the selected scan pulse having the applied signal pulse width is output to the selected common line through the AND gate 304. The circuit area of the AND gate matrix 301 that performs such a matrix operation is A
It is almost occupied by the wiring region of the ND gate, the common line, and the segment line. In this embodiment, a multilayer wiring structure is adopted and the occupied width is about 1000 μm.

Due to the long wiring lengths of the common line wiring and the segment line wiring in the AND gate matrix 301, a phase shift corresponding to the delay time occurs at the output section and the terminal section.

FIG. 5 shows a layout of the circuit positions on the board and the wiring.

When the common circuit 501 composed of the decoder 303 and the AND gate 304 is arranged in the central portion on the substrate, the wiring length and the wiring capacitance C (AN
The input resistance of the D gate matrix is included) and the wiring resistance R exists, and there is a difference of 90% arrival delay time t = CR [s] between the central portion of the substrate and the end portion of the substrate when the wiring is regarded as the distribution constant of CR.

On the other hand, for the wiring on the segment line side, a segment circuit 502 composed of a latch 306 and a shift register 305 is adjacent to each other on both sides of the common circuit 501 in order to allow the common side and the segment side to operate synchronously at high speed. When arranged in the same manner, a phase shift corresponding to the delay time occurs as in the common line wiring. The wiring length is about the same as that of the common line, but due to the wiring capacitance of which the input capacitance of the AND gate matrix is about ½ and the difference in the number of stages of the buffer 503, there is a print data valid period near the substrate end, which is the wiring end. The phase of the selective scanning pulse is shifted.

The buffer 503 is provided to shape the waveform and reduce the output load of the AND gate 304. In the present embodiment, the phase shift amount at the substrate end is that the selection scan pulse of the common line is delayed by about 100 ns with respect to the print data switching time on the segment line side.

FIG. 6 shows a timing chart. The print pulse width at this time is 1 μs. The drive control circuit 101 controls so as to secure the print data for a period longer than the difference of 100 ns, that is, at least 1.1 μs for the print data valid period. Specifically, the latch cycle is 1.43 μs, and the sequence is such that the common address and the print pulse are output in accordance with the latch signal, and the print pulse is controlled and output in a phase located within the print data valid period.

<Second Embodiment> As a second embodiment of the present invention, a case of a matrix formed of NAND gates will be described.

FIG. 7 shows a block diagram of a NAND gate matrix. A cell 701 including a heating element, a switching element, and a NAND gate is connected to the segment wiring lines S1 to S32
0 and the common wirings C1 to C44 are arranged over the matrix wirings. The switch element is a P-channel FET,
The operation is ON when the applied signal is at the low level and OFF when the applied signal is at the high level. As described above, it is possible to employ a combination of the NAND gate and the P-channel FET to operate with the logic of the polarity opposite to that of the first embodiment.

<Third Embodiment> As a third embodiment of the present invention, the common line selection scanning period is longer than the segment line print data valid period and the print data is positioned within the selection scanning period valid period. The case will be described.

In the first embodiment, the print signal pulse is passed to the common line side, whereas in the present embodiment, the print signal pulse is passed to the segment line side.

FIG. 8 shows a block diagram of the third embodiment.

Immediately after the output of the AND gate 801 from the latch 802, A is generated by the latched print data and print pulse.
The ND gated print data is output to 320 segment lines. On the other hand, the selection scanning signal is output to the common line according to the common address synchronized with the latch. At this time, the print pulse with respect to the latch is shifted in phase by at least the delay amount of the common line, and the AND gate 80
Enter 1. That is, the print pulse is input so that the print data is positioned within the effective period of the selective scanning signal. Even with such a method, it is possible to drive in consideration of the delay of the common line.

As a method of matrix driving of an ink jet, Japanese Patent Laid-Open No. 10-44411 discloses that in time-divisional driving, the heating element itself is used to heat and heat the ink so as to keep the ink at a constant temperature and to perform stable ejection. The configuration is also included in the present invention. Even if the number of nozzles is increased and the number of nozzles is increased, the present invention that controls the phase shift in consideration of the high density of the matrix region and the delay is effective.

[0044]

As described above, according to the present invention,
High-power driving of the matrix circuit due to the increase in the number and length of the nozzles and uniform distribution of the low-power high-density matrix circuit without generating the distribution of the applied signal pulse width due to the delay in the long-distance matrix wiring. An effect that matrix driving can be realized is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is an external view of an inkjet recording head according to the present invention.

FIG. 3 is a block diagram of a drive circuit according to the present invention.

FIG. 4 is a block diagram of an AND gate matrix.

FIG. 5 is a layout diagram of circuit positions and wirings of a drive circuit on a substrate.

FIG. 6 is a timing chart of a print data valid period and a print pulse.

FIG. 7 is a block diagram of a NAND gate matrix according to the second embodiment of the present invention.

FIG. 8 is a block diagram of print pulse input relating to phase shift control according to the third embodiment of the present invention.

FIG. 9 is a configuration diagram of a driving method in Conventional Example 1.

FIG. 10 is a configuration diagram of a diode matrix in Conventional Example 2-1.

FIG. 11 is a configuration diagram of a transistor matrix in Conventional Example 2-2.

FIG. 12 is a timing diagram of a phase shift in Conventional Example 2.

[Explanation of symbols]

101 drive control circuit 102 inkjet recording head 201 Silicon substrate 202 nozzle 203 drive circuit 204 cable 205 support substrate 206 Ink sub tank 207 Ink supply tube 301 AND gate matrix 302 level converter 303 decoder 304 AND gate 305 16 Pipe shift register 306 latch 401 cells 501 common circuit 502 segment circuit 503 buffer 504 common line 505 segment line 701 cells 801 AND gate 802 shift register 803 decoder

Claims (6)

[Claims] 1. A nozzle for ejecting ink, an ink supply path for supplying ink, a heating element for heating and foaming ink, and a drive circuit for generating an application signal for turning on / off the heating element based on print data. In an ink jet recording apparatus including a drive control circuit that generates print data and drive timing, the drive circuit includes a switch element that drives each heating element, a level shifter that drives the switch element, and a segment line that is print data. And an AND gate matrix circuit having an AND gate over common lines for selective scanning, a segment circuit for fetching print data for each printing of the number of segment lines, and a number of divisions obtained by dividing the total number of nozzles by the number of segment lines. It consists of a common circuit that generates a selective scan signal and And a common line matrix drive circuit for time-division driving, wherein an AND gate generates a logical product of a segment line and a common line, and the operation result is applied as a signal for inkjet driving. apparatus. 2. The AND gate matrix circuit is composed of n segment lines and m common lines. On the other hand, the nozzles are arranged in a line or in a matrix alternately in a row or in a matrix so as to correspond to the column order of the matrix configuration from S1 C1 ... SnC1 to S1Cm ... 2. The inkjet recording apparatus according to claim 1, wherein the common C1 to Cm are sequentially selected or selectively scanned. 3. The matrix configuration is AN for each element.
It is an AND gate matrix circuit of a logical operation that arranges a D gate circuit, inputs a segment line and a common line, and turns on printing when the print data on the segment line is on and the common line is selected. The ink jet recording apparatus according to claim 2, which is characterized in that. 4. In the time-divisional driving in which the print data of the segment line and the selective scan signal of the common line operate synchronously, the effective period of the print data corresponding to each selective scan of each continuous selective scan period is common. 2. The ink jet recording apparatus according to claim 1, wherein the phase relationship is such that the selective scanning pulse width is longer than the selective scanning pulse width of the line and the selective scanning pulse width is positioned within the effective period of the print data. 5. The print data valid period is controlled to be longer than at least a period in which a maximum value of a difference between a common line delay time and a segment line delay time is added to a selective scanning pulse width. The inkjet recording device according to claim 4. 6. A nozzle for ejecting ink, an ink supply path for supplying ink, a heating element for heating and firing ink, and a drive circuit for turning on / off the heating element based on print data are formed on the same substrate. The ink jet recording apparatus according to claim 1, wherein the ink jet recording apparatus is incorporated.