JP2003318173A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JP2003318173A
JP2003318173A JP2002120445A JP2002120445A JP2003318173A JP 2003318173 A JP2003318173 A JP 2003318173A JP 2002120445 A JP2002120445 A JP 2002120445A JP 2002120445 A JP2002120445 A JP 2002120445A JP 2003318173 A JP2003318173 A JP 2003318173A
Authority
JP
Japan
Prior art keywords
insulating film
film
semiconductor device
vacuum
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002120445A
Other languages
Japanese (ja)
Inventor
So Yasuoka
創 安岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002120445A priority Critical patent/JP2003318173A/en
Publication of JP2003318173A publication Critical patent/JP2003318173A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which is capable of restraining a capacitor element that uses a ferroelectric material or a high dielectric material as a capacitor insulating film from deteriorating in characteristics. <P>SOLUTION: The capacitor element 105 comprising a lower electrode 104, a ferroelectric capacitor insulating film 106, and an upper electrode 107 is formed on a first protective insulating film 101 on a semiconductor substrate 103 where a transistor 102 is formed. Then, a second protective insulating film 108 is formed so as to cover the capacitor element 105. Then, the substrate 103 and the others are subjected to a thermal treatment in a vacuum. A first wiring layer 110 is formed so as to be electrically connected to the transistor 102 and the capacitor element 105 through the intermediary of a contact hole 109 provided to the second protective insulating film 108. Then, an inter-wiring layer insulating film 111 is formed to cover the first wiring layer 110. Then, the semiconductor device is subjected to a thermal treatment in a vacuum. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、強誘電体膜又は高
誘電体膜を容量絶縁膜とする容量素子を内蔵した半導体
装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a built-in capacitive element having a ferroelectric film or a high dielectric film as a capacitive insulating film.

【0002】[0002]

【従来の技術】近年、マイクロコンピュータ等の高速
化、低消費電力化が推進される中で、民生用電子機器が
一段と高度化し、使用される半導体装置とその半導体素
子の微細化とが急速に進んできている。一方、それに伴
って、電子機器から発生される電磁波雑音である不要輻
射が大きな問題になっており、この不要輻射低減対策と
して高誘電率を有する誘電体(以下、単に高誘電体と記
す)を容量絶縁膜とする大容量の容量素子を半導体集積
回路装置等に内蔵する技術が注目をあびている。
2. Description of the Related Art In recent years, with advances in speeding up and low power consumption of microcomputers and the like, consumer electronic devices have become more sophisticated, and the semiconductor devices used and the miniaturization of their semiconductor elements have rapidly become smaller. It is progressing. On the other hand, along with this, unnecessary radiation, which is electromagnetic noise generated from electronic devices, has become a big problem. As a measure for reducing the unnecessary radiation, a dielectric material having a high dielectric constant (hereinafter simply referred to as a high dielectric material) is used. A technique for incorporating a large-capacity capacitive element serving as a capacitive insulating film into a semiconductor integrated circuit device or the like has been attracting attention.

【0003】また、ダイナミックRAMの高集積化に伴
い、従来の珪素酸化物または珪素窒化物の代わりに、高
誘電体を容量絶縁膜として用いる技術が広く研究されて
いる。さらに、従来にない低動作電圧かつ高速書き込み
読み出し可能な不揮発性RAMの実用化を目指し、自発
分極特性を有する強誘電体膜に関する研究開発が盛んに
行われている。これらの半導体装置を実現するための最
重要課題は、容量素子の特性を劣化させることなく多層
配線を実現できるプロセスを開発することである。
Further, as the dynamic RAM is highly integrated, a technique of using a high dielectric material as a capacitive insulating film instead of the conventional silicon oxide or silicon nitride has been widely studied. Furthermore, research and development on a ferroelectric film having a spontaneous polarization characteristic have been actively conducted with the aim of putting a non-volatile RAM capable of high-speed write / read with a low operating voltage, which has never been seen. The most important issue for realizing these semiconductor devices is to develop a process capable of realizing multilayer wiring without deteriorating the characteristics of the capacitive element.

【0004】この多層配線形成における課題の一つとし
て、層間絶縁膜に含まれる水分が拡散することによる強
誘電体膜の分極特性の劣化がある。その劣化メカニズム
については、未だ解明されていないが、絶縁膜中の水分
がAlやTiなどの配線材料と反応して水素を発生し、
酸化物である強誘電体または高誘電体素子を還元し、特
性劣化を招くという説が有力である。いずれにせよ絶縁
膜中などに残留する水分があった場合、配線工程などの
熱処理によって強誘電体または高誘電体薄膜の絶縁耐圧
性劣化、または強誘電体の分極特性劣化が発生するの
で、何らかのプロセス対策が必要とされてきた。
One of the problems in forming the multi-layer wiring is deterioration of polarization characteristics of the ferroelectric film due to diffusion of water contained in the interlayer insulating film. Although the deterioration mechanism has not been clarified yet, moisture in the insulating film reacts with wiring materials such as Al and Ti to generate hydrogen,
The theory that the ferroelectric or high-dielectric element, which is an oxide, is reduced and the characteristics are deteriorated is promising. In any case, if there is residual moisture in the insulating film, heat treatment such as wiring process may cause deterioration of dielectric strength of ferroelectric or high dielectric thin film or deterioration of polarization characteristic of ferroelectric. Process measures have been needed.

【0005】以下、従来の半導体装置の製造方法につい
て、図面を参照しながら説明する。図4(a)〜(d)
は従来の半導体装置の製造方法を示す工程断面図であ
る。
A conventional method of manufacturing a semiconductor device will be described below with reference to the drawings. 4 (a)-(d)
FIG. 7A is a process sectional view showing the manufacturing method of the conventional semiconductor device.

【0006】以下、従来の半導体装置の製造方法につい
て説明する。まず、図4(a)のように、トランジスタ
2および素子分離用酸化膜15が形成された半導体基板
3上に第1の保護絶縁膜1を形成し、この第1の保護絶
縁膜1上に白金膜などからなる容量素子用下電極4をス
パッタ法や蒸着法で形成し、続いて高誘電体または強誘
電体で構成された容量絶縁膜6を有機金属化学気相成長
法あるいはスパッタ法等で形成し、さらに白金膜などか
らなる容量素子用上電極7をスパッタ法で形成後、最後
に各々の膜をエッチングにて所望の形状に加工し容量素
子5を形成する。
A conventional method of manufacturing a semiconductor device will be described below. First, as shown in FIG. 4A, the first protective insulating film 1 is formed on the semiconductor substrate 3 on which the transistor 2 and the element isolation oxide film 15 are formed, and on the first protective insulating film 1. A lower electrode 4 for a capacitive element made of a platinum film or the like is formed by a sputtering method or a vapor deposition method, and then a capacitive insulating film 6 made of a high dielectric material or a ferroelectric material is formed by a metal organic chemical vapor deposition method or a sputtering method. And the upper electrode 7 for a capacitor element made of a platinum film or the like is formed by the sputtering method, and finally each film is processed into a desired shape by etching to form the capacitor element 5.

【0007】つぎに、図4(b)のように、容量素子5
を覆う第2の保護絶縁膜8として、オゾンを酸化剤と
し、TEOS(Tetraethoxysilane )を用いたシリコン
酸化膜(以下、オゾンTEOS膜と略す)を常圧CVD
法により形成した後、続いてトランジスタ(集積回路)
2および容量素子5へのコンタクトホール9を形成し、
さらに第1の配線層10をスパッタ法等で形成し、さら
にトランジスタ(集積回路)2および容量素子5を電気
的に接続するように第1の配線層10を所望の形状に加
工する。
Next, as shown in FIG. 4B, the capacitive element 5
As the second protective insulating film 8 for covering the surface, a silicon oxide film (hereinafter, abbreviated as ozone TEOS film) using ozone as an oxidizing agent and TEOS (Tetraethoxysilane) is used under atmospheric pressure CVD.
After forming by the method, then the transistor (integrated circuit)
2 and a contact hole 9 to the capacitor 5 is formed,
Further, the first wiring layer 10 is formed by a sputtering method or the like, and further, the first wiring layer 10 is processed into a desired shape so as to electrically connect the transistor (integrated circuit) 2 and the capacitive element 5.

【0008】つぎに、図4(c)のように、配線層間絶
縁膜11を形成する。ここで、配線層間絶縁膜11も、
オゾンを酸化剤とし、TEOS(Tetraethoxysilane )
を用いてシリコン酸化膜(以下、オゾンTEOS膜)を
常圧CVD法により形成するものとする。続いて配線層
間絶縁膜11を貫通して第1の配線層10へのビアホー
ル12を形成し、さらに第2の配線層13をスパッタ法
等で形成し、その後、第1の配線層10を電気的に接続
するように第2の配線層13を所望の形状に加工する。
Next, as shown in FIG. 4C, a wiring interlayer insulating film 11 is formed. Here, the wiring interlayer insulating film 11 is also
Using ozone as an oxidant, TEOS (Tetraethoxysilane)
Is used to form a silicon oxide film (hereinafter referred to as an ozone TEOS film) by an atmospheric pressure CVD method. Subsequently, a via hole 12 is formed through the wiring interlayer insulating film 11 to the first wiring layer 10, a second wiring layer 13 is further formed by a sputtering method, etc., and then the first wiring layer 10 is electrically connected. The second wiring layer 13 is processed into a desired shape so as to be electrically connected.

【0009】最後に、図4(d)のように、容量素子
5、第1の配線層および第2の配線層への水の浸入を防
止するためにプラズマCVD法により形成された耐湿性
の高いシリコン窒化膜などの第3の保護絶縁膜14を形
成する。
Finally, as shown in FIG. 4 (d), a moisture-resistant material formed by a plasma CVD method in order to prevent water from entering the capacitive element 5, the first wiring layer and the second wiring layer. A third protective insulating film 14 such as a high silicon nitride film is formed.

【0010】[0010]

【発明が解決しようとする課題】しかしながら上記の従
来の製造方法では、第2の保護絶縁膜8および配線層間
絶縁膜11としてオゾンTEOS膜を常圧CVD法で形
成する際に発生する水分をオゾンTEOS膜が吸収し、
この水分が以後に続く工程中の加熱処理時に容量素子へ
拡散し、特性劣化をひき起こすという課題を有してい
た。
However, in the above-mentioned conventional manufacturing method, the water generated when the ozone TEOS film is formed as the second protective insulating film 8 and the wiring interlayer insulating film 11 by the atmospheric pressure CVD method is ozone. TEOS film absorbs,
There is a problem in that this moisture diffuses into the capacitive element during the heat treatment in the subsequent steps, causing characteristic deterioration.

【0011】本発明は上記の従来の課題を解決するもの
で、強誘電体または高誘電体を容量絶縁膜とする容量素
子の特性劣化を抑制できる半導体装置の製造方法を提供
することを目的とする。
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing characteristic deterioration of a capacitive element having a ferroelectric or high dielectric as a capacitive insulating film. To do.

【0012】[0012]

【課題を解決するための手段】この目的を達成するため
に、本発明の半導体装置の製造方法は、強誘電体容量素
子又は高誘電体容量素子を覆う絶縁膜を形成後、真空中
で加熱処理を行う。
In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention comprises a method of heating an insulating film covering a ferroelectric capacitor element or a high dielectric capacitor element and heating it in vacuum. Perform processing.

【0013】また、本発明の半導体装置の製造方法にお
いて、真空中で行う加熱処理は、絶縁膜の形成以降に行
われる熱処理のうちの最高温度以下で行うことが好まし
い。
In the method for manufacturing a semiconductor device of the present invention, it is preferable that the heat treatment performed in vacuum is performed at a temperature not higher than the maximum temperature of heat treatments performed after the insulating film is formed.

【0014】また、本発明の半導体装置の製造方法にお
いて、真空中で行う加熱処理は、450℃以下で行うこ
とが好ましい。
Further, in the semiconductor device manufacturing method of the present invention, the heat treatment performed in vacuum is preferably performed at 450 ° C. or lower.

【0015】また、本発明の半導体装置の製造方法にお
いて、真空中で行う加熱処理は、圧力250Pa以下で
行うことが好ましい。
In the method for manufacturing a semiconductor device of the present invention, the heat treatment performed in vacuum is preferably performed at a pressure of 250 Pa or less.

【0016】また、本発明の半導体装置の製造方法にお
いて、絶縁膜は、オゾンを酸化剤としTEOSを原料と
したシリコン酸化膜または、りんを添加したシリコン酸
化膜であることが好ましい。
In the method of manufacturing a semiconductor device of the present invention, the insulating film is preferably a silicon oxide film using ozone as an oxidant and TEOS as a raw material, or a silicon oxide film to which phosphorus is added.

【0017】このような構成により、真空中に水分が放
出され、オゾンTEOS膜の膜中の水分が減少し、以後
に続く工程中の加熱処理時におけるオゾンTEOS膜か
らの容量素子への水分の拡散を低減し、特性劣化を抑制
することができる。
With such a structure, moisture is released into the vacuum, the moisture in the ozone TEOS film is reduced, and the moisture from the ozone TEOS film to the capacitive element during the heat treatment in the subsequent steps is reduced. It is possible to reduce diffusion and suppress characteristic deterioration.

【0018】[0018]

【発明の実施の形態】以下本発明の一実施形態につい
て、図面を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

【0019】図1(a)〜(d)は本発明の実施形態に
おける容量素子を内蔵した半導体装置の製造方法を示す
工程断面図である。
FIGS. 1A to 1D are process sectional views showing a method of manufacturing a semiconductor device having a built-in capacitor according to an embodiment of the present invention.

【0020】以下、本発明の実施形態における半導体装
置の製造方法について説明する。
A method of manufacturing a semiconductor device according to the embodiment of the present invention will be described below.

【0021】まず、図1(a)のように、トランジスタ
102および素子分離用酸化膜115が形成された半導
体基板103上に第1の保護絶縁膜101を形成し、こ
の第1の保護絶縁膜101上に白金膜などからなる容量
素子用下電極104をスパッタ法や蒸着法で形成し、続
いて高誘電体または強誘電体で構成された容量絶縁膜1
06を有機金属化学気相成長法あるいはスパッタ法等で
形成し、さらに白金膜などからなる容量素子用上電極1
07をスパッタ法で形成後、最後に各々の膜をエッチン
グにて所望の形状に加工し容量素子105を形成する。
First, as shown in FIG. 1A, a first protective insulating film 101 is formed on a semiconductor substrate 103 having a transistor 102 and an element isolation oxide film 115 formed thereon. A capacitive element lower electrode 104 made of a platinum film or the like is formed on 101 by a sputtering method or a vapor deposition method, and subsequently a capacitive insulating film 1 made of a high dielectric material or a ferroelectric material.
06 is formed by a metal organic chemical vapor deposition method, a sputtering method, or the like, and is further formed of a platinum film or the like.
After forming 07 by a sputtering method, finally, each film is processed into a desired shape by etching to form the capacitor 105.

【0022】つぎに、図1(b)のように、容量素子1
05を覆う第2の保護絶縁膜108として、オゾンTE
OS膜を常圧CVD法により形成する。ここで、本発明
では、半導体基板103に対して圧力250Paの真空
中で300℃の加熱処理を行い、第2の保護絶縁膜10
8の膜中水分を真空中に放出させる。
Next, as shown in FIG. 1B, the capacitive element 1
As a second protective insulating film 108 that covers 05, ozone TE
The OS film is formed by the atmospheric pressure CVD method. Here, in the present invention, the semiconductor substrate 103 is subjected to heat treatment at 300 ° C. in a vacuum with a pressure of 250 Pa, and the second protective insulating film 10 is formed.
The moisture in the film of No. 8 is released into vacuum.

【0023】その後、続いてトランジスタ(集積回路)
102および容量素子105へのコンタクトホール10
9を形成し、さらに第1の配線層110をスパッタ法等
で形成し、さらにトランジスタ(集積回路)102およ
び容量素子105を電気的に接続するように第1の配線
層110を所望の形状に加工する。
After that, subsequently, a transistor (integrated circuit)
Contact hole 10 to 102 and capacitor 105
9, the first wiring layer 110 is further formed by a sputtering method or the like, and the first wiring layer 110 is formed into a desired shape so as to electrically connect the transistor (integrated circuit) 102 and the capacitor 105. To process.

【0024】つぎに、図1(c)のように、配線層間絶
縁膜111を形成する。ここで、配線層間絶縁膜111
は、オゾンTEOS膜を常圧CVD法により形成するも
のとする。ここでさらに、本発明では、半導体基板10
3に対して圧力250Paの真空中で300℃の加熱処
理を行い、配線層間絶縁膜111の膜中水分を真空中に
放出させる。
Next, as shown in FIG. 1C, a wiring interlayer insulating film 111 is formed. Here, the wiring interlayer insulating film 111
In this case, the ozone TEOS film is formed by the atmospheric pressure CVD method. Here, further, in the present invention, the semiconductor substrate 10
3 is heat-treated at 300 ° C. in a vacuum with a pressure of 250 Pa to release moisture in the film of the wiring interlayer insulating film 111 into the vacuum.

【0025】続いて配線層間絶縁膜111を貫通して第
1の配線層110へのビアホール112を形成し、さら
に第2の配線層113をスパッタ法等で形成し、その
後、第1の配線層110を電気的に接続するように第2
の配線層113を所望の形状に加工する。そして、加工
した第2の配線層113の腐食防止のために350℃の
窒素雰囲気中で30分間加熱処理を行う。
Subsequently, a via hole 112 is formed through the wiring interlayer insulating film 111 to the first wiring layer 110, a second wiring layer 113 is further formed by a sputtering method, etc., and then the first wiring layer is formed. Second to connect 110 electrically
The wiring layer 113 is processed into a desired shape. Then, in order to prevent corrosion of the processed second wiring layer 113, heat treatment is performed for 30 minutes in a nitrogen atmosphere at 350 ° C.

【0026】最後に、図1(d)のように、容量素子1
05、第1の配線層110および第2の配線層113へ
の水の浸入を防止するためにプラズマCVD法により4
00℃の成膜温度で形成された耐湿性の高いシリコン窒
化膜などの第3の保護絶縁膜114を形成する。
Finally, as shown in FIG. 1D, the capacitive element 1
05, by the plasma CVD method in order to prevent water from entering the first wiring layer 110 and the second wiring layer 113.
A third protective insulating film 114 such as a silicon nitride film having high moisture resistance formed at a film forming temperature of 00 ° C. is formed.

【0027】次に、常圧CVD法により形成したオゾン
TEOS膜に含まれる水分の昇温脱離量に関する測定結
果について、図2を参照しながら説明する。
Next, the measurement results regarding the amount of temperature-programmed desorption of water contained in the ozone TEOS film formed by the atmospheric pressure CVD method will be described with reference to FIG.

【0028】図2の横軸は温度を、縦軸はその温度で放
出される水分量をそれぞれ示しており、これらの関係が
水分の吸着の強さに対応している。図2に示すように、
TEOS膜に吸着した水分が離脱するピーク温度は、第
1のピークが350℃〜450℃、第2のピークが65
0℃〜750℃にある。このうち、第2のピークに相当
する水分は充分強い吸着力でオゾンTEOS膜に吸着し
ているため、半導体装置の配線製造過程における450
℃以下の加熱処理では、特性にはほとんど影響しないと
考えられる。それに対して、第1のピークは350℃〜
450℃にあるため、吸着水が放出され水分の容量素子
への拡散により特性が劣化する危険性が高い。
The horizontal axis of FIG. 2 represents temperature, and the vertical axis represents the amount of water released at that temperature. These relationships correspond to the strength of water adsorption. As shown in FIG.
Regarding the peak temperature at which the water adsorbed on the TEOS film desorbs, the first peak is 350 ° C. to 450 ° C. and the second peak is 65 ° C.
It is between 0 ° C and 750 ° C. Of these, the moisture corresponding to the second peak is adsorbed to the ozone TEOS film with a sufficiently strong adsorbing power, so that it is 450 in the wiring manufacturing process of the semiconductor device.
It is considered that the heat treatment at a temperature of ℃ or less has almost no effect on the characteristics. On the other hand, the first peak is 350 ℃ ~
Since the temperature is 450 ° C., the adsorbed water is released, and there is a high risk that the characteristics will deteriorate due to the diffusion of water into the capacitive element.

【0029】以上に示したオゾンTEOS膜に含まれる
水分の昇温脱離量に関する測定結果は、大気圧中で行っ
たものであるが、我々は、真空中で加熱処理をすれば上
記の第1のピークよりもさらに低温でオゾンTEOS膜
に含まれる水分を脱離できると考え、第2の保護絶縁膜
108および配線層間絶縁膜111として常圧CVD法
でオゾンTEOS膜を成膜した後に、オゾンTEOS膜
の膜中水分を減少させることを目的として、250Pa
の真空中で120分間半導体基板を200℃で加熱し、
真空中に膜中水分を放出させることを行った。
The above-mentioned measurement results regarding the temperature-programmed desorption amount of the water contained in the ozone TEOS film are obtained under the atmospheric pressure. Considering that water contained in the ozone TEOS film can be desorbed at a temperature lower than the peak of 1, after forming the ozone TEOS film by the atmospheric pressure CVD method as the second protective insulating film 108 and the wiring interlayer insulating film 111, 250 Pa for the purpose of reducing moisture in the ozone TEOS film
The semiconductor substrate at 200 ° C for 120 minutes in the vacuum of
The moisture in the film was released in vacuum.

【0030】この結果を、図3を参照しながら説明す
る。
The results will be described with reference to FIG.

【0031】ここでは、オゾンTEOS膜を成膜後に真
空中で加熱処理を行った半導体基板上の容量素子の特性
と、真空中で加熱処理を行わなかった半導体基板上の容
量素子の特性について、強誘電体容量素子の残留分極率
で比較した。
Here, the characteristics of the capacitive element on the semiconductor substrate which was heat-treated in vacuum after forming the ozone TEOS film and the characteristics of the capacitive element on the semiconductor substrate which was not heat-treated in vacuum were described. The residual polarizability of the ferroelectric capacitors was compared.

【0032】図3は、オゾンTEOS膜を成膜後に真空
中で加熱処理を行った半導体基板上の容量素子と、真空
中で加熱処理を行わなかった半導体基板上の容量素子の
残留分極量をそれぞれ示している。
FIG. 3 shows the residual polarization amounts of the capacitive element on the semiconductor substrate which was heat-treated in vacuum after forming the TEOS ozone film and the capacitive element on the semiconductor substrate which was not heat-treated in vacuum. Shown respectively.

【0033】オゾンTEOS膜を成膜後に真空中で加熱
処理を行った半導体基板上の容量素子と真空中で加熱処
理を行わなかった半導体基板上の容量素子とを比較する
と、真空中で加熱処理を行った半導体基板上の容量素子
は特性が向上していることがわかる。これはオゾンTE
OS膜に含まれる水分が、大気中におけるよりも真空中
において、より低温で脱離するために、第2の保護絶縁
膜および配線層間絶縁膜としてのオゾンTEOS膜の膜
中に存在する水分がより減少し、以後の工程における加
熱処理時に容量素子への水分の拡散をさらに低減するこ
とができ、容量素子の特性劣化を抑制したためと考える
ことができる。
Comparing the capacitive element on the semiconductor substrate which is heat-treated in vacuum after forming the ozone TEOS film with the capacitive element on the semiconductor substrate which is not heat-treated in vacuum, heat treatment in vacuum is performed. It can be seen that the characteristics of the capacitive element on the semiconductor substrate subjected to the above are improved. This is Ozone TE
Since moisture contained in the OS film is desorbed at a lower temperature in vacuum than in the atmosphere, moisture present in the second protective insulating film and the ozone TEOS film as the wiring interlayer insulating film is removed. It can be considered that this is because the amount of water is further reduced, and the diffusion of water into the capacitor during the heat treatment in the subsequent steps can be further reduced, and the characteristic deterioration of the capacitor is suppressed.

【0034】なお、上記の実施形態ではオゾンTEOS
膜を第2の保護絶縁膜および配線層間絶縁膜として用い
た場合について説明したが、言うまでもなくいずれか一
方の膜としてのみオゾンTEOS膜を用いても、その後
に真空中で加熱処理することで同様の効果を得ることが
できる。
In the above embodiment, ozone TEOS is used.
Although the case where the film is used as the second protective insulating film and the wiring interlayer insulating film has been described, needless to say, even if the ozone TEOS film is used as only one of the films, the same applies when the heat treatment is performed in a vacuum thereafter. The effect of can be obtained.

【0035】また、この実施形態ではオゾンTEOS膜
を第2の保護絶縁膜および配線層間絶縁膜として用い、
かつ配線層間絶縁膜が1層の場合について説明したが、
多層配線におけるさらに上層の配線層間絶縁膜に用いた
場合でも同様に成立する。
In this embodiment, the ozone TEOS film is used as the second protective insulating film and the wiring interlayer insulating film,
Moreover, the case where the wiring interlayer insulating film is one layer has been described.
The same holds true when it is used for a wiring interlayer insulating film which is an upper layer in a multilayer wiring.

【0036】また、この実施形態ではオゾンTEOS膜
を第2の保護絶縁膜および配線層間絶縁膜として用いた
場合について説明したが、りんを添加したシリコン酸化
膜あるいはボロンを添加したシリコン酸化膜も高い吸水
性を有するため、これらを第2の保護絶縁膜および配線
層間絶縁膜として用いた場合について、真空中での加熱
処理によってオゾンTEOS膜の場合と同様の効果を得
ることができる。
In this embodiment, the case where the ozone TEOS film is used as the second protective insulating film and the wiring interlayer insulating film has been described, but a silicon oxide film containing phosphorus or a silicon oxide film containing boron is also high. Since they have water absorbency, when these are used as the second protective insulating film and the wiring interlayer insulating film, the same effect as that of the ozone TEOS film can be obtained by the heat treatment in vacuum.

【0037】[0037]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、真空中での加熱処理によって、オゾンTEOS膜の
膜中水分を減少させることができ、以後の工程における
加熱処理時に容量素子への水分の拡散を低減することが
でき、容量素子の特性劣化を抑制することができる。
According to the method of manufacturing a semiconductor device of the present invention, the moisture in the film of the ozone TEOS film can be reduced by the heat treatment in vacuum, and the capacitance element can be removed during the heat treatment in the subsequent steps. It is possible to reduce the diffusion of moisture and suppress the characteristic deterioration of the capacitive element.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態における半導体装置の製造方
法の工程順断面図
FIG. 1 is a cross-sectional view in order of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】オゾンTEOS膜からの水の昇温脱離量を示す
FIG. 2 is a diagram showing a temperature rise desorption amount of water from an ozone TEOS film.

【図3】本発明の実施形態と従来例とにおける残留分極
量の差を示す特性図
FIG. 3 is a characteristic diagram showing a difference in remanent polarization amount between the embodiment of the present invention and a conventional example.

【図4】従来例における半導体装置の製造方法の工程順
断面図
FIG. 4 is a cross-sectional view in order of steps of a method for manufacturing a semiconductor device in a conventional example.

【符号の説明】[Explanation of symbols]

1 第1の保護絶縁膜 2 トランジスタ 3 半導体基板 4 容量素子用下電極 5 容量素子 6 容量絶縁膜 7 容量素子用上電極 8 第2の保護絶縁膜 9 コンタクトホール 10 第1の配線層 11 配線層間絶縁膜 12 ビアホール 13 第2の配線層 14 第3の保護絶縁膜 15 素子分離用酸化膜 101 第1の保護絶縁膜 102 トランジスタ 103 半導体基板 104 容量素子用下電極 105 容量素子 106 容量絶縁膜 107 容量素子用上電極 108 第2の保護絶縁膜 109 コンタクトホール 110 第1の配線層 111 配線層間絶縁膜(真空加熱処理) 112 ビアホール 113 第2の配線層 114 第3の保護絶縁膜 115 素子分離用酸化膜 1 First protective insulating film 2 transistors 3 Semiconductor substrate 4 Lower electrode for capacitive element 5 capacitive elements 6 Capacitance insulating film 7 Upper electrode for capacitive element 8 Second protective insulating film 9 contact holes 10 First wiring layer 11 Wiring interlayer insulation film 12 beer hall 13 Second wiring layer 14 Third protective insulating film 15 Element isolation oxide film 101 First protective insulating film 102 transistor 103 semiconductor substrate 104 Lower electrode for capacitive element 105 Capacitive element 106 Capacitance insulating film 107 Upper electrode for capacitance element 108 Second protective insulating film 109 contact holes 110 First wiring layer 111 Wiring interlayer insulation film (vacuum heat treatment) 112 beer hall 113 Second wiring layer 114 Third protective insulating film 115 Device isolation oxide film

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 強誘電体容量素子又は高誘電体容量素子
を覆う絶縁膜を形成後、真空中で加熱処理を行うことを
特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: performing heat treatment in a vacuum after forming an insulating film covering a ferroelectric capacitor element or a high dielectric capacitor element.
【請求項2】 前記真空中で行う加熱処理は、前記絶縁
膜の形成以降に行われる熱処理のうちの最高温度以下で
行うことを特徴とする請求項1記載の半導体装置の製造
方法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment performed in the vacuum is performed at a temperature not higher than a maximum temperature of heat treatments performed after the insulating film is formed.
【請求項3】 前記真空中で行う加熱処理は、300℃
以下で行うことを特徴とする請求項1記載の半導体装置
の製造方法。
3. The heat treatment performed in the vacuum is 300 ° C.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed as follows.
【請求項4】 前記真空中で行う加熱処理は、圧力25
0Pa以下で行うことを特徴とする請求項1記載の半導
体装置の製造方法。
4. The heat treatment performed in the vacuum is performed at a pressure of 25.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed at 0 Pa or less.
【請求項5】 前記絶縁膜は、オゾンを酸化剤としTE
OSを原料としたシリコン酸化膜、りんを添加したシリ
コン酸化膜、あるいはボロンを添加したシリコン酸化膜
であることを特徴とする請求項1記載の半導体装置の製
造方法。
5. The insulating film uses ozone as an oxidant and TE
2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon oxide film is made of OS as a raw material, the silicon oxide film is doped with phosphorus, or the silicon oxide film is doped with boron.
JP2002120445A 2002-04-23 2002-04-23 Method of manufacturing semiconductor device Pending JP2003318173A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002120445A JP2003318173A (en) 2002-04-23 2002-04-23 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002120445A JP2003318173A (en) 2002-04-23 2002-04-23 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2003318173A true JP2003318173A (en) 2003-11-07

Family

ID=29536666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002120445A Pending JP2003318173A (en) 2002-04-23 2002-04-23 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2003318173A (en)

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