JP2003318161A - Device and method for plasma treatment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and method for plasma treatment by which the occurrence of failures can be prevented by holding a semiconductor substrate with sufficient electrostatic holding power. <P>SOLUTION: In the plasma treatment device which performs plasma treatment on a silicon wafer 6 while a protective tape 6a is stuck to the circuit forming surface of the wafer 6, the wafer 6 is placed on a placing surface 3d on the upper surface of a lower electrode 3 made of a conductive metal, with the protective tape 6a on the placing surface 3d side. When the wafer 6 is held by the lower electrode 3 by electrostatic attraction by impressing a DC voltage upon the electrode 3 from a DC power source section 18 for electrostatic attraction at the time of performing the plasma treatment, the protective tape 6a is utilized as a dielectric for electrostatic attraction. Consequently, the silicon wafer 6 can be held with sufficient electrostatic holding power, because the thickness of the can be reduced to the utmost. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma processing apparatus and a plasma processing method for plasma processing a semiconductor substrate such as a silicon wafer.

[0002]

2. Description of the Related Art In a manufacturing process of a silicon wafer used for a semiconductor device, a thinning process is performed to reduce the thickness of a substrate as the semiconductor device is made thinner. This thinning process is performed by mechanically polishing the back surface of the circuit formation surface after forming a circuit pattern on the surface of the silicon substrate, and after the polishing process, a damage layer generated on the polished surface of the silicon substrate by mechanical polishing. A plasma treatment is performed for the purpose of removing by etching.

In this plasma processing, since it is necessary to hold the silicon wafer with the surface to be processed (rear surface) facing upward, the circuit formation surface side of the silicon wafer faces the mounting surface of the substrate mounting portion. Hold in a posture. At this time, a protective tape is attached to the circuit forming surface in order to prevent the circuit from directly contacting the mounting surface and being damaged.

[0004]

As a method of holding such a silicon wafer, a method by electrostatic attraction is known. In this method, a silicon wafer is placed on a substrate mounting portion whose surface of a conductor is covered with a thin insulating layer, and a DC voltage is applied to the conductor to make the surface of the substrate mounting portion an electrostatic attraction surface. The Coulomb force is applied between the silicon wafer and the conductor below the insulating layer to hold the silicon wafer on the substrate mounting portion.

However, when the silicon wafer to which the above-mentioned protective tape is adhered is held by electrostatic attraction, the Coulomb force acts in a state in which an insulating protective tape is interposed in addition to the insulating layer. Therefore, compared with the case where the silicon wafer is directly adhered to the electrostatic attraction surface without using the protective tape, the electrostatic attraction force may be low and sufficient holding force may not be obtained. In addition to this, when a resin layer is formed on the surface of the silicon wafer for the purpose of sealing, wiring, etc. The problem occurs.

Therefore, an object of the present invention is to provide a plasma processing apparatus and a plasma processing method capable of holding a semiconductor substrate with a sufficient electrostatic holding force to prevent defects.

[0007]

A plasma processing apparatus according to claim 1 is a plasma processing apparatus for performing a plasma processing on a semiconductor substrate having an insulating layer formed of a resin tape attached to the surface thereof. A substrate mounting portion is provided on a part of which a conductive surface is exposed, and the semiconductor substrate is mounted with the insulating layer side facing this mounting surface, and the semiconductor substrate is electrostatically mounted on the mounting surface. An electrostatic chucking means for holding the semiconductor substrate mounted on the mounting surface is provided, and a plasma generating means for generating a plasma to process the semiconductor substrate mounted on the mounting surface. Use as a body.

According to a second aspect of the present invention, there is provided a plasma processing method in which a semiconductor substrate having an insulating layer formed of a resin tape attached to a surface thereof is held by electrostatic attraction on a mounting surface of a substrate mounting portion. A plasma processing method for performing a treatment, wherein at least a part of the mounting surface is a conductor, and the insulating layer is mounted with the insulating layer side of the semiconductor substrate facing the mounting surface of the substrate mounting portion. The semiconductor substrate is electrostatically adsorbed on the mounting surface by being used as the dielectric of the electrostatic adsorption means.

According to the present invention, the mounting surface of the substrate mounting portion is made of a conductor, and the insulating layer side of the semiconductor substrate is mounted with the mounting surface facing the mounting surface to electrostatically attract the insulating layer of the semiconductor substrate. The semiconductor substrate can be held with a sufficient electrostatic holding force by electrostatically adsorbing the semiconductor substrate to the mounting surface by using it as a dielectric of the above.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. 1 is a sectional view of a plasma processing apparatus according to an embodiment of the present invention, FIG. 2 is a sectional view of a substrate mounting portion of the plasma processing apparatus according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a cross-sectional view of a plasma processing apparatus according to an embodiment of the present invention, FIG. 4 is a graph showing electrostatic attraction force in the plasma processing apparatus according to one embodiment of the present invention, and FIG. 6 and 7 are process explanatory diagrams of the plasma processing method according to the embodiment of the present invention, and FIG. 8 is a diagram showing the substrate mounting portion of the plasma processing apparatus according to the embodiment of the present invention.

First, the plasma processing apparatus will be described with reference to FIGS. In FIG. 1, the inside of a vacuum chamber 1 is a processing chamber 2 for performing plasma processing, and inside the processing chamber 2, a lower electrode 3 and an upper electrode 4 are vertically opposed to each other. The lower electrode 3 is attached to the vacuum chamber 1 in an electrically insulated state by a support portion 3a extending downward, and the upper electrode 4 is electrically connected to the vacuum chamber 1 by a support portion 4a extending upward. It is installed. On the lower surface of the upper electrode 4, a gas blowout portion (not shown) that blows out a gas for plasma generation is formed.
The gas blowing part is connected to a plasma generating gas supply part (not shown) for supplying a fluorine generating gas or a plasma generating gas mainly containing a fluorine containing gas.

The lower electrode 3 is made of a conductive metal, and the upper surface of the lower electrode 3 is substantially the same as the planar shape of the silicon wafer 6 (FIG. 2), which is the semiconductor substrate of the object to be processed, and the semiconductor substrate is mounted thereon. It is a mounting surface 3d on which to place.
Therefore, the lower electrode 3 is a substrate mounting portion on which a mounting surface on which the conductor is exposed is provided and on which the semiconductor substrate is mounted. Here, the silicon wafer 6 is in a state immediately after the back side of the circuit forming surface is polished by mechanical polishing. As shown in FIG. 2, the protective tape 6a attached to the circuit forming surface of the silicon wafer 6 is attached to the lower electrode 3. It is placed with the mechanical polishing surface facing upwards toward the placement surface 3d. Then, the mechanically polished surface is plasma-treated to remove the damaged layer generated by the polishing process.

The protective tape 6a is a resin tape in which an insulating resin such as polyolefin, polyimide or polyethylene terephthalate is formed into a film having a thickness of about 100 μm, and is adhered to the circuit forming surface of the silicon wafer 6 with an adhesive material. . Protective tape 6 attached to silicon wafer 6
Reference numeral a denotes an insulating layer formed on the circuit forming surface (front surface), and this insulating layer functions as a dielectric when the silicon wafer 6 is electrostatically adsorbed, as described later.

A gate valve 1a for loading and unloading the substrate is provided on the side surface of the vacuum chamber 1, and the gate valve 1a is opened and closed by a gate opening / closing mechanism (not shown). An exhaust pump 8 is provided in the vacuum chamber 1 via a valve opening mechanism 7.
Are connected to the vacuum chamber 1 by opening the valve opening mechanism 7 and driving the exhaust pump 8.
The inside of the processing chamber 2 is evacuated. Then, by opening the atmosphere opening mechanism 9, the atmosphere is introduced into the processing chamber 2 and the vacuum is broken.

The atmosphere opening mechanism 9 may be one that introduces the outside air into the vacuum chamber 1 as it is, but when a gas containing a large amount of moisture is used, the moisture adheres to the inner wall of the vacuum chamber 1 and is prone to the next evacuation. It may take time. Therefore, it is preferable to introduce dry air that has been subjected to dehumidification treatment or a gas with a low humidity such as nitrogen gas.

As shown in FIG. 2, the lower electrode 3 is provided with a large number of adsorption holes 3e opening on the upper surface thereof.
Communicates with a suction hole 3b provided inside the lower electrode 3. The suction hole 3b is connected to the vacuum adsorption pump 12 via the gas line switching opening / closing mechanism 11, and the gas line switching opening / closing mechanism 11 is connected to the N ₂ gas supply unit 13 and the He gas supply unit 14 as shown in FIG. It is connected.
By switching the gas line switching opening / closing mechanism 11, the suction hole 3b can be selectively connected to the vacuum adsorption pump 12, the N ₂ gas supply unit 13, and the He gas supply unit 14.

By driving the vacuum suction pump 12 with the suction hole 3b communicating with the vacuum suction pump 12, the silicon wafer 6 mounted on the mounting surface 3d is vacuum-sucked by vacuum suction from the suction hole 3e. Hold. Therefore, the suction holes 3e, the suction holes 3b, and the vacuum suction pump 12 serve as a vacuum holding unit that vacuum-sucks the plate-shaped substrate and holds it on the mounting surface 3d by vacuum suction from the suction holes 3e opened on the mounting surface 3d. ing.

Further, by connecting the suction hole 3b to the N ₂ gas supply unit 13 or the He gas supply unit 14, it is possible to eject nitrogen gas or helium gas from the adsorption hole 3e to the lower surface of the silicon wafer 6. It has become. As will be described later, the nitrogen gas is a blowing gas for the purpose of forcibly separating the silicon wafer 6 from the mounting surface 3d, and the helium gas is a heat transfer gas used for promoting the cooling of the silicon wafer during plasma processing. It is gas.

The lower electrode 3 has a coolant flow path 3c for cooling.
Is provided, and the coolant channel 3c is connected to the cooling mechanism 10. By driving the cooling mechanism 10, a coolant such as cooling water circulates in the coolant channel 3c, and thereby the lower electrode 3 is heated by the heat generated during plasma processing.
The protective tape 6a on the lower electrode 3 is cooled. The coolant channel 3c and the cooling mechanism 10 serve as a cooling unit that cools the lower electrode 3 that is the substrate mounting portion.

The lower electrode 3 is electrically connected to a high frequency power source section 17 via a matching circuit 16. By driving the high frequency power supply unit 17, the upper electrode 4 and the lower electrode 3 which are electrically connected to the vacuum chamber 1 grounded to the grounding unit 19 are connected.
A high-frequency voltage is applied during this period, which causes plasma discharge in the processing chamber 2. The matching circuit 16 is
The impedance of the plasma discharge circuit for generating plasma in the processing chamber 2 and the impedance of the high frequency power supply unit 17 are matched. The lower electrode 3, the upper electrode 4, and the high-frequency power supply unit 17 are plasma generating means for generating plasma for plasma-processing the silicon wafer 6 mounted on the mounting surface.

Here, as the plasma generating means,
Opposed parallel plate electrodes (lower electrode 3 and upper electrode 4)
Although an example of a method of applying a high-frequency voltage is shown in between, a method other than this, for example, a method of providing a plasma generator in the upper part of the processing chamber 2 and sending plasma into the processing chamber 2 by a downflow method may be used. .

A DC power supply 18 for electrostatic attraction is connected to the lower electrode 3 via an RF filter 15. By driving the DC power supply unit 18 for electrostatic attraction, as shown in FIG.
As shown in (a), negative charges are accumulated on the surface of the lower electrode 3. Then, in this state, as shown in FIG. 3B, the high-frequency power supply 17 is driven to generate plasma in the processing chamber 2 (see the dotted portion 20 in the drawing), so that the mounting surface 3d
A direct current application circuit 21 that connects the silicon wafer 6 placed on the substrate to the grounding portion 19 is formed via the plasma in the processing chamber 2, whereby the lower electrode 3, the RF filter 15,
A closed circuit that sequentially connects the electrostatic attraction DC power supply unit 18, the ground unit 19, the plasma, and the silicon wafer 6 is formed, and positive charges are accumulated in the silicon wafer 6.

A Coulomb force acts between the negative charges accumulated in the lower electrode 3 and the positive charges accumulated in the silicon wafer 6, and the Coulomb force causes the silicon wafer 6
Are held by the lower electrode 3 via a protective tape 6a as a dielectric. At this time, the RF filter 15 prevents the high frequency voltage of the high frequency power supply unit 17 from being directly applied to the electrostatic attraction DC power supply unit 18. The lower electrode 3 and the DC power source 18 for electrostatic attraction serve as electrostatic attraction means for holding the silicon wafer 6, which is a plate-shaped substrate, on the mounting surface 3d by electrostatic attraction. The polarity of the electrostatic attraction DC power supply unit 18 may be reversed.

Here, the electrostatic attraction force will be described with reference to FIG. Adsorption force F due to Coulomb force is F = 1/2
given by ε (V / d) 2. Here, ε is the dielectric constant of the dielectric, V is the applied DC voltage, and d is the thickness of the dielectric. FIG. 4 shows a protective tape 6a made of resin.
Is attached to a silicon wafer 6, and the electrostatic attraction force when this protective tape 6a is used as a dielectric in electrostatic attraction is shown in relation to the applied DC voltage.

In this case, curves a, b and c are shown by curves a, b and c, respectively, when three kinds of resin materials of the protective tape 6a, that is, polyolefin, polyimide and polyethylene terephthalate are used and each is manufactured with a thickness of 100 μm. The curve d is a comparison of the electrostatic attraction force when an alumina insulating layer is formed with a thickness of 200 μm on the substrate mounting surface and is used as a dielectric for electrostatic attraction to electrostatically attract a silicon wafer without a protective tape. Is shown for.

As shown in FIG. 4, the example of polyolefin has almost the same adsorptive force as that of the conventional alumina insulating layer. When two kinds of materials, polyimide and polyethylene terephthalate, are used, the alumina insulating layer is used. It is shown that a larger adsorption force than that obtained when using the layer is obtained.

That is, it is possible to realize a good adsorption force without forming an insulating layer on the lower electrode, which is required when performing electrostatic adsorption in the conventional plasma processing apparatus. . Further, since the protective tape is brought into direct contact with the surface of the lower electrode 3 without interposing an insulating layer such as alumina having a poor thermal conductivity, a good cooling effect can be obtained, and the heat applied to the protective tape 6a and the silicon wafer 6 can be prevented. You can reduce the damage.

This plasma processing apparatus is configured as described above, and the plasma processing method will be described below with reference to FIGS. 6 and 7 along the flow of FIG. In FIG. 5, first, the silicon wafer 6, which is the object to be processed, is transferred into the processing chamber 2 (ST1), and the placement surface 3d of the lower electrode 3 is placed.
It is placed on (placement step). At this time, since the silicon wafer 6 is thin and easily bent, there is a case where the silicon wafer 6 is mounted in a state where it is warped to form a gap with the mounting surface 3d as shown in FIG. 6 (a). After that, the gate valve 1a is closed (ST2), and the vacuum suction pump 12 is driven to move the suction holes 3e and the suction holes 3 as shown in FIG. 6 (b).
Vacuum suction is performed via b, and the vacuum suction state of the silicon wafer 6 is turned on (ST3). As a result, as shown in FIG. 6C, the silicon wafer 6 is held by vacuum suction while being in close contact with the mounting surface 3d (holding step).

Then, the exhaust pump 8 is driven to drive the processing chamber 2
The inside is evacuated and the plasma generating gas is supplied from the gas outlet of the upper electrode 4 (ST4). Thereafter, the DC power source 18 for electrostatic attraction is driven to turn off the application of the DC voltage.
Then, the high frequency power supply unit 17 is driven to start plasma discharge (ST6). As a result, plasma is generated in the space between the silicon wafer 6 on the lower electrode 3 and the lower surface of the upper electrode 4 as shown in FIG. 7A, and plasma processing is performed on the silicon wafer 6 ( Plasma treatment step). In this plasma treatment, the lower electrode 3
An electrostatic attraction force is generated between the silicon wafer 6 and the silicon wafer 6 (see FIG. 3B), and the silicon wafer 6 is held by the lower electrode 3 by the electrostatic attraction force.

After this, the gas line switching opening / closing mechanism 11
To turn off the vacuum suction (ST7), and back He
Introduction is performed (ST8). That is, after the holding of the silicon wafer 6 to the lower electrode 3 by vacuum suction is released, helium gas for heat transfer is supplied from the He gas supply unit 14 through the suction holes 3b, and as shown in FIG. Then, it is ejected from the suction holes 3e to the lower surface of the silicon wafer 6. In this plasma treatment, the lower electrode 3 is cooled by the cooling mechanism 10, and the heat of the silicon wafer 6 which has been heated by the plasma treatment is transferred to the lower electrode 3 via the helium gas which is a gas having a high heat conductivity. As a result, the silicon wafer 6 is efficiently cooled.

When the discharge is completed after the lapse of a predetermined plasma processing time (ST9), the back He is stopped (ST10), and the vacuum adsorption is turned on again as shown in FIG. 7B (ST11). . As a result, the silicon wafer 6 is held on the mounting surface 3d by the vacuum attraction force instead of the electrostatic attraction force that disappears when the plasma discharge is completed.

Thereafter, the electrostatic attraction DC power supply unit 18 is stopped to turn off the DC voltage (ST12), and the atmosphere opening mechanism 9 is driven to open the atmosphere in the processing chamber 2 (ST1).
3).

After that, the gas line switching opening / closing mechanism 11 is driven again to turn off the vacuum suction (ST14), and then the wafer is blown (ST15). That is, FIG.
As shown in (c), nitrogen gas is supplied through the suction holes 3b and ejected from the adsorption holes 3e. As a result, the silicon wafer 6 is separated from the mounting surface 3d of the lower electrode 3.
If the gate valve 1a is opened (ST16) and the silicon wafer 6 is transferred to the outside of the processing chamber 2 (S16).
T17), the wafer blow is turned off (ST18), and one cycle of plasma processing is completed.

As described above, in the plasma processing shown in this embodiment, the plasma is generated in the processing chamber 2 and the lower electrode 3 of the silicon wafer 6 is held until the electrostatic attraction force is generated. This is done by vacuum adsorption. As a result, even when a thin and flexible plate-like substrate such as the silicon wafer 6 is targeted, the silicon wafer 6 can be always brought into close contact with the mounting surface 3d of the lower electrode 3 and appropriately held. Therefore, in the case of poor adhesion, it is possible to prevent abnormal discharge that occurs in the gap between the upper surface of the lower electrode 3 and the lower surface of the silicon wafer 6 and overheating of the silicon wafer 6 due to poor cooling.

As the lower electrode, a lower electrode 3'as shown in FIG. 8 may be used instead of the lower electrode 3 whose entire mounting surface 3d is made of a conductor. In this example, as shown in FIG. 8A, the mounting surface 3′d is larger than the silicon wafer 6 which is a semiconductor substrate, and an insulating portion 3′f having a predetermined width is formed at the outer edge portion protruding from the size of the silicon wafer 6. Has been done. The insulating portion 3'f is made of ceramic such as alumina, and its planar shape is determined according to the shape of the silicon wafer mounted on the mounting surface 3'd. FIG. 8 (b),
(C) shows an example of the shape of the insulating portion 3'f in each of the case where there is no oriental flat indicating the direction of the silicon wafer and the case where there is oriental flat.

By using such a lower electrode 3 ', the conductor on the upper surface of the lower electrode 3'is not directly exposed to the plasma while the silicon wafer is placed, and the lower electrode 3' There is an advantage that plasma discharge can be generated more uniformly on the mounting surface.

In the above embodiment, an example in which the resin protective tape 6a adhered to the silicon wafer 6 is used as the insulating layer to serve as an electrostatically attracting dielectric is shown. The present invention can also be applied to a case where an insulating resin layer formed on the surface for the purpose of sealing, wiring, or the like is brought into close contact with the electrostatic attraction surface for electrostatic attraction.

[0038]

According to the present invention, the mounting surface of the substrate mounting portion is made to be a conductor, and the insulating layer side of the semiconductor substrate is mounted with the mounting surface facing toward the mounting surface so that the insulating layer of the semiconductor substrate is electrostatically charged. The semiconductor substrate can be held with a sufficient electrostatic holding force by electrostatically attracting the semiconductor substrate to the mounting surface by using it as a dielectric of the attraction means.

[Brief description of drawings]

FIG. 1 is a sectional view of a plasma processing apparatus according to an embodiment of the present invention.

FIG. 2 is a sectional view of a substrate mounting portion of the plasma processing apparatus according to the embodiment of the present invention.

FIG. 3 is a sectional view of a plasma processing apparatus according to an embodiment of the present invention.

FIG. 4 is a graph showing electrostatic attraction force in the plasma processing apparatus according to the embodiment of the present invention.

FIG. 5 is a flowchart of a plasma processing method according to an embodiment of the present invention.

FIG. 6 is a process explanatory diagram of a plasma processing method according to an embodiment of the present invention.

FIG. 7 is a process explanatory diagram of the plasma processing method according to the embodiment of the present invention.

FIG. 8 is a diagram showing a substrate mounting portion of the plasma processing apparatus according to the embodiment of the present invention.

[Explanation of symbols]

1 Vacuum Chamber 2 Processing Chamber 3 Lower Electrode 4 Upper Electrode 6 Silicon Wafer 8 Exhaust Pump 12 Vacuum Adsorption Pump 13 N ₂ Gas Supply Unit 14 He Gas Supply Unit 17 High Frequency Power Supply Unit 18 Electrostatic Adsorption DC Power Supply Unit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Junichi Terayama             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5F004 AA16 BA04 BB18 BB22 BB25                       DB01 EB08

Claims (2)

[Claims] 1. A plasma processing apparatus for performing plasma processing on a semiconductor substrate having an insulating layer formed of a resin tape attached to the surface thereof, wherein a mounting surface on which a conductor is exposed is provided at least in part. A substrate mounting portion on which the semiconductor substrate is mounted with the insulating layer side facing this mounting surface, electrostatic attraction means for holding the semiconductor substrate on the mounting surface by electrostatic attraction, and the mounting surface. And a plasma generating means for generating plasma to process the semiconductor substrate placed on the semiconductor substrate, wherein the insulating layer of the semiconductor substrate is used as a dielectric of the electrostatic attraction means. 2. A plasma processing method in which plasma processing is performed while a semiconductor substrate having an insulating layer formed of a resin tape attached to the surface thereof is held on a mounting surface of a substrate mounting portion by electrostatic attraction. At least a part of the mounting surface is a conductor, the insulating layer side of the semiconductor substrate is mounted toward the mounting surface of the substrate mounting portion, the insulating layer as a dielectric of the electrostatic adsorption means. A plasma processing method characterized in that a semiconductor substrate is electrostatically adsorbed on the mounting surface by utilizing the method.