JP2003317481A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To directly access a memory from the outside without passing through a logic circuit in a semiconductor device with a logic circuit and a memory mounted in one package. <P>SOLUTION: Access to a logic circuit 10 is performed through an external terminal 12 for logic circuit, access to a memory 11 from the logic circuit 10 is performed through a connection node 10A and a selector 14, and direct access to the memory 11 from the outside is performed through an external terminal 13 for memory and the selector 14 without passing through the logic circuit 10. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a logic circuit and a memory are mounted together in one package.

[0002]

2. Description of the Related Art In recent years, due to advances in packaging technology and manufacturing process technology, a semiconductor device in which a logic circuit chip and a memory chip are mounted in one package and a system is configured by one package, so-called SIP (system in package) Is increasing.

FIG. 17 is a schematic configuration diagram showing an example of a conventional SIP. In FIG. 17, 1 is a package body, 2 is a logic circuit chip, 3 is a memory chip, 4 is an external terminal connected to the logic circuit chip 2, 5 is an external terminal connected to the memory chip 3, and the external terminal 5 Is an external terminal for power supply and test.

[0004]

FIG. 18 is a circuit diagram for explaining the problems of the conventional SIP shown in FIG. In FIG. 18, 6 is a logic circuit mounted on the logic circuit chip 2, and 7 is a memory mounted on the memory chip 3. In the conventional SIP, the memory 7 is basically the logic circuit 6 The external access to the memory 7 is performed via the external terminal 4 and the logic circuit 6, or is disabled.

Here, even if the memory 7 can be accessed via the external terminal 4 and the logic circuit 6, the memory 7 can be accessed via the access arbitration circuit. There is a problem that it takes time to access the memory 7 and that the memory 7 cannot be accessed when the CPU suspends the logic circuit 6.

In view of the above points, the present invention is a semiconductor device in which a logic circuit and a memory are mixedly mounted in one package, and enables direct access to the memory from the outside without going through the logic circuit. An object of the present invention is to provide a semiconductor device capable of speeding up memory access.

[0007]

SUMMARY OF THE INVENTION The present invention is a semiconductor device in which a logic circuit and a memory are mounted together in one package, and a memory access for directly accessing the memory from outside without passing through the logic circuit. It has means.

According to the present invention, by using the memory access means, it is possible to directly access the memory from outside without passing through the logic circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIGS.
First to eighth embodiments of the present invention and first of the present invention
An example of a system using the embodiment and the fifth embodiment will be described.

(First Embodiment ... FIGS. 1 to 4) FIG. 1 is a circuit diagram showing a part of a first embodiment of the present invention. Figure 1
Inside, 10 is a logic circuit, 11 is a memory, 12 is an external terminal for a logic circuit, 13 is an external terminal for a memory, 14 is a connection node 10A with the memory 11 of the logic circuit 10 or an external terminal 13 for a memory 11 is a selector that is selectively and electrically connected to 11.

The external terminal 12 for a logic circuit is representative of a plurality of external terminals for a logic circuit, and the external terminal 13 for a memory is representative of a plurality of external terminals for a memory. . Further, each one wiring represents a plurality of wirings existing in parallel. The same applies below.

FIG. 2 is a circuit diagram showing a part of the first example of the first embodiment of the present invention. In the first example of the first embodiment of the present invention, the logic circuit 10 and the memory 11 are different semiconductors. It is mounted on the substrates 15 and 16, and the selector 14 is mounted on the semiconductor substrate 15 for the logic circuit 10.

FIG. 3 is a circuit diagram showing a part of the second example of the first embodiment of the present invention. In the second example of the first embodiment of the present invention, the logic circuit 10 and the memory 11 are different semiconductors. It is mounted on the substrates 15 and 16, and the selector 14 is mounted on the semiconductor substrate 16 for the memory 11.

FIG. 4 is a circuit diagram showing a part of the third example of the first embodiment of the present invention. In the third example of the first embodiment of the present invention, the logic circuit 10 and the memory 11 are the same. The selector 1 is mounted on the semiconductor substrate 17 in a mixed manner.
It is equipped with 4.

In the first embodiment of the present invention, the logic circuit 10
Access to the memory 11 via the external terminal 12 for the logic circuit, access from the logic circuit 10 to the memory 11 via the connection node 10A and the selector 14, and direct access to the memory 11 from the outside. , Through the external terminal 13 for memory and the selector 14 without passing through the logic circuit 10.

The selector 14 is powered by the logic circuit 10.
When the logic circuit 10 is independent of the power supply of the above, the memory 11 can be accessed through the external terminal 13 even when the logic circuit 10 is not used.

According to the first embodiment of the present invention, the semiconductor device in which the logic circuit 10 and the memory 11 are mixedly mounted in one package is directly accessed from the outside without going through the logic circuit 10. Therefore, the speed of memory access can be increased.

(Second Embodiment ... FIG. 5) FIG. 5 is a circuit diagram showing a part of a second embodiment of the present invention. In FIG. 5, 1
8 is a logic circuit, 19-1, 19-2 and 19-n are memories, and a memory 19-3 between the memories 19-2 and 19-n.
Illustration of 19 to 19- (n-1) is omitted.

Reference numeral 20 is an external terminal for a logic circuit, 21 is an external terminal for a memory, and 22 is a memory 19-1 of the logic circuit 18.
Is a selector for selectively and electrically connecting the connection node 18A with the memory 19-1 to 19-n or the external terminal 21 for the memory to the memories 19-1 to 19-n.

In the second embodiment of the present invention, the logic circuit 18
Access to the memories 19-1 to 19-n from the logic circuit 18 is performed via the connection node 18A and the selector 22. Direct access to 1 to 19-n is performed via the external terminal 21 for the memory circuit and the selector 22 without passing through the logic circuit 18.

The memories 19-1 to 19-n can be configured so as to share the address signal and be treated as one memory, or can be configured so as not to share the address signal and to be n memories. It can also be configured to be treated.

The power source of the selector 22 is the logic circuit 18
Of the memories 19-1 to 19-1 through the external terminal 21 even when the logic circuit 18 is not used.
9-n can be accessed.

According to the second embodiment of the present invention, a semiconductor device in which a logic circuit 18 and memories 19-1 to 19-n are mounted together in one package is provided from outside without passing through the logic circuit 18. Since the memories 19-1 to 19-n can be directly accessed, the speed of memory access can be increased.

(Third Embodiment ... FIG. 6) FIG. 6 is a circuit diagram showing a part of a third embodiment of the present invention. 2 in FIG.
3 is a logic circuit, 24 is a memory, 25 is an external terminal for a logic circuit, and 26 is an external terminal for a memory.

In the third embodiment of the present invention, the logic circuit 23
Access to the memory 24 via the external terminal 25 for the logic circuit, access from the logic circuit 23 to the memory 24 via the connection node 23A of the logic circuit 23, and direct access from the outside to the memory 24. Is performed via the external terminal 26 for memory without passing through the logic circuit 23.

When the logic circuit 23 accesses the memory 24, among the nodes of the external device connected to the external terminal 26 for memory, the output node is controlled to have a high impedance, and the output node for memory is controlled. When accessing the memory 24 from the external terminal 26, the output node of the connection node 23A of the logic circuit 23 is controlled to have a high impedance.

Generally, in SIP, the wiring length can be shortened by physically bringing the logic circuit and the memory into close proximity to each other and internally wiring a short distance without passing through an external terminal, but the power consumption and the operating speed are reduced. When the requirement is not strict, it is possible to adopt a configuration in which the selector is not provided as in the third embodiment of the present invention.

According to the third embodiment of the present invention, the semiconductor device in which the logic circuit 23 and the memory 24 are mounted together in one package can directly access the memory 24 from the outside without going through the logic circuit 23. Therefore, the memory access can be speeded up.

(Fourth Embodiment ... FIG. 7) FIG. 7 is a circuit diagram showing a part of a fourth embodiment of the present invention. 2 in FIG.
7 is a logic circuit, 28-1, 28-2 and 28-n are memories, and a memory 28-3 between the memories 28-2 and 28-n.
28- (n-1) are not shown. Reference numeral 29 is an external terminal for a logic circuit, and 30 is an external terminal for a memory.

In the fourth embodiment of the present invention, the logic circuit 27
Access to the memories 28-1 to 28-n from the logic circuit 27 via the connection node 27A of the logic circuit 27, and access from the outside to the memory 28. Direct access to -1 to 28-n is performed via the external terminal 30 for the memory and not via the logic circuit 27.

The logic circuit 27 is used as the memories 28-1 and 28-2.
When accessing 8-n, external terminal 3 for memory
Among the nodes of the external device connected to 0, the output node is controlled to have a high impedance, and when accessing the memories 28-1 to 28-n from the external terminal 30 for memory, the output of the logic circuit 27 is The output node of the connection node 27A is controlled to have a high impedance.

Further, the memories 28-1 to 28-n can be constructed so as to share the address signal and be treated as one memory, or can be arranged so as not to share the address signal and to be n memories. It can also be configured to be treated.

According to the fourth embodiment of the present invention, a semiconductor device in which the logic circuit 27 and the memories 28-1 to 28-n are mounted together in one package is provided from outside without passing through the logic circuit 27. Since the memories 28-1 to 28-n can be directly accessed, the speed of memory access can be increased.

(Fifth Embodiment ... FIGS. 8 to 11) FIG. 8 is a circuit diagram showing a part of a fifth embodiment of the present invention. In FIG. 8, 31 is a logic circuit, 32 is a memory, 33 is an external terminal shared by the logic circuit 31 and the memory 32, 34 is a connection node 31A of the logic circuit 31 with the memory 32 or the external terminal 33 is selected as the memory 32. It is a selector that electrically and electrically connects.

FIG. 9 is a circuit diagram showing a part of the first example of the fifth embodiment of the present invention. In the first example of the fifth embodiment of the present invention, the logic circuit 31 and the memory 32 are different semiconductors. It is mounted on the substrates 35 and 36, and the selector 34 is mounted on the semiconductor substrate 35 for the logic circuit 31.

FIG. 10 is a circuit diagram showing a part of the second specific example of the fifth embodiment of the present invention. In the second specific example of the fifth embodiment of the present invention, the logic circuit 31 and the memory 32 are different semiconductors. It is mounted on the substrates 35 and 36, and the selector 34 is mounted on the semiconductor substrate 36 for the memory 32.

FIG. 11 is a circuit diagram showing a part of the third example of the fifth embodiment of the present invention. In the third example of the fifth embodiment of the present invention, the logic circuit 31 and the memory 32 are the same. The semiconductor substrate 37 is mixedly mounted on the semiconductor substrate 37, and the selector 34 is mounted on the semiconductor substrate 37.

In the fifth embodiment of the present invention, the logic circuit 31
Access to the memory 32 via the external terminal 33, access from the logic circuit 31 to the memory 32 via the connection node 31A and the selector 34, and direct access from the outside to the memory 32 is performed via the logic circuit 31. Not via the external terminal 33 and the selector 34.

According to the fifth embodiment of the present invention, the semiconductor device in which the logic circuit 31 and the memory 32 are mixedly mounted in one package can directly access the memory 32 from the outside without passing through the logic circuit 31. Therefore, it is possible to speed up the memory access and reduce the number of external terminals as compared with the first embodiment of the present invention.

(Sixth Embodiment ... FIG. 12) FIG. 12 is a circuit diagram showing a part of a sixth embodiment of the present invention. 12
Among them, 38 is a logic circuit, 39-1, 39-2, 39-n are memories, and the memory 3 between the memories 39-2, 39-n.
Illustrations of 9-3 to 39- (n-1) are omitted.

40 is a logic circuit 38 and memories 39-1 to 39-1.
An external terminal shared by 39-n, 41 is a connection node 38A of the logic circuit 38 with the memories 39-1 to 39-n or an external terminal 40 is selectively and electrically connected to the memories 39-1 to 39-n. Selector

In the sixth embodiment of the present invention, the logic circuit 38
Access to the memories 39-1 to 39-n from the logic circuit 38 via the connection node 38A of the logic circuit 38 and the selector 41, and the memory 39-from the outside. Direct access to 1 to 39-n does not go through the logic circuit 38, but to the external terminal 4
0 and the selector 41.

The memories 39-1 to 39-n may be configured to share the address signal and be treated as one memory, or may not be shared with the address signal and may be configured as n memories. It can also be configured to be treated.

According to the sixth embodiment of the present invention, a semiconductor device in which a logic circuit 38 and memories 39-1 to 39-n are mounted together in one package is provided from outside without passing through the logic circuit 38. Since the memories 39-1 to 39-n can be directly accessed, the speed of memory access can be increased and the number of external terminals can be reduced as compared with the second embodiment of the present invention.

(Seventh Embodiment ... FIG. 13) FIG. 13 is a circuit diagram showing a part of a seventh embodiment of the present invention. FIG.
42 is a logic circuit, 43 and 44 are memories, 45 is an external terminal shared by the logic circuit 42 and the memory 43, and 46 is an external terminal shared by the logic circuit 42 and the memory 44.

Reference numeral 47 is a selector for selectively and electrically connecting the connection node 42A with the memories 43 and 44 of the logic circuit 42 or the external terminal 45 to the memory 43, and 48 is the logic circuit 4
2 is a selector for selectively and electrically connecting the connection node 42A with the two memories 43 and 44 or the external terminal 46 to the memory 44.

In the seventh embodiment of the present invention, the logic circuit 42
Access to the memories 43 and 44 from the logic circuit 42 via the connection node 42A, and the memories 43 and 44 from the outside.
Direct access to the
This is performed through the external terminals 45 and 46 and the selectors 47 and 48.

In this example, the memories 43 and 44 share the address signal from the logic circuit 42, are treated as one memory from the logic circuit 42, and are external terminals 45, when directly accessed from the outside. Address signals from 46 are not shared and are treated as two memories.

According to the seventh embodiment of the present invention, the semiconductor device in which the logic circuit 42 and the memories 43 and 44 are mixedly mounted in one package is provided to the memories 43 and 44 from outside without passing through the logic circuit 42. Since direct access is possible, it is possible to speed up memory access.

(Eighth Embodiment ... FIG. 14) FIG. 14 is a circuit diagram showing a part of an eighth embodiment of the present invention. 14
Medium, 49 and 50 are logic circuits, 51 and 52 are memories, 53
Is an external terminal for the logic circuit, and 54 is an external terminal shared by the logic circuit 50 and the memories 51 and 52.

55 is a selector for selectively and electrically connecting the connection node 49A of the logic circuit 49 with the memory 51 or the external terminal 54 to the memory 51, and 56 is the connection node 50A of the logic circuit 50 with the memory 52 or the external terminal. The selector 54 selectively and electrically connects the memory 54 to the memory 52.

In the eighth embodiment of the present invention, the logic circuit 49
Is accessed through the external terminal 53, access to the logic circuit 50 is performed through the external terminal 54, and access from the logic circuit 49 to the memory 51 is performed at the connection node 49.
A and the selector 55 are used to access the memory 52 from the logic circuit 50 via the connection node 50A and the selector 56. Direct access to the memories 51 and 52 from the outside is performed via the logic circuit 49, It does not go through 50, but via the external terminal 54 and the selectors 55 and 56.

In this example, the memories 51 and 52 are treated as one memory by the logic circuits 49 and 50, respectively, and when accessed directly from the outside, share the address signal from the external terminal 54 and share one address. Is treated as memory.

According to the eighth embodiment of the present invention, a semiconductor device in which the logic circuits 49 and 50 and the memories 51 and 52 are mounted together in one package is provided from outside without passing through the logic circuits 49 and 50. Since the memories 51 and 52 can be directly accessed, the speed of memory access can be increased.

(Example of System Using First Embodiment of Present Invention ... FIG. 15) FIG. 15 is a circuit diagram showing a part of an example of a system using the first embodiment of the present invention.
In FIG. 15, 57 is a CPU (Central Processing Unit),
Reference numeral 58 is an FPGA (Field) for connecting the CPU 57 to the CPU 57 and the first embodiment 58 of the present invention.
Programmable Gate Array), 60 is a logic circuit access port used when accessing the logic circuit 10 in the first embodiment 58 of the present invention, and 61 is a direct access to the memory 11 in the first embodiment 58 of the present invention. It is a memory access port used in some cases.

In this system, the CPU 57
By using the logic circuit access port 60 in the FPGA 59, the logic circuit 1 in the first embodiment 58 of the present invention
0, and the memory 11 in the first embodiment 58 of the present invention can be directly accessed by using the memory access port 61 in the FPGA 59.

According to this system, the CPU 57 can directly access the memory 11 included in the first embodiment 58 of the present invention, so that the speed of memory access can be increased and the first embodiment of the present invention can be achieved. The memory 11 included in the form 58 can be effectively used, and the memory capacity of the entire system can be reduced.

Further, by directly accessing the memory 11 from the CPU 57 and writing the initial value to the address in the memory 11 used by the logic circuit 10, the logic circuit 1
The time required for the initial setting of 0 can be reduced.

In the case of this example, the FPGA 59
Comprises a node 60A for accessing the logic circuit 10 and a node 61A for accessing the memory 11, so that instead of the first embodiment of the present invention, the second and third embodiments of the present invention are implemented. It can also be configured to use the configuration or the fourth embodiment.

(Example of System Using Fifth Embodiment of the Present Invention ... FIG. 16) FIG. 16 is a circuit diagram showing a part of an example of a system using the fifth embodiment of the present invention.
In FIG. 16, 62 is a CPU, 63 is a fifth embodiment of the present invention, 64 is an FPGA for connecting the CPU 62 and the fifth embodiment 63 of the present invention, and 65 is a fifth embodiment 63 of the present invention.
A logic circuit access port used to access the logic circuit 31 in the internal circuit 66 is a fifth embodiment 63 of the present invention.
It is a memory access port used when directly accessing the memory 32 inside.

In this system, the CPU 62
By using the logic circuit access port 65 in the FPGA 64, the logic circuit 3 in the fifth embodiment 63 of the present invention
1 and the memory 32 in the fifth embodiment 63 of the present invention can be directly accessed by using the memory access port 66 in the FPGA 64.

According to this system, since the CPU 62 can directly access the memory 32 of the fifth embodiment 63 of the present invention, the speed of memory access can be increased and the fifth embodiment of the present invention can be achieved. The memory 32 of the form 63 can be effectively used, and the memory capacity of the entire system can be reduced.

Further, by directly accessing the memory 32 from the CPU 62 and writing the initial value to the address in the memory 32 used by the logic circuit 31, the logic circuit 3
The time required for the initial setting of 1 can be reduced.

In the case of this example, the FPGA64
Is configured to include a common node 67 as a node for accessing the logic circuit 31 and a node for accessing the memory 32.
Instead of the embodiment, the sixth embodiment of the present invention can be configured to be used.

[0065]

As described above, according to the present invention, the memory access means for directly accessing the memory from the outside without passing through the logic circuit is provided. Therefore, without passing through the logic circuit, Since the memory can be directly accessed from the outside, the memory access can be speeded up.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a first specific example of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a part of a second specific example of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of a third specific example of the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a part of a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a part of a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a part of a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a part of a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a part of a first example of the fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a part of a second specific example of the fifth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a part of a third specific example of the fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a part of a sixth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a part of a seventh embodiment of the present invention.

FIG. 14 is a circuit diagram showing a part of an eighth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a part of an example of a system using the first embodiment of the present invention.

FIG. 16 is a circuit diagram showing a part of an example of a system using the fifth embodiment of the present invention.

FIG. 17 is a schematic configuration diagram showing an example of a conventional SIP.

FIG. 18 is a circuit diagram for explaining a problem of the conventional SIP shown in FIG.

[Explanation of symbols]

1 package 4 External terminals for logic circuits 5 External terminal for memory

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuyuki Tanaka             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited (72) Inventor Ryushi Otsuka             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 5B015 HH01 HH03 JJ21 PP02

Claims (5)

[Claims] 1. A semiconductor device in which a logic circuit and a memory are mixedly mounted in one package, and a memory access unit for directly accessing the memory from outside without passing through the logic circuit is provided. Semiconductor device. 2. The memory access means includes an external terminal for a memory and a connection node for connecting the memory to the memory of the logic circuit or a selector for selectively and electrically connecting the external terminal for the memory to the memory. The semiconductor device according to claim 1, wherein: 3. The memory access means includes an external terminal for a memory electrically connected to the memory, wherein the logic circuit accesses the memory from the external terminal for the memory. 2. The semiconductor device according to claim 1, wherein the connection node of the logic circuit with the memory is controlled to have a high impedance. 4. The memory access means includes a selector for selectively and electrically connecting a connection node of the logic circuit with the memory or an external terminal for the logic circuit to the memory, The external terminal is adapted to be also used as an external terminal for a memory.
The semiconductor device described. 5. The memory includes a plurality of memories, the plurality of memories are treated as one memory when accessed from the logic circuit, and are directly accessed from the outside, Treated as multiple memories,
Alternatively, when it is accessed from the logic circuit, it is treated as a plurality of memories, and when it is directly accessed from the outside, it is treated as one memory. 3. The semiconductor device according to 3 or 4.