JP2003316645A - Information processor and memory management method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of improving the using efficiency of a memory while reducing overheads caused at the time of memory access, and a memory management method. <P>SOLUTION: An image forming apparatus for mapping the memory to the process of an application performing an information processing comprises: a region acquisition means for acquiring at least a direct mapping region capable of direct mapping by the process on the memory; and an address conversion means for correlating the physical address of the direct mapping region with a virtual address for the direct mapping region included on a virtual memory region. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and a memory management method, and more particularly to an information processing apparatus and a memory management method using a virtual address function.

[0002]

2. Description of the Related Art Information processing devices such as personal computers perform various information processing by executing one or more software corresponding to various information processing.
In a conventional information processing apparatus, a process generated by executing each software separately acquires a necessary memory.

An image forming apparatus as an application example of an information processing apparatus has the functions of each device such as a printer, a copier, a facsimile and a scanner housed in one housing. The image forming apparatus is provided with a display unit, a printing unit, an image pickup unit, and the like in one housing, and four types of software corresponding to a printer, a copy, a facsimile, and a scanner, respectively, are provided, and the software is switched to change the printer, It operates as a copy machine, a facsimile machine, and a scanner.

The compound machine is provided with software corresponding to a printer, a copy machine, a facsimile machine, and a scanner, respectively. Therefore, the process generated by executing each software separately acquired the required memory.

By the way, when the software executed by the information processing apparatus and the image forming apparatus operates on an operating system (hereinafter referred to as OS), the OS manages memory. OS that realizes multi-process
Performs address management using, for example, the virtual address function, and provides another virtual address space for each process.

The virtual address function uses a paging technique to protect the memory from access by other processes. Paging divides the virtual address space provided to the process and the physical address space with physical memory into pages of a predetermined size determined by the processor, and associates the page in the virtual address space with the page in the physical address space. A method of managing and converting a virtual address into a physical address.

In the paging method, the page table is used to manage the correspondence between the pages of the virtual address space and the pages of the physical address space. A page table is required for each process that has provided virtual address space.

In the case of using the paging method, since address conversion for converting a virtual address into a physical address is required for all memory accesses, hardware support is essential from the viewpoint of execution speed. This address conversion is performed by the memory management unit of the processor (hereinafter, MM
U), and the correspondence differs from processor to processor.

For example, in the MMU of one processor, by setting the physical address of the page table in the control register, the page table in the memory is automatically searched when the memory is accessed, and the physical address to the physical address is set. Do the conversion. In this case, the physical address of another page table is set in the control register when switching processes.

Further, the MMU of another processor does not automatically search the page table, but searches only the translation table inside the processor called a translation lookaside buffer (hereinafter referred to as TLB) to search the physical address. Conversion to. In this case, a TLB exception error occurs when there is no virtual address entry to be accessed in the TLB.
The page table is searched by software by the exception error handler. Then, an entry based on the search result is added to the TLB.

[0011] Patent Document 1 describes a technique relating to sharing a page table. Patent Document 2 describes a technique of dividing one segment on a virtual memory into a common area and a unique area.

[0012]

[Patent Document 1] JP-A-7-160583

[0013]

[Patent Document 2] Japanese Patent Publication No. 6-58649

[0014]

In the address management using the paging method, a substantial execution speed is obtained by the hardware support. However, the address management using a method called demand paging has the following problems.

First, since no physical memory is allocated when a process is created, the contents of the page table are all invalid. Then, when the process is executed, memory access is performed and a page table exception error occurs, and the handler for the page table exception error acquires the physical memory and creates the contents of the page table.

Therefore, even if the physical memory has a margin, there is a problem that a certain overhead is generated during the memory access. This overhead becomes a problem when executing an information processing process that uses a large amount of memory such as an image forming process.

The address of the physical memory corresponding to the virtual memory is set in page units by the page table for flexible management of the physical memory. Therefore, data written to consecutive virtual addresses may be divided into page units and written to discontinuous physical addresses, and data exchange with a device using direct memory access (hereinafter, DMA) is performed. There was a problem that could be complicated.

The contents described in Patent Documents 1 and 2 do not reduce the overhead generated during memory access.

The present invention has been made in view of the above points, and provides an information processing apparatus and a memory management method capable of improving the memory usage efficiency while reducing the overhead generated during memory access. The purpose is to

[0020]

In order to solve the above problems, an invention according to claim 1 is an image forming apparatus for mapping a memory to a process of an application which performs information processing, wherein: An area acquisition unit that acquires at least a direct map area that can be directly mapped by the process, an address conversion unit that associates a physical address of the direct map area with a temporary address for the direct map area included in the virtual memory area. And having.

In such an information processing apparatus, at least a direct map area is acquired in the memory, and the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other. As a result, it is possible to reduce the occurrence of exception errors due to the address conversion means, and it is possible to reduce the memory access overhead for the direct map area.

The invention according to claim 2 is characterized in that the virtual memory area is managed for each page of a predetermined size.

In such an information processing apparatus, the virtual memory area can be managed in units of pages of a predetermined size,
It is possible to adapt to the architecture of the operating system that manages memory on a page-by-page basis.
Therefore, it is possible to improve the memory usage efficiency.

According to a third aspect of the present invention, the contents of the address conversion means for associating the physical address of the direct map area with the temporary address for the direct map area included in the virtual memory area are stored in the virtual storage system. It is characterized in that it further comprises an address rewriting means for rewriting without intervening.

In such an information processing apparatus, the contents of the address converting means in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other without passing through the virtual storage system. By rewriting to, it is possible to use the virtual address conversion function of the hardware while avoiding the overhead of the virtual memory system.

Further, the invention according to claim 4 is characterized in that the address rewriting means rewrites the contents of the address converting means when each process of the application is activated.

In such an information processing apparatus, by rewriting the contents of the address converting means at the time of starting each process of the application, it is possible to reduce the occurrence of an exception error by the address converting means at the time of executing each process, and to directly map It is possible to reduce the overhead of memory access to the area.

The invention according to claim 5 is characterized in that the area acquisition means acquires the direct map area when the information processing apparatus is activated.

In such an information processing apparatus, when the information processing apparatus is activated, the map area is directly acquired,
When each process of the application is activated, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area can be associated with each other.

According to a sixth aspect of the present invention, the address translation means is configured such that, for each process of the application, the temporary map address for the direct map area included in the physical address of the direct map area and the virtual memory area. It is characterized in that it is an address conversion table in the kernel in which and are associated with each other.

In such an information processing apparatus, the occurrence of an exception error can be reduced in the processor that automatically searches the address translation table in the kernel and translates into the physical address, and the memory for the direct map area is reduced. It is possible to reduce the access overhead.

According to a seventh aspect of the present invention, the address conversion means is configured such that, for each process of the application, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area. And an address translation table in the processor in which

In such an information processing apparatus, the occurrence of an exception error can be reduced in the processor which automatically searches the address translation table in the processor and translates into the physical address, and the memory for the direct map area is reduced. It is possible to reduce the access overhead.

Further, in the invention according to claim 8, the address translation means sets a physical address of the direct map area and a virtual memory area in a portion of the address translation table in the processor which is not to be overwritten. It is characterized in that it is associated with the temporary address for the included direct map area.

In such an information processing apparatus, the correspondence between the physical address of the direct map area stored in the address conversion table in the processor and the temporary address for the direct map area included in the virtual memory area is erased by overwriting. It can be avoided.

According to a ninth aspect of the present invention, when the temporary address for the direct map area included in the virtual memory area is continuous, the address translation means corresponds to the direct map corresponding to the temporary address. The physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated so that the physical addresses of the area are continuous.

In such an information processing apparatus, an area contiguous with the temporary address for the direct map area included in the virtual memory area can be assigned to the continuous physical address of the direct map area. Therefore, it is possible to avoid complicated data exchange with a device using direct memory access, and it is possible to transfer a large amount of data by one direct memory access.

According to a tenth aspect of the present invention, the address conversion means includes a physical address of the direct map area and a direct address included in the virtual memory area so that the direct map area is shared by a plurality of processes. It is characterized in that it is associated with a temporary address for the map area.

In such an information processing apparatus, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other so that a plurality of processes share the direct map area. By setting, the memory can be shared by multiple processes.

According to an eleventh aspect of the present invention, the virtual memory area has a user program area and a stack area managed by the virtual memory system, and a direct map area not managed by the virtual memory system. The direct map area may be acquired in an unused area that is not used as the user program area or the stack area in the virtual memory area.

In such an information processing apparatus, the map area is directly acquired in an unused area which is not managed by the virtual memory system in the virtual memory area, so that the virtual address conversion function of the hardware can be realized without going through the virtual memory system. It can be used directly to convert virtual addresses to physical addresses.

A twelfth aspect of the present invention is a memory management method of an information processing apparatus for mapping a memory to a process of an application which performs information processing, wherein the memory is directly mapped on the memory by the process. The present invention is characterized by including an area acquisition step of acquiring at least an area, and an address conversion step of associating a physical address of the direct map area with a temporary address for the direct map area included in the virtual memory area.

In such a memory management method, at least a direct map area is acquired in the memory, and the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other. As a result, it is possible to reduce the exception error that occurs when the virtual address is converted to the physical address, and it is possible to reduce the memory access overhead for the direct map area.

The invention according to claim 13 is characterized in that the virtual memory area is managed for each page of a predetermined size.

In such a memory management method, the virtual memory area can be managed in page units of a predetermined size, and the memory management can be adapted to the architecture of the operating system that manages pages in page units. Therefore, it is possible to improve the memory usage efficiency.

According to a fourteenth aspect of the present invention, in the address translation step, the contents in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other is virtualized. It is characterized by rewriting without going through a storage system.

In such a memory management method, by rewriting the contents in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other without passing through the virtual storage system, It is possible to use the virtual address conversion function of hardware while avoiding the overhead of the virtual memory system.

Further, in the invention according to claim 15, in the address translation step, when each process of the application is started, a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are provided. It is characterized in that the contents associated with and are rewritten.

In such a memory management method, when each process of the application is activated, the contents in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other is rewritten. , Exception error that occurs when converting from virtual address to physical address should not occur when each process is executed. Therefore, the overhead of memory access to the direct map area can be reduced.

The invention according to claim 16 is characterized in that, in the area acquisition step, the direct map area is acquired when the image forming apparatus is started.

In such a memory management method, the direct map area is acquired when the information processing apparatus is started, so that the physical address of the direct map area and the direct map included in the virtual memory area are acquired when each process of the application is started. It can be associated with the temporary address for the area.

According to a seventeenth aspect of the present invention, in the address translation step, the temporary address for the direct map area included in the physical address of the direct map area and the virtual memory area is included in each process of the application. It is characterized by rewriting the address conversion table in the kernel which is associated with.

With such a memory management method, it is possible to reduce the occurrence of an exception error in a processor that automatically searches the address translation table in the kernel and translates into a physical address, and it is possible to reduce the memory for the direct map area. It is possible to reduce the access overhead.

According to the eighteenth aspect of the present invention, in the address translation step, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are included in each process of the application. It is characterized by rewriting the address translation table in the processor in which the and are associated with each other.

With such a memory management method, it is possible to reduce the occurrence of an exception error in a processor which automatically searches the address translation table in the processor and translates into a physical address, and the memory for the direct map area is reduced. It is possible to reduce the access overhead.

According to a nineteenth aspect of the present invention, in the address translation step, the physical address of the direct map area and the virtual memory area are provided in a portion of the address translation table in the processor that is not overwritten. It is characterized in that it is associated with the temporary address for the included direct map area.

In such a memory management method, the correspondence between the physical address of the direct map area stored in the address conversion table in the processor and the temporary address for the direct map area included in the virtual memory area is erased by overwriting. It can be avoided.

According to the twentieth aspect of the present invention, when the temporary address for the direct map area included in the virtual memory area is continuous in the address converting step, the direct map corresponding to the temporary address is provided. The physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated so that the physical addresses of the area are continuous.

In such a memory management method, an area contiguous with the temporary address for the direct map area included in the virtual memory area can be assigned to the continuous physical address of the direct map area. Therefore, it is possible to avoid complicated data exchange with a device using direct memory access, and it is possible to transfer a large amount of data by one direct memory access.

According to a twenty-first aspect of the present invention, in the address translation step, the physical address of the direct map area and the direct address included in the virtual memory area are shared so that the direct map area is shared by a plurality of processes. It is characterized in that it is associated with a temporary address for the map area.

In such a memory management method, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other so that a plurality of processes share the direct map area. By setting, the memory can be shared by multiple processes.

According to a twenty-second aspect of the present invention, the virtual memory area has a user program area and a stack area managed by the virtual memory system, and a direct map area not managed by the virtual memory system. The direct map area may be acquired in an unused area that is not used as the user program area or the stack area in the virtual memory area.

In such a memory management method, by directly acquiring the map area in an unused area which is not managed by the virtual memory system in the virtual memory area, the virtual address conversion function of the hardware can be realized without going through the virtual memory system. It can be used directly to convert virtual addresses to physical addresses.

[0064]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus according to the present invention. The information processing device 1000 is configured to include a hardware resource 1100 and a software group 1200.

The hardware resources 1100 include a memory device 1110, an input device 1120, a display device 1130, other hardware resources 1140 and the like. The software group 1200 includes applications 1210-1 to 121-1.
210-n, OS 123 such as UNIX (registered trademark)
0, BIOS 1240, device driver 1250 and the like.

The information processing apparatus 1000 is turned off when the power is turned on.
The program of S1230 is read from the auxiliary storage device,
The read program is transferred to the memory device 1110 and activated. Further, the information processing apparatus 1000 reads the programs of the applications 1210-1 to 1210-n from the auxiliary storage device when the power is turned on or in response to a start instruction from the operator, and the read program is read from the memory device 1.
Transfer to 110 and start.

Applications 1210-1 to 1210
-N causes the information processing apparatus 1000 to perform various types of information processing. The BIOS 1240 is a program that controls the hardware resource 1100. The device driver 1250 is a program that manages peripheral devices included in the hardware resource 1100.

0S1230 is an API (Application Pr
gram interface) 1220 is used to receive requests from the applications 1210-1 to 1210-n.
The API 1220 is used to receive a request from the applications 1210-1 to 1210-n by a predefined function.

The OS 1230 is the application 121
Each software of 0-1 to 1210-n is controlled in parallel as a process. Also, the OS 1230 is the BIOS 124
0, the device driver 1250 is used to make a request to the hardware resource 1100.

Next, the hardware configuration of the information processing apparatus 1000 will be described. FIG. 2 is a hardware configuration diagram of an embodiment of the information processing apparatus according to the present invention. The information processing device 1000 includes an input device 1510, a display device 1520, an auxiliary storage device 1530, a memory device 1540, and an arithmetic processing device 1 which are connected to each other by a bus B.
550.

The input device 1510 is composed of a keyboard and a mouse, and is used for inputting various operation instructions. The display device 1520 displays various windows and data necessary for operation. The auxiliary storage device 1530 is
It stores a program that causes the information processing apparatus 1000 to perform processing, and also stores various files and data necessary for processing the program.

The memory device 1540 is used by the information processing device 10.
00 is started, the program is read from the auxiliary storage device 1530 and stored. The arithmetic processing unit 1550 executes processing according to a program stored in the memory device 1540.

Next, an image forming apparatus as an application example of the information processing apparatus according to the present invention will be described. The image forming apparatus described in this embodiment is also called a compound machine because the functions of the printer, copier, facsimile, scanner, and other devices are housed in one housing.

FIG. 3 is a block diagram of an embodiment of the compound machine according to the present invention. The compound machine 1 includes a hardware resource 10,
It is configured to include a software group 20 and a multi-function peripheral activation unit 50. The hardware resource 10 includes a monochrome laser printer 11, a color laser printer 12, and a hardware resource 13 such as a scanner or a facsimile. Further, the software group 20 has an application 30 and a platform 40 activated on an operating system (hereinafter referred to as OS) such as UNIX (registered trademark).

The platform 40 interprets the processing request from the application 30 and interprets the hardware resource 10
Control service 51 that issues a request to obtain
A system resource manager (hereinafter referred to as SRM) 43 that manages one or more hardware resources 10 and arbitrates an acquisition request from the control service 51;
A handler layer 52 that manages the hardware resource 10 in response to the acquisition request from M43.

The control service 51 includes a system control service (hereinafter referred to as SCS) 42 and an engine control service (hereinafter referred to as ECS) 4
4, memory control service (hereinafter referred to as MCS) 45, operation panel control service (hereinafter referred to as OCS) 46, fax control service (hereinafter referred to as FCS) 47, network control service (hereinafter referred to as NCS) 48, etc. It is configured to have the above service modules.

The platform 40 is configured to have an application program interface (hereinafter, referred to as API) 53 that can receive a processing request from the application 30 by a predefined function. The OS executes each software of the platform 40 and the application 30 in parallel as a process.

The SRM 43 process controls the system and manages resources together with the SCS 42. For example, the SRM 43 process includes an engine such as a scanner unit and a printer unit, a memory, an HDD file, a host I / O (Centro I / F, a network I / F, an IE).
Arbitration is performed and execution control is performed according to a request from an upper layer that uses the hardware resource 10 such as the EE1394 I / F and the RS232C I / F.

Specifically, the SRM 43 determines whether the requested hardware resource 10 is available (whether it is not used by another request), and if it is available, the requested hardware resource 10 is available. Notify upper layer that is available. Further, the SRM 43 schedules the use of the hardware resource 10 in response to a request from the upper layer, and directly executes the request contents such as paper conveyance and image forming operation by the printer engine, memory acquisition, and file generation.

The SCS 42 process includes application management, operation unit control, system screen display, LED display,
Performs resource management and interrupt application control.
The process of the ECS 44 controls the engine of the monochrome laser printer 11, the color laser printer 12, and other hardware resources 13.

The process of MCS 45 includes acquisition and release of image memory, use of hard disk device (HDD),
It compresses and decompresses image data. The process of OCS 46 controls the operation panel which is a means for transmitting information between the operator and the main body control.

The FCS 47 process is executed by the PSTN or IS from each application layer of the system controller.
An application is provided for performing facsimile transmission / reception using a DN network, registration / quotation of various facsimile data managed by BKM (backup SRAM), facsimile reading, facsimile reception printing, and fusion transmission / reception.

The NCS 48 process uses the network I
A service that can be used in common is provided to applications 30 that require I / O. Data received by each protocol from the network side is distributed to each application 30, and
It acts as an intermediary when transmitting data from 0 to the network side.

The handler layer 52 includes a fax control unit handler (hereinafter referred to as FCUH) 54 for managing a fax control unit (hereinafter referred to as FCU) described later, memory allocation for each process, and memory allocated to each process. Management of
An image memory handler (hereinafter referred to as IMH) 55 that manages a direct map area, which will be described later, is included.

SRM43, FCUH54 and IMH5
5 makes a processing request to the hardware resource 10 by using an engine I / F 56 that transmits a processing request to the hardware resource 10 by a predefined function.

Further, the application 30 performs processing unique to each user service relating to image forming processing such as printer, copy, facsimile, and scanner.

The application 30 is a printer application 31 which is an application for a printer having a page description language (PDL, PCL) and Postscript (PS), a copy application 32 which is a copying application, and a fax which is a facsimile application. It has an application 33 and a scanner application 34 which is a scanner application.

FIG. 4 is a hardware configuration diagram of an embodiment of the compound machine according to the present invention. The compound machine 1 of FIG. 4 includes a controller 60, an operation panel 70, and a fax control unit (hereinafter referred to as FCU) 80.
A USB device 90, an IEEE 1394 device 100, and an engine unit 110.

The controller 60 has a CPU 61
, MEM-P62, North Bridge (hereinafter referred to as NB) 63, South Bridge (hereinafter referred to as SB) 6
4, ASIC 66, MEM-C 67, HDD 68
And a network I / F controller 69.

The operation panel 70 is directly connected to the ASIC 66 of the controller 60. Also, F
The CU 80, the USB device 90, the IEEE 1394 device 100 and the engine unit 110 are the controller 6
0 ASIC 66 is connected by a PCI bus or the like.

The controller 60 uses the ASIC 66 as the ME.
The M-C67, the HDD 68, the network I / F controller 69, etc. are connected, and the CPU 61 and the ASI are connected.
C66 is connected via the NB63 of the CPU chip set. In this way, the CPU 61 via the NB 63
By connecting the ASIC 66 and the ASIC 66, it is possible to cope with the case where the interface of the CPU 61 is not open to the public.

Here, the ASIC 66 and the NB 63 are PCs.
IGP (Acce
lerated Graphics Port) 65. As described above, in order to control the execution of one or more processes forming the platform 40 and the application 30 of FIG. 3, the ASIC 66 and the NB 63 are connected to the low-speed PCI.
The connection is not via the bus, but via AGP 65 to prevent performance degradation.

The CPU 61 controls the entire compound machine 1. The CPU 61 includes SCS42, SRM43, ECS44, which forms the platform 40 on the OS.
MCS45, OCS46, FCS47, NCS48, F
The CUH 54 and the IMH 55 are respectively activated and executed as processes, and the printer application 31, the copy application 32, the fax application 33, and the scanner application 34 forming the application 30 are activated and executed. The CPU 61 has a page table automatic reference function.

The NB63 is composed of the CPU 61 and MEM-P6.
2, a bridge for connecting the SB 64 and the ASIC 66. The MEM-P 62 is a system memory used as a drawing memory of the multi-function peripheral 1. SB64
Is a bridge for connecting the NB 63 to the ROM, PCI bus, and peripheral devices.

The MEM-C 67 is a local memory used as a copy image buffer and a code buffer.
The ASIC 66 is an IC for image processing applications having a hardware element for image processing. The HDD 68 is a storage for accumulating image data, programs, font data, and forms. In addition, the operation panel 70 is an operation unit that receives an input operation from an operator and performs a display for the operator.

The multi-function peripheral activation unit 50 of FIG. 3 is first executed when the power of the multi-function peripheral 1 is turned on, and activates the platform 40 and the application 30. FIG. 5 is a block diagram of an example of the compound machine starting unit. Fusion machine start-up section 50
Has a ROM monitor 121 and a program starting unit 122.

The ROM monitor 121 is executed when the power is turned on, and performs hardware initialization, controller board diagnosis, software initialization, OS startup, and the like. The program activation unit 122 is called from the OS and acquires a memory area on the MEM-P62 and MEM-C67. Then, the program activation unit 122 reads out the programs of the control service 51 and the application 30 from the ROM, and reads each of the read out programs M
The data is transferred to the memory area acquired on the EM-P62 and MEM-C67 and activated.

Hereinafter, the processing of the compound machine as an application example of the information processing apparatus according to the present invention will be mainly described. FIG. 6 is a diagram illustrating an example of memory management in the compound machine.

For example, MEM-P62 and MEM-C6
The memory map of No. 7 is represented as shown in FIG. M
The EM-P62 and the MEM-C67 are, for example, a kernel area used by the OS and various applications 30.
A general-purpose area used by the various control services 51 and a direct map area described later are acquired. The kernel area and the general-purpose area are managed by the OS.

The memory map of the virtual memory area is
It is expressed as shown in FIG. As the virtual memory area, a user program area, a direct map area described later, and a stack area are acquired. The virtual memory area is allocated for each process of the application 30 such as the printer application 31 and the copy application 32, and for each process of the control service 51 such as the ECS 44 and MCS 45.

The user program area and the stack area are managed by the virtual storage system. Therefore, the contents of the page table for the user program area and the stack area are created or changed by the virtual storage system.

First, a first embodiment using a processor having a page table automatic reference function will be described. FIG. 7 shows a flowchart of an example of the page access process. Here, the page access processing when the content of the page table is invalid will be described.

When a new page is accessed, CP
The U61 proceeds to step S10 and determines whether the virtual address of the page to be accessed is registered in the page table. When the content of the page table is invalid, the CPU 61 determines that the virtual address of the page to be accessed is not registered in the page table (NO in S11), and proceeds to step S13.

In step S13, a page table exception error occurs because it is determined that the virtual address of the page to be accessed is not registered in the page table. After step S13, the process proceeds to step S14, where C
The PU 61 acquires the virtual address where the page table exception error has occurred.

In step S15 following step S14, the virtual storage system determines whether the virtual address acquired in step S14 is within the range mapped in the memory. If it is determined that the acquired virtual address is within the range mapped in the memory (YES in S16), the virtual storage system proceeds to step S18 and acquires one page of physical memory. If it is determined that the acquired virtual address is not within the range mapped in the memory (NO in S16), the virtual storage system proceeds to step S17 to notify the process of an illegal address access error.

In step S19 following step S18, the virtual storage system creates the contents of the page table by registering the address of the physical memory acquired in step S18 in the page table. In step S10 following step S20, the CPU 61 determines whether the virtual address of the page to be accessed is registered in the page table.

Since the contents of the page table are created in step S19, the CPU 61 determines that the virtual address of the page to be accessed is registered in the page table (YES in S11), and proceeds to step S12. Then, in step S12, the page table exception error does not occur, and the access to the new page is successful. In such a page access process, a certain overhead occurs during memory access even if the physical memory has a margin.

Therefore, in the present invention, a direct map area is created in the virtual memory area, and the contents of the page table corresponding to the direct map area are created by issuing a system call when a process is created or when a user process is executed. . FIG. 8 shows a memory map of an example of the direct map area. As shown in FIG. 8, the direct map area is allocated for each application process such as the printer application 31 and the copy application 32 and each control service process such as the ECS 44 and MCS 45.

According to the present invention, an unused area other than the virtual memory area of the physical memory is directly acquired as the map area when the virtual storage system is activated. Therefore, the contents of the page table corresponding to the direct map area are not created or modified by the virtual storage system.

FIG. 9 is a diagram for explaining the memory management method for the direct map area. It should be noted that, in FIG. 9, components not related to the description are appropriately omitted.

The kernel stores a virtual memory processing unit 133 for processing access to the virtual memory and a virtual memory use area.
It has a page table management unit 134 that manages each page using a page table, and an exception processing unit 135 that performs exception processing for access to virtual memory. The virtual storage processing unit 133, the page table management unit 134, and the exception processing unit 135 form a virtual storage system.

The direct map area acquisition unit 131 in the OS is
When the virtual storage system is activated, a temporary address for the direct map area included in the virtual memory area corresponding to the direct map area of the physical memory is set. In addition, the memory map unit 132 directly maps the memory for the process to the map area according to the instruction from the IMH 55 when the process is generated or the system call is issued when the user process is executed. In other words, the memory map unit 132 associates the physical address of the direct map area with the temporary address for the direct map area included in the virtual memory area,
The contents of the page table managed by the page table management unit 134 are rewritten.

The direct map area acquisition unit 131 corresponds to the area acquisition means described in the claims. The page table managed by the page table management unit 134 corresponds to the address conversion unit described in the claims. The memory map unit 132 corresponds to the address rewriting unit described in the claims.

The page access processing for the direct map area will be described with reference to FIG. When the page directly included in the map area is accessed, the CPU
The process proceeds to step S10 to determine whether the virtual address of the page to be accessed is registered in the page table.

Since the contents of the page table corresponding to the direct map area have already been created by issuing a system call when the process is created or when the user process is executed,
The CPU 61 determines that the virtual address of the page to be accessed is registered in the page table (YES in S11), and proceeds to step S12. Then, in step S12, the page table exception error does not occur, and the access to the page directly included in the map area is successful.

That is, when a processor having a page table automatic reference function directly accesses a page included in the map area, a page table exception error does not occur and the processor automatically refers to the page table to generate a virtual address. Is converted to a physical address.

Therefore, the virtual memory system does not know that the direct map area is accessed and does not perform the processing for managing the virtual memory area.
In such a page access process, it is possible to access a page without the overhead of the virtual storage system.

In the first embodiment, the user address space between the user program area of the virtual memory area and the stack area, which is not used by the virtual memory system, is directly used as the map area. In general, the user address space included in the virtual memory area is sufficiently larger than the address space actually used, so there is no problem in directly using the user address space not used by the virtual memory system as the map area.

Next, a second embodiment will be described in which a processor having an address conversion function by TLB is used without the page table automatic reference function.

In the cache memory of the CPU 61, the CP
There is a TLB managed by U61. T
The LB holds a temporary address and a physical address in association with each other for each process, and converts the specified temporary address into a physical address when the process attempts to access the memory by specifying the temporary address. Is. This TLB holds a predetermined number (for example, 48, 64, etc.) of sets of temporary addresses and physical addresses. FIG. 10 is a diagram for explaining the relationship between the TLB and the page table of each process. As shown in FIG. 10, each page table uses a temporary address unique to each process, and manages a physical address corresponding to the temporary address. In addition, the TLB stores a temporary address accessed by each process and a physical address corresponding to the temporary address as a process ID (hereinafter, PID).
Hold) for each.

For example, when the process of the printer application 31 accesses the temporary address 1100, the CP
U61 searches the PID of the printer application 31 for the temporary address 1100, and uses the physical address 130 corresponding to the temporary address 1100 of the printer application 31.

On the other hand, when the process of the printer application 31 accesses the temporary address 1000, the CP
U61 searches the PID of the printer application 31 for the temporary address 1000. However, the TLB of FIG.
The temporary address 1000 of the printer application 31 is not registered in. Therefore, a TLB exception error occurs, and the CPU 61 refers to the page table of the printer application 31. Then, the physical address 30 corresponding to the temporary address 1000 of the printer application 31 is acquired, and an entry of “PID: printer application, physical address: 30, temporary address: 1000” is added to the TLB.

However, since the number of entries that the TLB can hold is determined by the processor, the previous entry may be overwritten when a new entry is added. As described above, the TLB entry may be overwritten and its contents changed, but there is a function of protecting an important entry that is frequently used from being overwritten for fixed use.

FIG. 11 is a block diagram showing an example of TLB.
In the TLB of FIG. 11, a predetermined number of entries are fixedly used entries that are not overwritten, and the remaining entries are dynamically used entries that are overwritten. By using the fixedly used entries, it is possible to protect important entries from being overwritten.

Therefore, in the present invention, as in the first embodiment,
A direct map area is created in the virtual memory area, and the virtual address of the direct map area and the physical address corresponding to the virtual address are fixedly used in FIG. 11 by issuing a system call when a process is created or when a user process is executed. I wrote it in the entry. According to the present invention, an unused area other than the virtual memory area of the physical memory is directly acquired as a map area when the virtual storage system is activated. Therefore, the contents of the TLB for the direct map area are not created or modified by the virtual storage system.

In the case of the second embodiment, the memory map unit 132 of FIG. 8 causes the CPU 61 to associate the physical address of the direct map area with the temporary address for the direct map area included in the virtual memory area. TLB to manage
Write to a permanently used entry in.

When a page directly included in the map area is accessed in this state, the search for the temporary address in the TLB always hits, and the CPU 61 can obtain the physical address corresponding to the temporary address. As described above, since the TLB exception error does not occur, the virtual storage system does not know that the direct map area is accessed, and does not perform the processing for managing the virtual memory area. Therefore, it is possible to access the page without incurring the overhead of the virtual memory system.

In the second embodiment, the user address space between the user program area of the virtual memory area and the stack area, which is not used by the virtual memory system, is directly used as the map area. Normally, the user address space included in the virtual memory area is sufficiently larger than the address space actually used, so there is no problem in directly using the user address space not used by the virtual memory system as the map area.

Since the address range that can be specified by one entry is limited, when an address range exceeding the limit is directly used as a map area, a plurality of entries are fixedly used in the TLB. Need to be written in.

In the above-mentioned first and second embodiments, the direct map area as shown in FIG. 6 is realized by directly utilizing the support by hardware. Therefore, the multi-function peripheral 1 of the present invention creates a page table or TLB so that the physical addresses corresponding to the virtual addresses in the direct map area are continuous, so that the areas where the addresses are continuous in the virtual address space are also addressed in the physical memory. It is possible to associate such that they are continuous.

Usually, data exchange by DMA performed by devices is performed in the physical address space. Therefore, when the data created in the virtual address space is transferred to the device by DMA, a large amount of data can be transferred to the device by one DMA if there is a guarantee that the addresses are continuous on the physical memory. .

Further, the multi-functional peripheral 1 of the present invention can share a memory when data is shared by a plurality of processes. FIG. 12 shows an example memory map when a memory is shared by a plurality of processes.

In the memory map of FIG. 12, the areas a and b are arranged so that the area a included in the virtual memory area of the process A and the area b included in the virtual memory area of the process B use the same physical memory area. The content of the page table or TLB corresponding to is rewritten. Therefore, the process A and the process B have almost no overhead caused by the virtual memory system,
The physical memory area can be shared.

A process of sharing a memory with a plurality of processes using the memory map of FIG. 12 will be described with reference to FIG. FIG. 13 shows a sequence diagram of an example when a memory is shared by a plurality of processes.

In FIG. 13, the process A is performed in step S30.
Requests the IMH 49 to acquire the virtual memory area a. In step S31 following step S30, the I
The MH 49 acquires a physical memory area in response to a request from the process A, and notifies the process A of the temporary address A corresponding to the acquired physical memory area. For example, the process A creates an image, and the temporary address A that acquired the created image
Write in.

Progressing to step S32 following step S31, the process A notifies the process B of the temporary address A in which the image is written by interprocess communication. Note that the area a included in the virtual memory area of the process A and the area b included in the virtual memory area of the process B use the same physical memory area so that the page table or the TLB corresponding to the areas a and b is used. Therefore, the process B can read the image from the temporary address A notified from the process A and output the read image to, for example, a printer. Progressing to step S33 following step S32, the process B notifies the process A that the image has been read and output to the printer by interprocess communication. After step S33, step S3
4, the process A requests the IMH 49 to release the physical address and ends the process.

In this embodiment, the processing of the multi-function peripheral 1 has been mainly described, but the information processing apparatus 1000 shown in FIGS.
It can be easily applied to. In the information processing apparatus 1000, the application 12 is used instead of the IMH 55 of FIG.
10-1 to 1210-n and other programs give instructions to the memory map unit 132 when a process is generated.

[0139]

As described above, according to the present invention, since an exception error hardly occurs at the time of memory access,
It is possible to reduce the overhead of memory access to the direct map area.

Further, according to the present invention, since the area contiguous with the temporary address for the direct map area contained in the virtual memory area can be allocated to the continuous physical address of the direct map area, Data exchange with a device using memory access is not complicated, and a large amount of data can be transferred by one direct memory access.

According to the present invention, the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other so that a plurality of processes share the direct map area. Therefore, the memory can be shared by a plurality of processes.

[0142]

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an information processing device according to the present invention.

FIG. 2 is a hardware configuration diagram of an embodiment of an information processing device according to the present invention.

FIG. 3 is a configuration diagram of an embodiment of a compound machine according to the present invention.

FIG. 4 is a hardware configuration diagram of an embodiment of the compound machine according to the present invention.

FIG. 5 is a configuration diagram of an example of a compound machine starting unit.

FIG. 6 is a diagram illustrating an example of memory management in the multi-function peripheral.

FIG. 7 is a flowchart of an example of page access processing.

FIG. 8 is a memory map of an example of a direct map area.

FIG. 9 is a diagram for explaining a memory management method for a direct map area.

FIG. 10 is a diagram for explaining a relationship between a TLB and a page table of each process.

FIG. 11 is a block diagram of an example of TLB.

FIG. 12 is a memory map of an example when a memory is shared by a plurality of processes.

FIG. 13 is a sequence diagram of an example when a memory is shared by a plurality of processes.

[Explanation of symbols]

1 Fusion machine 10,1100 Hardware resource 11 Monochrome laser printer 12 Color laser printer 13,1140 Hardware resource 20,1200 Software group 30,1210-1-1210-n Application 40 Platform 42 System control service (SCS) 43 System resource Manager (SRM) 44 Engine Control Service (ECS) 45 Memory Control Service (MCS) 46 Operation Panel Control Service (OCS) 47 Fax Control Service (FCS) 48 Network Control Service (NCS) 50 Multifunction Machine Startup Unit 51 Control Service 52 Handler Layers 53, 1220 Application Program Interface (API) 54 Ax control unit handler (F
CUH) 55 Image memory handler (IMH) 56 Engine I / F 60 Controller 61 CPU 62 System memory (MEM-P) 63 Northbridge (NB) 64 Southbridge (SB) 65 AGP (Accelerated Graphics Port) 66 ASIC 67 Local memory (MEM-C) 68 Hard disk device (HDD) 69 Network I / F controller 70 Operation panel 80 Fax control unit (FCU) 90 USB device 100 IEEE 1394 device 110 Engine section 121 ROM monitor 122 Program activation section 131 Direct map area acquisition section 132 Memory map unit 133 Virtual memory processing unit 134 Page table management unit 135 Exception processing unit 1000 Information processing device 1110 Memory device 1120 On Device 1130 display device 1230 operating system (OS) 1240 BIOS 1250 device driver

Claims (22)

[Claims] 1. An information processing apparatus that maps a memory to a process of an application that performs information processing, comprising: an area acquisition unit that acquires at least a direct map area that can be directly mapped by the process on the memory; An information processing apparatus comprising: an address conversion unit that associates a physical address of a map area with a temporary address for a direct map area included in a virtual memory area. 2. The information processing apparatus according to claim 1, wherein the virtual memory area is managed for each page of a predetermined size. 3. An address rewriting means for rewriting the contents of an address converting means in which a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are associated with each other without going through a virtual storage system. The information processing apparatus according to claim 1, further comprising: 4. The information processing apparatus according to claim 3, wherein the address rewriting unit rewrites the contents of the address converting unit when each process of the application is activated. 5. The information processing apparatus according to claim 1, wherein the area acquisition unit acquires the direct map area when the information processing apparatus is activated. 6. The address conversion means is provided in a kernel in which a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are associated with each other for each process of the application. The information processing apparatus according to claim 1, wherein the information processing apparatus is an address conversion table. 7. The address conversion means is provided in a processor in which a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are associated with each other for each process of the application. An address translation table is provided.
5. The information processing device according to any one of 5 to 5. 8. The address conversion means is a temporary map area direct address included in the physical address of the direct map area and the virtual memory area in a portion of the address conversion table in the processor which is not to be overwritten. The information processing apparatus according to claim 7, wherein the information processing apparatus is associated with an address. 9. The address converting means, when the temporary address for the direct map area included in the virtual memory area is continuous, the physical address of the direct map area corresponding to the temporary address is continuous. 9. The information processing apparatus according to claim 1, wherein a physical address of the direct map area is associated with a temporary address for the direct map area included in the virtual memory area. 10. The address conversion means sets a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area so that a plurality of processes share the direct map area. The information processing apparatus according to claim 1, wherein the information processing apparatus is associated with each other. 11. The virtual memory area has a user program area and a stack area managed by the virtual storage system, and a direct map area not managed by the virtual storage system, and the direct map area is the virtual memory. 11. The information processing apparatus according to claim 3, wherein the information processing apparatus is acquired in an unused area that is not used as the user program area or the stack area among the areas. 12. A memory management method of an information processing apparatus for mapping a memory to a process of an application which performs information processing, wherein an area acquisition step of acquiring at least a direct map area directly mappable by the process on the memory And an address conversion step of associating a physical address of the direct map area with a temporary address for the direct map area included in the virtual memory area. 13. The memory management method according to claim 12, wherein the virtual memory area is managed for each page of a predetermined size. 14. The address translation step includes rewriting the content in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other without going through a virtual storage system. The memory management method according to claim 12 or 13, characterized in that. 15. The address translation step rewrites the contents in which the physical address of the direct map area and the temporary address for the direct map area included in the virtual memory area are associated with each other when each process of the application is activated. 15. The memory management method according to claim 14, wherein: 16. The memory management method according to claim 12, wherein in the area acquisition step, the direct map area is acquired when the information processing apparatus is activated. 17. The address conversion step is performed in a kernel in which a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are associated with each other for each process of the application. 17. The memory management method according to claim 12, wherein the address conversion table is rewritten. 18. The address translation step in a processor in which a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are associated with each other for each process of the application. 17. The memory management method according to claim 12, wherein the address conversion table is rewritten. 19. In the address translation step, a temporary address for the direct map area included in the physical address of the direct map area and the virtual memory area is provided in a portion of the address translation table in the processor which is not to be overwritten. 19. The memory management method according to claim 18, wherein the memory management method is associated with an address. 20. In the address converting step, when the temporary address for the direct map area included in the virtual memory area is continuous, the physical addresses of the direct map area corresponding to the temporary address are continuous. 20. The memory management method according to claim 12, wherein the physical address of the direct map area is associated with the temporary address for the direct map area included in the virtual memory area. 21. In the address conversion step, a physical address of the direct map area and a temporary address for the direct map area included in the virtual memory area are shared so that a plurality of processes share the direct map area. 21. The memory management method according to claim 12, wherein the memory management method is associated with each other. 22. The virtual memory area includes a user program area and a stack area managed by the virtual storage system, and a direct map area not managed by the virtual storage system, and the direct map area is the virtual memory. 22. The memory management method according to claim 14, wherein the memory is acquired in an unused area that is not used as the user program area or the stack area among the areas.