JP2003316324A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device whose power consumption is not increased even when a frame frequency is raised in order to solve flicker and a beat phenomenon due to an FRC (frame rate control) system. <P>SOLUTION: A liquid crystal display device is provided with an FRC conversion circuit 3 which converts multi-level display data into FRC data in which data are thinned every one frame in accordance with the number of gradation and a liquid crystal driving circuit 2 which generates liquid crystal driving voltages based on the FRC data transferred every one frame from the FRC conversion circuit 3 and applies these voltages to a liquid crystal panel 1. The FRC conversion circuit 3 inserts a halt frame for suspending the transferring of the FRC data to the liquid crystal driving circuit 2 between arbitrary frames of the plurality of frames needed for refreshing one screen of the liquid crystal panel 1. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which performs gradation display by a frame thinning gradation method.

[0002]

2. Description of the Related Art A general matrix type display device has a display section having row electrodes and column electrodes arranged in a matrix, and a voltage for generating a row voltage for driving the row electrodes and a column voltage for driving the column electrodes. A generation circuit, a row electrode drive circuit that connects the row electrode and the voltage generation circuit to apply a row voltage to the row electrode, and a column electrode that connects the column electrode and the voltage generation circuit to apply a column voltage to the column electrode. It is equipped with a drive circuit.

In such a matrix type display device, display is performed at the intersections of the row electrodes and the column electrodes which form pixels.

The display portion of a matrix type liquid crystal display device, which is a typical matrix type display device, is constructed as a liquid crystal panel in which liquid crystal is sandwiched between two electrode substrates having pixel electrodes. By applying a row voltage and a column voltage, the optical characteristics of the liquid crystal are changed to perform display.

Of the matrix type liquid crystal display devices, a simple matrix type liquid crystal display device is nowadays often used in the field of mobile terminals, especially in mobile phones, and has a low power consumption and displays images and the like. It is also desired to increase the number of gradations.

As a gradation display method in a simple matrix type liquid crystal display device, the voltage value applied to the liquid crystal is spatiotemporally changed by thinning out the data to be transmitted for each frame according to the gradation data. A frame thinning method (FRC (Frame Rate Control) method) for realizing display is widely used.

However, in the FRC system, in principle,
When the number of gradations is increased, the FRC completion period (frequency of one screen refresh rate) of the liquid crystal panel is extremely decreased, and there is a problem that the liquid crystal screen is likely to flicker.

In order to suppress such flicker of the liquid crystal screen, an optimum FRC completion cycle is selected according to the response speed of the liquid crystal element and the number of gradations for FRC control.

However, due to the following factors, it may be necessary to increase the frame frequency of the liquid crystal screen (the time for scanning the first line to the last line of the liquid crystal panel).

Currently, the commercial frequency of Japan is 50 in eastern Japan.
It is roughly divided into the Hz band and the 60 Hz band of western Japan.

Due to the interference between the commercial frequency and the frame frequency of the liquid crystal screen, there is a problem that a horizontal stripe pattern beat phenomenon occurs.

Most of liquid crystal panels used in mobile terminals such as mobile phones have both a transmissive type and a reflective type. In a bright place under a fluorescent lamp, the liquid crystal panel is used in a reflective mode, so that Life is extended.

Particularly in the reflection mode, the light source illuminated by the liquid crystal panel at a commercial frequency such as a fluorescent lamp and the frame frequency driving the liquid crystal panel interfere with each other to cause a noticeable horizontal stripe beat phenomenon.

Even the horizontal striped beat phenomenon that has not occurred in the 60 Hz band of western Japan may occur in the eastern part of the 50 Hz band.

In order to suppress the horizontal stripe pattern beat phenomenon in both of these areas, it is necessary to increase the frame frequency of the liquid crystal panel to more than double the original frame frequency (frame frequency that could suppress flickering due to FRC control). . Therefore, high-speed transfer processing must always be performed during the data transfer period between the FRC conversion circuit and the liquid crystal drive circuit, resulting in increased power consumption.

For example, 1/82 Duty, response speed 15
A liquid crystal panel of 0 ms is normally driven at a frame frequency of 90 Hz, and in the commercial frequency 60 Hz band, the beat phenomenon does not appear even in the reflection mode, which is a good display state, but in the commercial frequency 50 Hz band, a strong beat phenomenon occurs. appear.

The degree of the beat phenomenon that appears on the liquid crystal panel display when the frame frequency is changed with respect to the commercial frequencies of 50 Hz and 60 Hz is visually evaluated by 4 ranks (no, slight, yes, strong) and graphed. Is shown in FIG. From the graph shown in FIG. 4, when the commercial frequency is 50 Hz,
Under both conditions at 60 Hz, the frame frequency at which the beat phenomenon does not appear is 150 Hz or higher.

Even if the frame frequency is increased to 150 Hz in order to suppress the beat phenomenon, some flicker due to the FRC method remains, so the frame frequency is further increased to 180 Hz.
It is necessary to raise to Hz. In this case, the current consumption is 2.8 mA (frame frequency 90 Hz) → 4.5 mA (frame frequency 180 H)
z), which is a 1.6-fold increase.

As described above, in order to suppress the horizontal striped beat phenomenon in both the 50 Hz and 60 Hz regions, the frame frequency of the liquid crystal panel is set higher than the frame frequency that was originally capable of suppressing the flicker due to the FRC control. There was a problem that power consumption would increase significantly because of the need to take measures.

Therefore, a technique for suppressing an increase in power consumption in FRC control is disclosed in, for example, Japanese Patent Laid-Open No. 2001-75538.
It is disclosed in the publication. In the above publication, the display data output from a microcomputer or the like is once written into a memory through a frame thinning conversion circuit (FRC conversion circuit), and the necessary data is read bit by bit in the corresponding frame, thereby reducing power consumption by FRC control. It is designed to suppress the increase. That is, the above-mentioned publication discloses a technique for suppressing an increase in power consumption due to FRC control by reducing the number of read bits.

[0021]

However, since the technique disclosed in the above publication only reduces the number of bits read from the display data memory, the data thinning conversion circuit and the display device are driven during FRC control. Data transfer to and from the drive circuit is continuously performed. Therefore, as described above, in order to eliminate the flicker and the beat phenomenon due to the FRC method, it is necessary to increase the frame frequency and always perform high-speed transfer processing.
There arises a problem that the increase in power consumption cannot be suppressed.

The present invention has been made in view of the above problems, and an object thereof is to eliminate the flicker and the beat phenomenon due to the FRC system and to prevent the power consumption from increasing even if the frame frequency is increased. To provide a device.

[0023]

In order to solve the above problems, a liquid crystal display device of the present invention is a liquid crystal display device for performing multi-gradation display of a liquid crystal display panel by a frame thinning gradation (FRC) method. An FRC conversion circuit that thins out display data of multiple gradations for each frame according to the number of gradations and converts it into FRC data, and a liquid crystal based on the FRC data transferred from the FRC conversion circuit for each frame. A liquid crystal drive circuit for generating a drive voltage and applying the liquid crystal drive voltage to the liquid crystal display panel, wherein the FRC conversion circuit is an arbitrary frame of a plurality of frames necessary for refreshing one screen of the liquid crystal display panel. A pause frame that pauses the transfer of FRC data to the liquid crystal drive circuit is inserted between them.

According to the above structure, the liquid crystal display panel 1
Since a pause frame that suspends the transfer of FRC data to the liquid crystal drive circuit is inserted between arbitrary frames of a plurality of frames required for screen refresh, the FRC data of one frame is refreshed during one screen refresh of the liquid crystal display panel. There can be a period when the transfer is paused.

As a result, since the data transfer from the FRC conversion circuit to the liquid crystal drive circuit is intermittently performed, the power consumption required for the data transfer is smaller than that in the case where the data transfer is continuously performed. I'm done. In particular, FRC
Even when the data transfer needs to be performed at high speed, such as when the frame frequency is raised to eliminate the flicker and beat phenomenon caused by the method, there is a period during which the data transfer is paused. It is possible to suppress an increase in power consumption required for data transfer.

Therefore, it is possible to provide a liquid crystal display device which does not increase the power consumption even if the frame frequency is increased in order to eliminate the flicker and the beat phenomenon due to the FRC method.

Further, the liquid crystal drive circuit includes a storage unit for storing one frame of FRC data transferred from the FRC conversion circuit, and reads the FRC data from the storage unit to generate a liquid crystal drive voltage. May be.

In this case, the liquid crystal drive circuit is provided with the storage unit for storing one frame of the FRC data transferred from the FRC conversion circuit, so that there is a pause period in which the FRC data is not transferred to the liquid crystal drive circuit. However, since the FRC data transferred before the rest period exists in the storage unit,
During the idle period, the FRC data stored in the storage unit can be read to generate the liquid crystal drive voltage.

As a result, the FRC from the FRC conversion circuit
The liquid crystal drive circuit can continuously generate the liquid crystal drive voltage even when there is a rest period in which the data transfer is stopped. Therefore, the liquid crystal drive voltage is continuously applied to the liquid crystal display panel. be able to.

Therefore, in order to reduce the power consumption,
Even if the transfer of FRC data from the FRC conversion circuit to the liquid crystal drive circuit is stopped, the voltage applied to the liquid crystal display panel is not interrupted, so that the display deterioration of the liquid crystal display panel can be suppressed.

The storage unit stores 1 of FRC data.
Since only the frames are stored, the storage capacity is small, and the size of the IC chip forming the liquid crystal drive circuit can be reduced.

Further, the FRC conversion circuit may insert the pause frame so that the transfer period of the FRC data and the transfer pause period alternate.

In this case, since the FRC data transfer period to the liquid crystal drive circuit and the transfer suspension period alternate, the read timing of the FRC data stored in the storage section in the liquid crystal drive circuit is set to the FRC data transfer suspension period. It is possible to continuously generate the liquid crystal drive voltage by shifting the amount.

Thus, the liquid crystal drive voltage can be continuously applied to the liquid crystal display panel during the one-screen refresh period, so that the deterioration of display quality and the deterioration of display can be prevented.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION The following will describe one embodiment of the present invention. In addition, the liquid crystal display device according to the present embodiment, 64k color (R (red) data 5bit,
PWM for G (green) data 6bit, B (blue) data 5bit)
Method (pulse width modulation method) and FRC (Frame Rate C
ontrol) method.

The liquid crystal display device according to the present embodiment is shown in FIG.
As shown in FIG. 3, a liquid crystal panel (liquid crystal display panel) 1, a liquid crystal drive circuit 2, and an FRC conversion circuit 3 are included, and based on multi-gradation display data input from a host 4 which is an external video signal source. The liquid crystal panel 1 is adapted to display multi-gradation.

First, the liquid crystal panel 1 will be described.

The liquid crystal panel 1 is a simple matrix type liquid crystal panel and is adapted to display a desired image by applying a driving voltage to row electrodes and column electrodes arranged in a matrix not shown. There is. This drive voltage is
It is supplied from the liquid crystal drive circuit 2 as a liquid crystal drive voltage.

Next, the liquid crystal drive circuit 2 will be described.

The liquid crystal drive circuit 2 is a circuit for generating a liquid crystal drive voltage to be supplied to the liquid crystal panel 1 based on the FRC data transferred from the FRC conversion circuit 3, and a driver memory for storing the FRC data. (Storage unit)
5. A pulse width control unit 6 for generating a PWM signal for PWM (Pulse Width Modulation) control based on the FRC data stored in the driver memory 5, and a drive voltage generation for generating a liquid crystal drive voltage based on the PWM signal It has a section 7.

The driver memory 5 stores the FRC data transferred from the FRC conversion circuit 3 for each color component, that is, R.
Each GB is stored in a frame unit. Specifically, in the driver memory 5, the FRC data is stored as R
The components are stored as 3 bits (8 gradations), G component 3 bits (8 gradations), and B component 2 bits (4 gradations). The FRC data stored in the driver memory 5 is transferred to the pulse width control unit 6 in the subsequent stage as needed.

The pulse width control unit 6 is adapted to generate a PWM signal on the basis of FRC data in frame units transferred from the driver memory 5, and includes a clock selection unit 8 and a pulse width determination unit 9. I have it.

The pulse width determining unit 9 determines the pulse width of each frame of the FRC data transferred from the driver memory 5 based on the clock from the clock selecting unit 8 and generates a driving voltage for the subsequent stage as a PWM signal. It is adapted to be transferred to the section 7.

In the drive voltage generation section 7, based on the PWM signal for each color component transferred from the pulse width control section 6,
Drive voltage corresponding to each color component (liquid crystal drive voltage)
Are generated and applied to the row electrodes and the column electrodes provided in the liquid crystal panel 1.

In the liquid crystal drive circuit 2, drive control in the driver memory 5, the pulse width control unit 6, and the drive voltage generation unit 7 is performed by a control unit (not shown).

Next, the FRC conversion circuit 3 will be described.

The FRC conversion circuit 3 converts multi-gradation display data (hereinafter referred to as gradation data) from the host 4 into
It is a circuit for converting the data to be transmitted for each frame into thinned FRC data.
It is configured to include an RC table 11, a pause frame insertion unit 12, and a memory controller 13. In the present embodiment, the gradation data transferred from the host 4 to the FRC conversion circuit 3 will be described as display gradation data of 64k color.

The controller memory 10 is used by the host 4
Gradation data transferred from each color component, that is, RGB
It is designed to be temporarily stored every time. In particular,
In the controller memory 10, the gradation data is converted into the R component 5
bit (32 gradations), G component 6 bits (64 gradations), B component 5
It is designed to be stored as bits (32 gradations). The gradation data stored in the controller memory 10 is transferred to the FRC table 11 in the subsequent stage as needed.

The FRC table 11 has, for each color component,
The FRC data of four frames is converted according to each gradation level. Specifically, in the FRC table 11, 5 bit R component is converted into 4 frame data (3 bit × 4 frame) for 1 frame 3 bit data, and 6
The G component of bit is converted into 4 frames (3 bits x 4 frames) of data where 1 frame is 3 bits, and the B component of 5 bits is 4 frames of data where 1 frame is 2 bits (2 bits x 4 fram).
It is designed to be converted to e).

Here, four frames are one of the liquid crystal panel 1.
The FRC completion cycle indicates the frequency of the screen refresh rate. That is, in the FRC table 11, the gradation data of each color component is converted so that the FRC completion cycle is 4 frames as shown in FIG. 2B.

FR generated by the FRC table 11
The C data is adapted to be transferred to the rest frame insertion unit 12 in the subsequent stage.

The rest frame inserting section 12 is provided with the FR.
A pause frame for suspending the transfer of FRC data to the liquid crystal drive circuit 2 is inserted between arbitrary frames of a plurality of frames forming the C completion cycle. In this case, since the number of frames increases, the FRC completion cycle becomes longer, but the frame frequency of each frame is raised so that the completion cycle does not flicker. That is, rather than the frame frequency of the frame before the insertion of the pause frame,
The frame frequency of the frame after the insertion of the pause frame is changed to be higher.

In this embodiment, as shown in FIG. 2A, the pause frames are interleaved so that the frames for data transfer and the pause frames for suspending data transfer alternate. The inserted example will be described. In FIG. 2A, the frame frequency of each frame is increased without changing the FRC completion period shown in FIG. 2B, and a pause frame having the same frame frequency as the increased frame frequency is inserted. Therefore, in FIG. 2A, the frame for data transfer and the frame for data transfer suspension are combined to form an FRC completion cycle with eight frames. However, what is actually transferred to the liquid crystal drive circuit 2 is data of four frames other than the pause frame.

In this way, the pause frame is inserted in the FRC completion cycle, and the FRC data is controlled to be transferred frame by frame to the driver memory 5 of the liquid crystal drive circuit 2 by the memory controller 13. However, the data transfer to the liquid crystal drive circuit 2 is stopped during the period of four pause frames, and the data transfer to the liquid crystal drive circuit 2 is performed only during the remaining four frames.

The gradation display operation of the liquid crystal display device having the above structure will be described below.

First, display gradation data of 64k color is transferred from the host (HOST) 4 and input to the liquid crystal display device. The inputted display gradation data is temporarily held in the controller memory 10 in the FRC conversion circuit 3.

The display gradation data read from the controller memory 10 is converted into FRC data having an FRC completion cycle of 4 frames in the FRC table 11 according to the gradation level. The converted FRC data is transferred to the pause frame insertion unit 12, the frame frequency of the data transfer frame is increased, and a pause frame for pausing data transfer is inserted between the frames, and then the liquid crystal drive circuit 2 Is written in the driver memory 5 of The writing of the FRC data to the driver memory 5 is controlled by the memory controller 13.

Subsequently, in the liquid crystal drive circuit 2, the FRC data transferred from the FRC conversion circuit 3 is stored in the driver memory 5.
In the above, each frame is stored and transferred to the pulse width determination unit 9 of the pulse width control unit 6 for each frame.

In the pulse width determining section 9, the transferred F
A PWM signal for PWM control is generated based on the RC data and the clock output from the clock selection unit 8 and transferred to the drive voltage generation unit 7 in the subsequent stage.

Finally, the drive voltage generator 7 generates a liquid crystal drive voltage based on the transferred PWM signal and applies it to the liquid crystal panel 1.

As described above, in the liquid crystal display device having the above structure, the liquid crystal panel 1 is driven by the FRC control of 4 frames and the PWM control of each frame, and is displayed in 64k color. The liquid crystal drive circuit 2 including the driver memory 5, the pulse width control unit 6, and the drive voltage generation unit 7
And the FRC conversion circuit 3 including the controller memory 10, the FRC table 11, the pause frame insertion unit 12, and the memory controller 13 constitute a gradation control device.

In the liquid crystal display device having the above structure, the FRC
When the FRC data generated by the conversion circuit 3 is transferred from the FRC conversion circuit 3 to the liquid crystal drive circuit 2, a pause frame is inserted within the FRC completion cycle, so a pause period for data transfer occurs.

As a result, the power consumption required to transfer the FRC data from the FRC conversion circuit 3 to the liquid crystal drive circuit 2 can be reduced.

Further, since the liquid crystal drive circuit 2 is provided with the driver memory 5 for storing the FRC data for each frame, even if the data from the FRC conversion circuit 3 is disconnected, that is, from the FRC conversion circuit 3. Even if the data transfer to the liquid crystal drive circuit 2 is suspended, the image stored can be displayed by reading the data stored in the driver memory 5, that is, the data before the suspension.

Moreover, F generated by the FRC conversion circuit 3
The RC data is set to 1 in order to have the same period as the FRC completion period when a pause frame is not inserted in the FRC completion period.
The frame frequency of the frame is high. For example,
When the FRC completion cycle when the pause frame is not inserted is 4 frames and the FRC completion cycle when the pause frame is inserted is 8 frames, the frequency of one frame of the FRC completion cycle when the pause frame is inserted is the pause frame. It is twice the frequency of one frame when it is not inserted.

By increasing the frame frequency in this way, it is possible to prevent not only the beat phenomenon but also the flicker due to the FRC control.

Table 1 below shows a performance comparison regarding frame frequency, power consumption, flicker, and beat phenomenon.

[0068]

[Table 1]

Since the beat phenomenon is caused by the mutual interference between the commercial frequency and the frame frequency of the liquid crystal display device, it largely depends on the frame frequency and is 50 Hz, 60H.
This is a phenomenon that is affected by not only z but also doubled frequencies (100 Hz, 120 Hz) and appears as stripe noise on the liquid crystal display.

Flicker is a phenomenon caused by mutual interference between the commercial frequency and the FRC completion cycle (frequency of the refresh rate of one screen) which is the frequency for switching the screen of the liquid crystal. Therefore, since the FRC completion cycle is originally longer than the frame frequency, even if the frame frequency is as low as 90 Hz and the beat phenomenon appears, the flickering of the screen is difficult to be recognized. However, like the frame frequency, flicker may not be noticeable in a period in which the FRC completion period is a double period of the commercial frequency, but may be recognized.

As described above, the flicker is a phenomenon that appears as a flicker on the liquid crystal screen depending on the FRC completion period.
As can be seen from FIGS. 2A and 2B, the FRC completion cycle is made up of several frames.

Therefore, as can be seen from Table 1, when the frame frequency is increased, the flicker and beat phenomenon due to the FRC method are eliminated, but the power consumption increases.

However, in the liquid crystal display device of the present invention, as described above, it is possible to eliminate the flicker and the beat phenomenon by the FRC system while suppressing the increase of the current consumption by increasing the frame frequency.

That is, by providing the pause frame period in the FRC completion cycle, the number of frames for completing the gradation display of one screen by FRC control increases, but in order to suppress the horizontal stripe pattern beat phenomenon, the liquid crystal Since the frame frequency of panel 1 is higher than the original frame frequency (frame frequency that was able to suppress flickering due to FRC control), F
Since the RC completion cycle is the same as or longer than the original cycle,
Good gradation display by the FRC system can be obtained without display deterioration due to flicker.

Further, as shown in FIG. 2A, since the pause frames are inserted so that the FRC data transfer frames and the transfer pause frames alternate in the FRC completion cycle, the data transfer period, Pause frame periods are alternately provided.

As a result, even if the reading of the display data from the controller memory 10 in the FRC conversion circuit 3 and the writing of the FRC data to the driver memory 5 in the liquid crystal drive circuit 2 are stopped, one frame of FRC data is driven by the liquid crystal. Circuit 2
Since the FRC data is read from the driver memory 5 in the liquid crystal drive circuit 2 even during the pause frame period, data transfer according to the frame period can be omitted and low power consumption is achieved. It is possible to operate. Furthermore, since the voltage applied to the liquid crystal of the liquid crystal panel 1 is not interrupted, display deterioration can be suppressed.

Further, since the data is stored and read in units of one frame, the storage capacity of the driver memory 5 can be reduced.

Next, reduction of power consumption in the liquid crystal display device having the above structure will be described below with reference to FIGS. 3 and 4.

First, the frame frequency at which the beat phenomenon does not appear is examined. Figure 4 shows commercial frequencies of 50Hz and 60Hz
On the other hand, the degree of the beat phenomenon that appears on the liquid crystal panel display when the frame frequency is changed is visually evaluated by 4 ranks (none, slight beat, with beat, strong beat)
However, it is a graph. From this graph, it is understood that the frame frequency at which the beat phenomenon does not appear is 150 Hz or higher under both conditions of the commercial frequency of 50 Hz and 60 Hz.

Next, the power consumption is checked. Fig. 3 is 64k
6 is a graph showing the current consumption of the liquid crystal module when the frame frequency is changed during color display. In this graph, the FRC mode shown in FIG. 2B when the pause frame is not provided within the FRC completion cycle (conventional) and the FRC mode when the pause frame is provided within the FRC completion cycle shown in FIG. Mode (hereinafter, FSKIP (Frame Ski
The current consumption in the liquid crystal module in the p) mode) is compared.

In FIG. 3, the liquid crystal panel used is 1
/ 82Duty, response speed 150ms, usually 90Hz
It is driven at the frame frequency of.

Here, the liquid crystal panel is set to a commercial frequency of 60H.
When used in z, the beat phenomenon does not appear even in the reflection mode, and the display state is good, but the commercial frequency is 50 Hz.
When used in, a strong beat phenomenon appeared. At this time, the current consumption in the normal FRC mode is about 2.8 mA.
Met.

In order to suppress this beat phenomenon, the frame frequency was raised to the frame frequency of 150 Hz which was clarified in FIG. 4, but since some flicker due to FRC control remained,
Further increase the frame frequency to 180Hz, and FRC
Flicker due to control was eliminated. As a result, normal FR
In C mode, the current consumption was 4.5 mA.

Therefore, in the normal FRC mode, when the frame frequency is increased from 90 Hz to 180 Hz, the current consumption is from 2.8 mA to 4.5 mA, about 1.
It turned out to rise 6 times.

On the other hand, in the FSKIP mode in which the pause frame is provided during the FRC completion period, from the graph shown in FIG. 3, when the frame frequency is 90 Hz, the current consumption is 2.1 mA, and the frame frequency is increased to 180 Hz. In that case, the current consumption is 3.0 mA.

From the above, the frame frequency is 90H.
When z, the current consumption is 2.8 m in the normal FRC mode.
In contrast to A, the FSKIP mode consumes 2.1 mA, and the FSKIP mode has a normal FR.
It can be seen that the current consumption is smaller than that in the C mode.

When the frame frequency is 180 Hz, the current consumption is 4.5 mA in the normal FRC mode, while the current consumption is 3.0 in the FSKIP mode.
It is found that the current consumption is mA and that the FSKIP mode consumes less current than the normal FRC mode.

Therefore, when the frame frequency is raised to 180 Hz in order to prevent the flicker due to FRC control, the current consumption in the FSKIP mode is the normal F
It can be seen that the current consumption is reduced to about 66.7% of the current consumption in the RC mode.

Further, the liquid crystal display device of the present invention realizes gradation display by thinning out the data to be transmitted for each frame according to the gradation data, thereby changing the voltage value applied to the liquid crystal spatially and spatially. In a liquid crystal display device using the FRC method, gradation data is input to an FRC conversion circuit, and the FRC conversion circuit converts the display data to a display data corresponding to an FRC driving method and outputs the liquid crystal driving circuit by FRC control. A pause frame period in which the display data transfer period is paused may be provided between arbitrary frames required for completion.

In this case, by providing the pause frame period, the read operation of the memory in the FRC conversion circuit and the write operation in the memory of the liquid crystal drive circuit are stopped, the data change during that period is eliminated, and the power consumption is reduced. Has the effect of

In this embodiment, the FRC system and PW are used.
Although the example in which the M method is used in combination has been described, the present invention is not limited to this, and the FRC method alone may be used.
PH for controlling the amplitude of the liquid crystal drive voltage amplitude applied to the liquid crystal element according to the gradation data used in the TFT liquid crystal.
It may be combined with the M method (Pulse Height Modulation).

When the PHM method is used in this way, even if the amplitude of the on-voltage is modulated, the effective voltage value in the non-selected period can be kept constant, so that crosstalk can be prevented. Play.

In the present invention, another halftone display method that can be combined with the FRC system is amplitude modulation (AM).
Methods and voltage / pulse width modulation methods.

The AM method is basically the same as the PHM method in the sense that it drives the TFT liquid crystal. Therefore,
The effect of using the AM method is the same as the effect of using the PHM method.

Further, the voltage / pulse width modulation system can process the drive voltage digitally, unlike the analog drive of the amplitude modulation system. Therefore, when the voltage / pulse width modulation method is used, it is possible to reduce variations in voltage application to the liquid crystal.

[0096]

As described above, according to the liquid crystal display device of the present invention, in the liquid crystal display device which performs the multi-gradation display of the liquid crystal display panel by the frame thinning gradation (FRC) method, the multi-gradation display data is displayed. An FRC conversion circuit that thins out data for each frame and converts it into FRC data according to the number of gradations;
FR transferred from the FRC conversion circuit for each frame
A liquid crystal drive circuit for generating a liquid crystal drive voltage based on C data and applying the liquid crystal drive voltage to the liquid crystal display panel, wherein the FRC conversion circuit includes a plurality of liquid crystal display circuits necessary for refreshing one screen of the liquid crystal display panel. In this configuration, a pause frame that pauses the transfer of FRC data to the liquid crystal drive circuit is inserted between arbitrary frames of the frame.

Therefore, since the data transfer from the FRC conversion circuit to the liquid crystal drive circuit is performed intermittently,
Compared to the case where data transfer is continuously performed, less power consumption is required for data transfer. In particular, in order to eliminate the flicker and beat phenomenon caused by the FRC method, even when the data transfer has to be performed at high speed, such as when the frame frequency is increased, an increase in power consumption required for the data transfer is suppressed. There is an effect that can be.

Further, the liquid crystal drive circuit is provided with a storage section for storing one frame of FRC data transferred from the FRC conversion circuit, and the FRC data is read from the storage section to generate a liquid crystal drive voltage. May be.

Therefore, in order to reduce the power consumption, F
Even if the transfer of FRC data from the RC conversion circuit to the liquid crystal drive circuit is stopped, the voltage applied to the liquid crystal display panel will not be interrupted, so that the display deterioration of the liquid crystal display panel can be suppressed.

Further, the storage unit stores 1 of FRC data.
Since only the frames are stored, the storage capacity is small, and the size of the IC chip forming the liquid crystal drive circuit can be reduced.

Further, the FRC conversion circuit may insert the pause frames so that the transfer frames of the FRC data and the transfer pause frames alternate with each other.

Therefore, the transfer period of the FRC data to the liquid crystal drive circuit and the transfer suspension period alternate, so that the read timing of the FRC data stored in the storage section in the liquid crystal drive circuit is set to the transfer suspension period of the FRC data. The liquid crystal drive voltage can be continuously generated by shifting the amount.

As a result, since the liquid crystal drive voltage can be continuously applied to the liquid crystal display panel during the one-screen refresh period, it is possible to prevent deterioration of display quality and display deterioration.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 shows a frame structure of an FRC completion cycle, (a)
FIG. 3 is a diagram showing a frame configuration including a pause frame, and FIG. 6B is a diagram showing a frame configuration not including a pause frame.

FIG. 3 is a graph showing the relationship between frame frequency and current consumption.

FIG. 4 is a graph showing the degree of a beat phenomenon.

[Explanation of symbols]

1 Liquid crystal panel (liquid crystal display panel) 2 LCD drive circuit 3 FRC conversion circuit 5 Driver memory (storage unit) 6 Pulse width controller 7 Drive voltage generator 8 Clock selection section 9 Pulse width determination unit 10 Controller memory 11 FRC table 12 Pause frame insertion part 13 Memory controller

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 631 G09G 3/20 631B 633 633G 641 641E F term (reference) 2H093 NA10 NA33 NA55 ND03 ND06 ND34 5C006 AA14 AA15 AA17 AF03 AF04 AF06 AF44 AF69 BB12 BF02 FA23 FA44 FA47 GA03 5C080 AA10 BB05 CC03 DD06 DD22 DD26 EE29 FF12 GG08 GG09 GG12 GG17 JJ02 JJ05 KK07 KK47

Claims (3)

[Claims] 1. In a liquid crystal display device for performing multi-gradation display of a liquid crystal display panel by a frame thinning gradation method (FRC method), display data of multi-gradation is displayed for each frame according to the number of gradations. An FRC conversion circuit for thinning out and converting into FRC data, and an FR transferred from the FRC conversion circuit for each frame.
A liquid crystal drive circuit that generates a liquid crystal drive voltage based on C data and applies the liquid crystal drive voltage to the liquid crystal display panel, wherein the FRC conversion circuit includes a plurality of FRC conversion circuits necessary for refreshing one screen of the liquid crystal display panel. 2. A liquid crystal display device, wherein a pause frame for interrupting the transfer of FRC data to the liquid crystal drive circuit is inserted between arbitrary frames of the above frame. 2. The liquid crystal drive circuit includes a storage section for storing one frame of FRC data transferred from the FRC conversion circuit, and reads the FRC data from the storage section to generate a liquid crystal drive voltage. The liquid crystal display device according to claim 1, which is characterized in that: 3. The liquid crystal display device according to claim 2, wherein the FRC conversion circuit inserts a pause frame so that the FRC data transfer period and the pause period alternate.