JP2003315416A - Analytical method for scan test circuit, testing apparatus and semiconductor integrated-circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analytical method for a scan test circuit in which a flip-flop having a nonconformity in a shift operation in a flip-flop chain of the scan test circuit is specified in a short time even without using a special analyzer such as an EB tester or the like. <P>SOLUTION: A power-supply voltage (VDD) is changed (from 1.8 V to 2.2 V) only in a shift operation of a designated flip-flop, a flip-flop to be designated is changed, the shift operation is tested repeatedly, a hold margin (HM21) is eliminated on the basis of a fact that an output timing of shift data from a final-stage flip-flop becomes earlier than that in a normal operation, and a flip-flop (FFn) generating a shift error is specified. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for analyzing a scan test circuit, and more particularly to analyzing a shift operation of a flip-flop chain included in a scan test circuit for performing a scan test of a logic circuit, resulting in a shift error. The present invention relates to a technique for identifying a flip-flop in which a defect has occurred.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization of semiconductors, power supply drops, crosstalk, and noise generated in semiconductor integrated circuits due to difficulty in design verification cause problems of design failure, and the manufacturing process of semiconductor integrated circuits. In the above, the problem of voltage-dependent defects is becoming more prominent due to insufficient formation of contact portions. In particular, a flip-flop (hereinafter abbreviated as FF) chain of a scan test circuit has a small operation margin and is likely to cause a problem due to the nature of the circuit.

First, regarding these operation failure states,
This will be described with reference to FIGS. 20, 21A, 21B, 22A, 22B, 23A, and 23B.

FIG. 20 is a block diagram of a general scan test circuit which is a device under test (DUT). Figure 20
, 1201 is a scan test circuit, 1202 is an FF chain, 1203 is a combination circuit, 1204 is an input data (SDIN) terminal for scan test, and 12
Reference numeral 05 is a clock signal (CLK) terminal, 1206 is a scan enable signal (NT) terminal, and 1207 is a scan test output data (SDOUT) terminal. SDI
The N terminal 1204 and the CLK terminal 1205 are the FFs in the first stage FF1 in the FF chain 1202, respectively.
The chain is connected to the input data (DT) terminal and the clock signal (CK) terminal, and the output data (Q) terminal of the last stage FFm in the FF chain 1202 is connected to the SDOUT terminal 1207.

During the scan test, the SDIN terminal 120
The combinational circuit 1203
The data is set to, and the output signal of the combination circuit 1203 is output from the OUT terminal 1207, whereby the combination circuit 1203 is tested. Normally, before testing the combinational circuit 1203, the tests from FF1 to FFm in the FF chain 1202 are performed.

Next, F included in the FF chain 1202
A method of analyzing a malfunction of the FF chain from F1 to FFn will be described.

FIG. 21A is for FFs other than FFn1208, and FIG. 21B is for FFn1208.
7 is a graph showing dependence characteristics of a delay time of input data (DT) at a T terminal and a delay time of a clock signal (CK) at a CK terminal on a power supply voltage (VDD).

As shown in FIG. 21A, FFs other than FFn1208 always have a faster CK than DT within the use range of the power supply voltage VDD, but as shown in FIG. 21B, FFn12.
08 is CK for DT within the use range of the power supply voltage VDD
There is a region where the power consumption is early and a region where the power consumption is slow.
Has 2.0V as the border.

FIG. 22A shows the timing relationship between DT and CK when the power supply voltage of FFn1208 is lower than 2.0V, and FIG. 22B shows the power supply voltage of FFn1208 at 2.0V.
It is a figure which shows the timing relationship of DT and CK in the case of higher than. As shown in FIG. 22A, the power supply voltage VDD is 2.
When the voltage is lower than 0V, CK changes faster than DT, so that there is a sufficient hold margin HM.
8 works normally. However, as shown in FIG. 22B,
When power supply voltage VDD is higher than 2.0V, CK is DT
Since it changes more slowly, there is no hold margin HM,
The FFn 1208 is in the shift error state. Other F
F operates normally because CK always changes faster than DT.

FIG. 23A is a diagram showing the operation timing of the FF chain 1202 when the power supply voltage VDD is 1.8V and FIG. 23B is a diagram when the power supply voltage VDD is 2.2V. Scan enable signal NT is logic "1"
23. In this shift operation mode, when one pulse signal is input to the IN terminal 1204 in this shift operation mode, as shown in FIG. 23A, the power supply voltage VD
When D is 1.8V which is lower than 2.0V (during normal operation), the input pulse signal is shifted and mCLK
It is output from the OUT terminal 1207 to the eye. However, FIG.
As shown in FIG. 3B, when the power supply voltage VDD is 2.2 V which is higher than 2.0 V (during malfunction), the input pulse signal is shifted and OUT is output at the (m−1) th CLK.
It is output from the terminal 1207, and it can be seen that a shift error has occurred in the flip-flop chain 1202.

Next, in order to identify a defective FF, an EB (Electron Beam) tester or the like is used to
By the back trace method that goes back from the output of the chain 1202, the operational relationship between the input DT and the Q output of each FF is sequentially examined and analyzed from the FFm to the preceding stage.

[0012]

However, in the conventional method for specifying the FF in which the shift error occurs,
A special analysis device such as an EB tester is required, and after performing preparatory work such as grasping the operating state by the LSI tester, opening the package, and specifying the observation points on the layout, the EB tester backs up multiple nodes. The trace analysis had to be performed to identify the defective part, which required a long analysis time.

The present invention has been made in view of the above problems, and an object thereof is a flip-flop having a defect in a flip-flop chain of a scan test circuit without using a special analysis device such as an EB tester. It is an object of the present invention to provide a method for analyzing a scan test circuit capable of specifying the value in a short time, a test apparatus using the same, and a semiconductor integrated circuit device using the same.

[0014]

In order to achieve the above object, a method of analyzing a scan test circuit according to the present invention is such that a logic circuit and a plurality of flip-flops are connected in series to perform a scan test on the logic circuit. In a semiconductor integrated circuit device including a scan test circuit having a flip-flop chain, a method for analyzing the occurrence of shift error in the flip-flop chain, comprising: And a second power supply voltage that causes a shift error operation in the flip-flop chain, and a power supply voltage is set to the second power supply voltage during the shift operation of the flip-flop to be analyzed in the flip-flop chain, Other than flip-flop shift operation Sets the power supply voltage to the first power supply voltage and switches the power supply voltage between the first power supply voltage and the second power supply voltage to perform a shift operation test on all flip-flops included in the flip-flop chain. And a step of identifying a flip-flop in which a malfunction has occurred in the shift operation.

According to this structure, it is possible to identify a flip-flop having a defective shift operation in the flip-flop chain of the scan test circuit in a short time.

In order to achieve the above object, a first test apparatus according to the present invention is a test apparatus using the scan test circuit analyzing method according to the present invention, wherein the semiconductor integrated circuit device is a power supply voltage source. Power supply terminal (VDD
Terminal), an input data terminal (SDIN terminal) to which input data for scan test is supplied, a clock signal terminal (CLK terminal) to which a clock signal is commonly supplied to a plurality of flip-flops, and a plurality of flip-flops. An enable signal terminal (N to which an enable signal is commonly supplied
T terminal) and an output data terminal (SDOUT terminal) to which shift data is output from the final-stage flip-flop among the plurality of flip-flops, and a power supply voltage, input data, and clock signal supplied to the semiconductor integrated circuit device. ,
And an enable signal is generated, and a flip-flop having a defect in the shift operation is specified based on the shift data from the output data terminal.

According to this structure, a normal LSI tester is used to generate the signals necessary for the shift operation test without using a special analysis device such as an EB tester, and the shift data from the scan test circuit is received. By comparing with the expected value, it becomes possible to identify a flip-flop having a defective shift operation in a short time.

In order to achieve the above object, a second test apparatus according to the present invention is a test apparatus using the method for analyzing a scan test circuit according to the present invention, wherein the semiconductor integrated circuit device is a power supply voltage source. Power supply terminal (VDD
Terminal), an input data terminal (SDIN terminal) to which input data for scan test is supplied, a clock terminal (CLK terminal) to which a clock signal is commonly supplied to a plurality of flip-flops, and a common to a plurality of flip-flops Enable pin (NT pin) to which an enable signal is supplied to
And the output data terminal (SDOUT terminal) to which the shift data from the final stage flip-flop among the plurality of flip-flops is output, the test apparatus is configured to constantly operate the semiconductor integrated circuit device during the shift operation of the flip-flop chain. The semiconductor integrated circuit device is provided with a power supply voltage switching circuit that supplies a power supply voltage to a power supply terminal and switches between a first power supply voltage and a second power supply voltage and supplies the power supply terminal to the power supply terminal. The input data, the clock signal, and the enable signal to be supplied to are generated, and the flip-flop in which the shift operation is defective is specified based on the shift data from the output data terminal.

According to this structure, the power supply voltage switching circuit is provided between the LSI tester and the semiconductor integrated circuit device which is the device under test, so that the LSI can be tested by the test program.
Compared with the first test apparatus that controls the power supply driving device of the tester to switch the power supply voltage, the switching time of the power supply voltage can be shortened, and the inspection time can be greatly shortened.

In order to achieve the above-mentioned object, a first semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to the present invention is applied. The device has a first
A power supply terminal (VDD1 terminal) to which the power supply voltage of
An input data terminal (SDIN terminal) to which input data for shift operation test is supplied, and a clock terminal (CLK to which a clock signal is commonly supplied to a plurality of flip-flops
Terminal), an enable terminal (NT terminal) to which an enable signal is commonly supplied to a plurality of flip-flops, and an output data terminal (SDO) to which shift data is output from the last-stage flip-flop among the plurality of flip-flops.
UT terminal), a first power supply line (VDD1 line) connected to the first power supply terminal, a second power supply line (VDD2 line) to which a second power supply voltage is applied, and one input terminal The other input terminal is connected to the first power supply line and the other input terminal is connected to the second power supply line.
Power supply voltage switching circuits for switching the power supply voltages of the plurality of power supply voltages to the scan test circuit, and control terminals (S terminal, TES) to which control signals for the plurality of power supply voltage switching circuits are supplied.
T terminal).

According to this structure, by providing the power supply voltage switching circuit inside the semiconductor integrated circuit device which is the device under test, the power supply voltage switching time becomes equal to the operating time of the semiconductor integrated circuit device, and further, The inspection time can be shortened. Further, if the analysis is performed only at the time of the wafer probing inspection, it is not necessary to output the power source terminal for testing to the outside in the packaged product.

To achieve the above object, a second semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device to which the above-mentioned scan test circuit analysis method according to the present invention is applied. The device includes a first power supply terminal (VD) to which a power supply voltage for an input / output circuit is supplied during normal operation.
A DIO terminal), a second power supply terminal (VDI terminal) to which a power supply voltage for the internal logic circuit is supplied during normal operation, an input data terminal (SDIN terminal) to which input data for shift operation test is supplied, A clock terminal (CLK terminal) to which a clock signal is commonly supplied to a plurality of flip-flops, an enable terminal (NT terminal) to which an enable signal is commonly supplied to a plurality of flip-flops, and a final stage of the plurality of flip-flops. Output data terminal (SDOU) to which shift data is output from the flip-flop of
T terminal), a first power supply line (VDDIO line) connected to the first power supply terminal, a second power supply line (VDDI line) connected to the second power supply terminal, and one input terminal A plurality of power supplies which are connected to the first power supply line and whose other input terminal is connected to the second power supply line and which switch the power supply voltage for the input / output circuit and the power supply voltage for the internal logic circuit to supply to the scan test circuit. The power supply voltage switching circuit includes a voltage switching circuit and a control terminal (S terminal, TEST terminal) to which control signals for the plurality of power supply voltage switching circuits are supplied. When the second power supply voltage obtained in advance is lower than the first power supply voltage, the second power supply voltage is changed according to the control signal (S signal).
Select the power supply voltage for the internal logic circuit as the power supply voltage of
When the second power supply voltage obtained in advance is higher than the first power supply voltage, the power supply voltage for the input / output circuit is selected as the second power supply voltage.

According to this structure, when the semiconductor integrated circuit device has two power supply systems, one for the input / output circuit and the other for the internal logic circuit, these power supply voltages are switched to the scan test circuit to be supplied. There is no need to add a power supply line for testing as in the semiconductor integrated circuit device.

In order to achieve the above-mentioned object, a third semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device to which the above-mentioned scan test circuit analyzing method according to the present invention is applied. The device has a first
A power supply terminal (VDD1 terminal) to which the power supply voltage of
A first power supply line (VDD connected to the first power supply terminal)
1 line), a second power supply line to which a second power supply voltage is applied (VDD2 line), one input terminal is connected to the first power supply line, and the other input terminal is connected to the second power supply line. A plurality of power supply voltage switching circuits that are connected to each other and switch between the first power supply voltage and the second power supply voltage to supply the scan test circuit, and a test signal that supplies scan test input data and a clock signal to the scan test circuit. A generation circuit, a test number counting circuit that outputs a signal (Cycle) indicating the number of repetitions of the shift operation test of the flip-flop chain to the outside of the semiconductor integrated circuit, and a plurality of power supply voltage switching circuits, the analysis target according to the number of repetitions. Control signal generation circuit for supplying a control signal (power supply voltage switching signal S) for switching the power supply voltage during the shift operation of the flip-flop of And (power supply voltage switching signal generating circuit),
An expected value comparison circuit that compares the timing of the shift data output from the scan test circuit with the timing of the expected value signal and outputs the comparison result (JUDGE) to the outside of the semiconductor integrated circuit is provided. It is characterized in that the flip-flop in which the shift operation is defective is specified based on the output signal from the value comparison circuit.

According to this structure, while having the advantages of the first semiconductor integrated circuit device, a test signal generating circuit, a test number counting circuit, and a control signal are provided for the shift operation test of the flip-flop chain of the scan test circuit. By incorporating a self-test circuit (BIST circuit) including a generation circuit (power supply voltage switching signal generation circuit) and an expected value comparison circuit in a semiconductor integrated circuit device, an external control device can be provided as compared with the first semiconductor integrated circuit device. Does not depend on the operating speed of
A high-speed shift operation test can be performed within the operation limit of the semiconductor integrated circuit device.

In order to achieve the above object, a fourth semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device to which the above-mentioned scan test circuit analyzing method according to the present invention is applied. The device includes a first power supply terminal (VD) to which a power supply voltage for an input / output circuit is supplied during normal operation.
DIO terminal), a second power supply terminal (VDI terminal) to which a power supply voltage for the internal logic circuit is supplied during normal operation, and a first power supply line (VDDI) connected to the first power supply terminal.
O line), a second power supply line (VDDI line) connected to the second power supply terminal, one input terminal is connected to the first power supply line, and the other input terminal is connected to the second power supply line. Multiple power supply voltage switching circuits that are connected and switch the power supply voltage for the input / output circuit and the power supply voltage for the internal logic circuit to supply to the scan test circuit, and the input data and clock signal for scan test to the scan test circuit And a signal indicating the number of repetitions of the shift operation test of the flip-flop chain (Cy
control signal (power supply voltage) for switching the power supply voltage during the shift operation of the flip-flop to be analyzed according to the number of repetitions. The control signal generating circuit (power supply voltage switching signal generating circuit) that supplies the switching signal S) and the timing of the shift data output from the scan test circuit are compared with the timing of the expected value signal, and the comparison result (JUDGE) is stored in the semiconductor. An expected value comparison circuit for outputting to the outside of the integrated circuit is provided, and during the shift operation of the flip-flop to be analyzed, the plurality of power supply voltage switching circuits has a second power supply voltage determined in advance that is higher than the first power supply voltage. If it is low, the power supply voltage for the internal logic circuit is selected as the second power supply voltage in accordance with the control signal (S signal), and the second power supply obtained in advance is selected. When the voltage is higher than the first power supply voltage, the power supply voltage for the input / output circuit is selected as the second power supply voltage, and the shift operation fails based on the output signals from the test count circuit and the expected value comparison circuit. It is characterized in that the flip-flop in which is generated is specified.

According to this structure, in addition to having the advantages of the second semiconductor integrated circuit device, a test signal generating circuit, a test number counting circuit, and a control signal are provided for the shift operation test of the flip-flop chain of the scan test circuit. By incorporating a self-test circuit (BIST circuit) including a generation circuit (power supply voltage switching signal generation circuit) and an expected value comparison circuit in a semiconductor integrated circuit device, an external control device can be provided as compared with the second semiconductor integrated circuit device. Does not depend on the operating speed of
A high-speed shift operation test can be performed within the operation limit of the semiconductor integrated circuit device.

It is preferable that the first to fourth semiconductor integrated circuit devices include a delay element that delays and supplies the control signal (S signal) to at least one of the plurality of power supply voltage switching circuits. As a result, it is possible to prevent a plurality of power supply voltage switching circuits from opening simultaneously.

In order to achieve the above-mentioned object, a fifth semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to the present invention is applied. The device is connected to a power supply terminal (VDD terminal) to which a power supply voltage is externally supplied, a power supply line (VDD line) connected to the power supply terminal, and a power supply line, and is scanned based on a control signal (S signal). The power supply voltage in the test circuit is the power supply voltage (V
DD-Id × Rr), a plurality of power supply voltage drop circuits, and a control terminal (S terminal, TEST terminal) to which control signals for the plurality of power supply voltage drop circuits are supplied. During the shift operation, the plurality of power supply voltage drop circuits normally operate as the second power supply voltage according to the control signal (S signal) when the second power supply voltage obtained in advance is lower than the first power supply voltage. The power supply voltage (VDD- (Id + I
t) × Rr), and when the second power supply voltage obtained in advance is higher than the first power supply voltage, the power supply voltage for normal operation is set as the second power supply voltage.

According to this structure, for example, instead of the power supply voltage switching circuit of the fourth semiconductor integrated circuit device, a power supply voltage dropping circuit is incorporated in the semiconductor integrated circuit, whereby
In addition to the advantages of the semiconductor integrated circuit device, the power supply voltage to be supplied is only one (only VDD).

In the above configuration, the hole margin of the input data and the clock in each flip-flop (FF) forming the flip-flop chain of the scan test circuit changes depending on the power supply voltage. It focuses on the fact that the state of power supply voltage dependence is different. It is possible to change the power supply voltage only during the clock operation of the specified FF during the logical operation of the circuit, and by changing the specified FF and repeating the test, hold An FF with no margin can be specified. This makes it possible to perform analysis in a short time without using a special analysis device such as an EB tester.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a configuration diagram of a scan test circuit to which the scan test circuit analysis method according to the embodiment is applied.

In FIG. 1, 101 is a scan test circuit which is a device under test (DUT), 102 is a scan FF chain, 103 is a combinational circuit as a logic circuit, and 104 is input data for scan test (SDI).
N) terminal, 105 is a clock signal (CLK) terminal, 10
Reference numeral 6 is a scan enable signal (NT) terminal, and 107 is an output data (SDOUT) terminal for scan test. The SDIN terminal 104 and the CLK terminal 105 are FFs in the first FF1 of the FF chain 102, respectively.
The SDOUT terminal 107 is connected to the input data (DT) terminal and the clock (CK) terminal for the chain,
Output data (Q) of the last stage FFm in the F chain 102
It is connected to the terminal.

During the scan test, the SDIN terminal 104
The data input to the combination circuit 103 sets data in the combination circuit 103, and the output signal of the combination circuit 103 is output from the SDOUT terminal 107, whereby the combination circuit 103 is tested. 108 is the nth FF in the FF chain 102, and in the present embodiment,
It is assumed that the FF causes a shift error.

FIG. 2 is a block diagram of a test apparatus for the scan test circuit 101 of FIG. 1 using an LSI tester.
111 is a semiconductor integrated circuit device including the scan test circuit 101, 112 is an LSI tester, 113 is a power supply voltage (VDD) supply line to the scan test circuit (DUT) 101, 114 is a clock signal (CLK) line, and 115 is a scan test. Input data (SDIN) line, 116 is a scan test output data (SDOUT) line, and 117 is a scan enable signal (NT) line.

The VS terminal, DR1 terminal, DR2 terminal, DR3 terminal, and CMP terminal of the LSI tester 112 are the VDD terminal, CLK terminal, and SDIN of the DUT 101, respectively.
It is connected to the terminal, the NT terminal, and the SDOUT terminal. L
From the VS terminal of the SI tester 112, the power supply voltage VDD internally controlled by the program is supplied to the VDD supply line 11.
Is supplied to the VDD terminal of the DUT 111 via
From the DR1 terminal, the DR2 terminal, and the DR3 terminal of the I tester 112, the signals similarly generated by the program are CLK line 114, SDIN line 115, and NT line 1 respectively.
The CLK terminal, the SDIN terminal, and the NT terminal of the DUT 101 are input via 17, and the output data from the SDOUT terminal of the DUT 101 is input to the CMP terminal of the LSI tester 112. A comparison is made.

Next, the principle of identifying the FF in which the shift operation is defective in the FF chain 10 will be described.

FIG. 3A shows the power supply voltage of the FF other than FFn108, and FIG. 3B shows the delay time of the input data (DT) at the DT terminal and the delay time of the clock signal (CK) at the CK terminal in FFn108. (VDD)
It is a graph which shows the dependence characteristic with respect to.

As shown in FIG. 3A, in FFs other than FFn108, CK is always earlier than DT in the operating voltage range, but as shown in FIG.
In Fn108, D on the high voltage side within the working voltage range
There is a range (hatched portion) where CK is slower than T.
By design, DT and CK have the delay relationship shown in FIG. 3A,
Due to a manufacturing error such as a design error in device operation due to crosstalk between signal wires or a drop in power supply voltage, or a manufacturing problem such as an increase in resistance of contacts in a signal wire path,
Fn108 shows the delay relationship of FIG. 3B. In this embodiment, when VDD is 2.0 V or higher, C is higher than DT.
K will be slow. However, depending on the cause and the place of occurrence on the circuit, when VDD is small, C is higher than DT.
K may be delayed.

In FIG. 3A, the difference in timing between DT and CK when VDD is 2.2V (hereinafter referred to as hold margin HM) is HM11, and the hold margin HM when VDD is 1.8V is HM12. , FIG. 3B, hold margin H when VDD is 2.2V
Let M be HM21 and the hold margin HM when VDD is 1.8V be HM22.

Next, in FIG. 3B, the hold margin HM21
In order to check which FF the state of exists in, the hold margin HM only for the specific FF designated in one inspection
In the state of No. 21, that is, only when the clock of the specific FF is operating, the power supply voltage may be set to 2.2 V, which is high enough to eliminate the hold margin of DT with respect to CK. this,
This will be described with reference to FIGS. 4A and 4B.

FIGS. 4A and 4B are timing charts showing the power supply voltage VDD and the clock signal CLK and the hold margin HM of FIGS. 3A and 3B in the first and nth tests respectively in association with each other. In the first test of FIG. 4A, VDD is increased from 1.8V to 2.2V before the first CLK (1) rises, and 2
VDD is 2.2V before the second CLK (2) rises
To 1.8 V, and thereafter, VDD is kept at 1.8 V, and a shift operation test of the FF chain 102 is performed. In the nth test in FIG. 4B, the nth CLK
VDD rises from 1.8V to 2.2V before (n) rises
, VDD is lowered from 2.2V to 1.8V before the (n + 1) th CLK (n + 1) rises, and thereafter V
The shift operation test of the FF chain 102 is performed with DD kept at 1.8V. Similarly, in the (n + 1) th to mth tests, VDD is raised from 1.8V to 2.2V before one CLK rises, and the next CL
Before K rises, VDD is lowered from 2.2V to 1.8V, and a shift operation test is performed.

In FIG. 4A, FF1 to FF (n-1)
And the hold margin HM of FF (n + 1) to FFm is
During the shift operation of FF1 by CLK (1), hold margin HM11, FF2 to FF (n) by CLK (2) to CLK (n-1) and CLK (n + 1) to CLK (m).
−1) and the FF (n + 1) to FFm shift operations become the hold margin HM12, and the FFn hold margin HM becomes the hold margin HM22 during the CLK (n) shift operation.

In FIG. 4B, FF1 to FF (n-1)
And the hold margin HM of FF (n + 1) to FFm is
CLK (1) to CLK (n-1) and CLK (n + 1) to
Hold margin HM during shift operation by CLK (m)
12, the hold margin HM of FFn is CLK
(N) Hold margin HM21 during shift operation
Becomes A hold error occurs when the condition of the hold margin HM21 at which the hold margin HM disappears is given, that is, VDD occurs at the shift operation timing of FFn.
Is raised from 1.8V to 2.2V, a hold error occurs in the entire FF chain at the nth test.

5A and 5B respectively show 1- (n-1) and (n + 1) -m at which the shift operation is normally performed.
The input data SDI of the FF chain 102 in the nth test in which the shift error occurs and the nth test in which a shift error occurs
It is a figure which shows the timing relationship between N and output data SDOUT. As shown in FIG. 5A, when the shift operation is normal and one pulse signal is input to the SDIN terminal 104 of the DUT 101, the pulse input from the SDOUT terminal 107 at the timing of the m-th CLK (m). The signal is shifted and output. On the other hand, as shown in FIG. 5B, when a shift error occurs, the SDIN terminal 104
When one pulse signal is input to, the m-th CLK
(M-1) th CLK (m-) which is one earlier than (m)
At the timing of 1), the input pulse signal is shifted and output from the SDOUT terminal 107.

Next, the FF shift error is caused by the power supply voltage VD.
F that causes a shift error when it occurs on the low voltage side of D
The principle of identifying F will be described.

6A shows the power supply voltage of the FF other than FFn108, and FIG. 6B shows the delay time of the input data (DT) at the DT terminal and the delay time of the clock signal (CK) at the CK terminal in FFn108. (VDD)
It is a graph which shows the dependence characteristic with respect to.

As shown in FIG. 6A, in FFs other than FFn108, CK is always earlier than DT in the operating voltage range, but as shown in FIG. 6B, FFn
In 108, there is a range (hatched portion) where CK is slower than DT on the low voltage side within the operating voltage range. By design,
Although DT and CK have a delay relationship shown in FIG. 6A, in the present embodiment, when VDD is 2.0 V or less, CK becomes slower than DT as shown in FIG. 6B.

In FIG. 6A, when VDD is 2.2V, the hold margin HM is HM31 and VDD is 1.8V.
6B, the hold margin HM when the VDD is 2.2V is HM41, and the hold margin HM when the VDD is 1.8V is HM42 in FIG. 6B.

FIGS. 7A and 7B are timing charts showing the power supply voltage VDD and the clock signal CLK and the hold margin HM of FIGS. 6A and 6B in the first and nth tests respectively in association with each other. In the first test of FIG. 7A, VDD is lowered from 2.2V to 1.8V before the first CLK (1) rises, and 2
VDD is 1.8V before the second CLK (2) rises
To 2.2V, and thereafter, VDD is kept at 2.2V, and the shift operation test of the FF chain 102 is performed. In the nth test of FIG. 7B, the nth CLK
VDD rises from 2.2V to 1.8V before (n) rises
To VDD and raise VDD from 1.8V to 2.2V before the (n + 1) th CLK (n + 1) rises, and then V
The shift operation test of the FF chain 102 is performed with DD kept at 2.2V. Similarly, in the (n + 1) th to mth tests, VDD is lowered from 2.2V to 1.8V before one CLK rises, and the next CL
Before K rises, VDD is increased from 1.8V to 2.2V and a shift operation test is performed.

In FIG. 7A, FF1 to FF (n-1)
And the hold margin HM of FF (n + 1) to FFm is
During the shift operation of FF1 by CLK (1), FF2 to FF (n) by the hold margin HM32, CLK (2) to CLK (n-1) and CLK (n + 1) to CLK (m).
−1) and the FF (n + 1) to FFm shift operations become the hold margin HM31, and the FFn hold margin HM becomes the hold margin HM41 during the CLK (n) shift operation.

In FIG. 7B, FF1 to FF (n-1)
And the hold margin HM of FF (n + 1) to FFm is
CLK (1) to CLK (n-1) and CLK (n + 1) to
Hold margin HM during shift operation by CLK (m)
31 and the hold margin HM of FFn is CLK
(N) Hold margin HM42 during shift operation
Becomes A hold error occurs when the condition of the hold margin HM42 that eliminates the hold margin HM is given, that is, VDD is generated at the shift operation timing of FFn.
Is decreased from 2.2V to 1.8V, a hold error occurs in the entire FF chain at the nth test.

In FIGS. 8A and 8B, 1- (n-1) and (n + 1) -m, respectively, in which the shift operation is normally performed, are shown.
The input data SDI of the FF chain 102 in the nth test in which the shift error occurs and the nth test in which a shift error occurs
The timing relationship between N and the output data SDOUT is shown.
As shown in FIG. 8A, when the shift operation is normal, the DUT
When one pulse signal is input to the SDIN terminal 104 of 101, SD is input at the m-th CLK (m) timing.
From the OUT terminal 107, the input pulse signal is shifted and output. On the other hand, as shown in FIG. 8B, in the case where a shift error occurs, when one pulse signal is input to the SDIN terminal 104, the (m-1) th CLK which is one earlier than the mth CLK (m). At the timing of (m−1), the input pulse signal is shifted and output from the SDOUT terminal 107.

(Second Embodiment) In the first embodiment,
As shown in FIG. 2, the level of the power supply voltage VDD generated inside the LSI tester is switched and supplied to the VDD terminal of the DUT. However, the second embodiment of the present invention is such that the power supply voltage switching circuit is provided outside the LSI tester. Are provided, and the power supply voltages (VDD1, VDD) of different levels input to the power supply voltage switching circuit are provided.
2) is switched and supplied to the VDD terminal of the DUT.

FIG. 9 shows a second embodiment of the present invention.
It is a block diagram of the test apparatus of the scan test circuit using an LSI tester. In FIG. 9, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 9, 201 is a power supply voltage switching circuit, 202 is a power supply voltage switching signal (SS) line connecting the DR0 terminal of the LSI tester 112 and the SS terminal of the power supply voltage switching switching circuit 201, and 203 is a power supply. Voltage switching circuit 2
01 is a power supply voltage (VDD) supply line that connects the SY terminal of 01 and the VDD terminal of the DUT 101.

Next, the operation of the test apparatus thus constructed will be described with reference to FIG. As a premise, it is assumed that the FF having a defective shift operation has no hold margin of DT with respect to CK on the high voltage side shown in FIG. 3B, and VDD1 is 1.8V and VDD2 is 2.2V.

FIG. 10 is a timing chart of the signals of the respective parts of FIG. 9 in the n-th test. In FIG. 10, first, the scan enable signal NT rises from the logic "0" to the logic "1" to enter the shift operation mode. In the nth test, the power supply voltage switching signal SS from the DR0 terminal of the LSI tester 112 is logic "0" until the nth CLK (n) rises. At this time, the SY of the power supply voltage switching circuit 201 is SY. VDD1 = 1.8V is supplied as the power supply voltage VDD from the terminal to the VDD terminal of the DUT 101. Next, when the power supply voltage switching signal SS rises from the logic “0” to the logic “1”, the power supply voltage V is supplied from the SY terminal of the power supply voltage switching circuit 201 to the VDD terminal of the DUT 101.
VDD2 = 2.2V is supplied as DD.

When the power supply voltage switching signal SS from the DR0 terminal falls from the logic "1" to the logic "0" before the (n + 1) th CLK (n + 1) rises, the power supply voltage switching circuit 201 outputs the SY terminal. VDD1 = 1.8V is supplied as the power supply voltage VDD to the VDD terminal of the DUT 101. Thereafter, similarly to the m-th CLK (m), the DUT
VDD1 = 1.8V is supplied to the VDD terminal of 101.

FIG. 11A is a circuit diagram showing an example of the internal configuration of power supply voltage switching circuit 201 shown in FIG. FIG. 11A
In the figure, 301 is a switch controlled by the power supply voltage switching signal SS, and 302 and 303 are diodes. The SB terminal to which VDD2 (= 2.2 V) + Vf (Vf corresponds to the forward voltage of the diode 302) is supplied,
The SA terminal, which is connected to the anode of the diode 302 via the switch 301 and is supplied with VDD1 (= 1.8 V) + Vf (Vf corresponds to the forward voltage of the diode 303), is connected to the anode of the diode 303, The cathodes of 302 and diode 303 are commonly SY
Connected to the terminal.

Next, the operation of the voltage switching circuit 201 thus configured will be described with reference to FIG. 11B.
FIG. 11B is an SS of the power supply voltage switching circuit 201 shown in FIG.
FIG. 9 is a timing diagram of a power supply voltage switching signal at a terminal and a power supply voltage output from the SY terminal.

When the power supply voltage switching signal SS has the logic "0", the switch 301 is turned off, and VDD1 (= 1.8V) + Vf supplied to the SA terminal is lowered by the forward voltage Vf by the diode 303. Then, it is output as VDD1 from the SY terminal. On the other hand, when the power supply voltage switching signal SS is logic "1", the switch 301 is turned on and VDD1 (= 1.8) supplied to the SA terminal.
VDD2 (= supplied to the SB terminal rather than V) + Vf
2.2V) + Vf is large, the diode 303 is in the cutoff state, the diode 302 is in the conduction state, and VDD
2 (= 2.2V) + Vf is reduced by the forward voltage Vf by the diode 302 and output from the SY terminal as VDD2.

Power supply voltage switching circuit 20 as in this embodiment
By providing 1, the power supply voltage VDD to the DUT 101 can be increased during the test as compared to the voltage switching method using a general relay.
It is possible to prevent the power from becoming unpaid at the moment of switching.

Further, in the case of the first embodiment, the power supply driving device of the LSI tester 112 is controlled by the test program to switch the power supply voltage. Therefore, considering the switching time and the stability of the power supply voltage after switching, A power source voltage switching time of several milliseconds is required for each test, which is a large proportion of the entire inspection time, which is 99% or more. On the other hand, according to the present embodiment, by providing the power supply voltage switching circuit outside the LSI tester, the power supply voltage switching time can be significantly shortened.

Although the power supply voltage switching circuit 201 is composed of the switch 301 and the diodes 302 and 303 in the present embodiment, the present invention is not limited to this, and for example, a DC-DC converter with a voltage control terminal is used. May be.

(Third Embodiment) In the first embodiment,
The power supply voltage is switched inside the LSI tester, and in the second embodiment, the power supply voltage is switched by the power supply voltage switching circuit provided between the LSI tester and the semiconductor integrated circuit device. However, the third embodiment of the present invention Has a structure in which a power supply voltage switching circuit is provided inside the semiconductor integrated circuit device.

FIG. 12 is a schematic diagram showing the internal structure of a semiconductor integrated circuit device to which the scan test circuit analyzing method according to the third embodiment of the present invention is applied.

In FIG. 12, 401 is a semiconductor integrated circuit device, 402 is a scan test circuit, 403, 404,
405 and 406 are power supply voltage switching circuits, 407 is VDD1
Power line (used during normal operation and test), 40
Reference numeral 8 is a VDD2 power supply line (used during testing), and 409 is a delay element.

The VDD1 power supply line 407 is connected to the VDD1 terminal of the semiconductor integrated circuit device 401 and the power supply voltage switching circuit 40.
3 to 406, and the VDD2 power supply line 408 is connected to VDD2 of the semiconductor integrated circuit device 401.
The terminals are connected to the other input terminals of the power supply voltage switching circuits 403 to 406. Further, the power supply voltage switching circuits 403-40
The output terminal of 6 is connected to the VDDs terminal of the scan test circuit 402. The CLK terminal, SDIN terminal, NT terminal, and SDOUT terminal of the semiconductor integrated circuit device 401 are terminals for scan test. The TEST terminal is directly connected to the power supply voltage switching circuits 403 to 406, and the S terminal is directly connected to the power supply voltage switching circuits 403 and 404.
In addition, the power supply voltage switching circuit 405 via the delay element 409,
It is connected to 406. The delay element 409 has a function of preventing the power supply voltage switching circuits 403 to 406 from being simultaneously opened when switching.

13A and 13B are a circuit diagram and an operation timing diagram showing the internal structure of power supply voltage switching circuits 403 to 406 of FIG. 12, respectively.

During normal operation, the TEST signal is always set to logic "0" in order to select VDD1 (test invalid section). On the other hand, during the test, the TEST signal becomes logic "1", the S signal from the S terminal becomes valid, and if the S signal is logic "0", VDD1 is selected and the S signal becomes logic "1". If there is, VDD2 is selected (test valid section). Also, at the time of test, VDD1 and VDD
Any voltage of 2 may be high.

As described above, according to this embodiment, the power supply voltage switching time is equal to the operating time of the semiconductor integrated circuit device. Further, if the analysis is performed only at the time of the wafer probing inspection, it is not necessary to output the VDD2 terminal to the outside in the packaged product.

(Fourth Embodiment) In the third embodiment,
Although the power supply voltage corresponding to the normal operation is only one VDD1, the fourth embodiment of the present invention has a structure in which the power supply voltage switching circuit is provided in the semiconductor integrated circuit device having a plurality of power supply systems.

FIG. 14 is a schematic diagram showing the internal structure of a semiconductor integrated circuit device to which the scan test circuit analyzing method according to the fourth embodiment of the present invention is applied.

In FIG. 14, 601 is a semiconductor integrated circuit device, 602 is a scan test circuit, and 603 and 604.
Reference numerals 605 and 606 are power supply voltage switching circuits, 607 is a VDDI (low voltage) power supply line for internal logic circuits, 608 is a VDDIO (high voltage) power supply line for input / output circuits, and 60.
Reference numeral 9 is a delay element.

The VDDI power supply line 607 is connected to the VDDI terminal of the semiconductor integrated circuit device 601 and the power supply voltage switching circuit 60.
3 to 606, the VDDIO power supply line 608 is connected to one of the input terminals of the semiconductor integrated circuit device 601.
It is connected to the IO terminal and the other input terminal of the power supply voltage switching circuits 603 to 606. In addition, the power supply voltage switching circuit 603 to
The output terminal of 606 is VDD of the scan test circuit 602.
connected to the s terminal. CL of the semiconductor integrated circuit device 601
The K terminal, the SDIN terminal, the NT terminal, and the SDOUT terminal are terminals for scan test. The TEST terminal is directly connected to the power supply voltage switching circuits 603 to 606,
The S terminal is directly connected to the power supply voltage switching circuits 603 and 604, and the power supply voltage switching circuit 6 is connected via the delay element 609.
05 and 606. The delay element 409 has a function of preventing the power supply voltage switching circuits 403 to 406 from being simultaneously opened when switching.

FIGS. 15A and 15B are a circuit diagram and an operation timing diagram showing the internal configuration of power supply voltage switching circuits 603 to 606 of FIG. 14, respectively.

During normal operation, the TEST signal is always set to logic "0" to select VDDI (test invalid section). On the other hand, during the test, the TEST signal becomes logic "1" (test valid period), the MODE signal and the S signal from the MODE terminal and the S terminal are respectively valid, and the switching operation of the power supply voltage between VDDI and VDDIO is performed. Is performed, and a specific flip-flop FF is brought into a state without a hold margin.

By setting the MODE signal to the state of logic "0" in the test effective section, it is possible to test the FF which causes the shift error on the low power supply voltage side. That is, at the shift timing of the FF other than the analysis target, the S signal is set to the logic “0”, and V of higher voltage is applied.
The DDIO is supplied to the VDDs terminal of the scan test circuit, and at the shift timing (ER section) of the FF to be analyzed, the S signal is set to logic "1" to lower the VDDI voltage.
Is supplied to the VDDs terminal of the scan test circuit, it is possible to identify the FF that causes the shift error on the low power supply voltage side.

On the other hand, in the test valid section, MODE
By setting the signal to the logic “1” state, it is possible to perform a test on the FF that causes a shift error on the high power supply voltage side. That is, at the shift timings of the FFs other than the analysis target, the S signal is set to logic “0”, VDDI of lower voltage is supplied to the VDDs terminal of the scan test circuit, and the shift timings of the FFs to be analyzed (ER section).
Then, set the S signal to logic "1" and set VDD to a higher voltage.
By supplying IO to the VDDs terminal of the scan test circuit, it is possible to identify the FF that causes the shift error on the low power supply voltage side.

As described above, according to the present embodiment, when the semiconductor integrated circuit device has two power supply systems, those power supply voltages are switched to the scan test circuit and supplied, whereby the third embodiment can be realized. Such an additional VDD2 power supply line is unnecessary.

(Fifth Embodiment) Next, as a fifth embodiment of the present invention, a self-test circuit for performing a shift operation test of an FF chain of a scan test circuit in a semiconductor integrated circuit device according to the fourth embodiment. The case of incorporating is described with reference to FIGS. 16, 17A and 17B.

FIG. 16 is a schematic diagram showing the internal structure of a semiconductor integrated circuit device to which the scan test circuit analyzing method according to the fifth embodiment of the present invention is applied.

In FIG. 16, reference numeral 801 is a semiconductor integrated circuit device, 802 is a scan test circuit, and 803 is a built-in self test for testing an FF chain.
Test: Hereinafter, abbreviated as BIST) circuit, 804, 80
5, 806 and 807 are power supply voltage switching circuits, 808 is a VDD1 power supply line for internal logic circuits, 809 is a VDD2 power supply line for input / output circuits, and 810 is a delay element.

The VDD1 power supply line 808 is connected to the VDD1 terminal of the semiconductor integrated circuit device 801 and the power supply voltage switching circuit 80.
4 to 807, the VDD2 power supply line 809 is connected to VDD2 of the semiconductor integrated circuit device 801.
The terminals are connected to the other input terminals of the power supply voltage switching circuits 804 to 807. Further, the power supply voltage switching circuits 804-80
The output terminal of 7 is connected to the VDDs terminal of the scan test circuit 802.

The TEST terminal of the semiconductor integrated circuit device 801 is connected to the power supply voltage switching circuits 804 to 807 and the BIST.
It is connected to the TEST terminal of the circuit 803.

The NT terminal, CLK terminal, SDIN terminal and SDOUT terminal of the BIST circuit 803 are respectively the NT terminal, CLK terminal and SDI of the scan test circuit 802.
It is connected to the N terminal and the SDOUT terminal. Also, BI
ST circuit 803 END terminal, Cycle terminal, JUD
The GE terminals are respectively E of the semiconductor integrated circuit device 801.
It is connected to the ND terminal, Cycle terminal, and JUDGE terminal, and indicates that the predetermined number of tests (m) has been completed.
D signal, Cycle signal indicating the current number of tests, FF
A JUDGE signal indicating the result of the chain shift operation test is output to the outside. The BIST 803 generates the NT signal, the CLK signal, and the SDIN signal necessary for the shift operation test of the FF chain of the scan test circuit 802, supplies them to the scan test circuit 802, receives the SDOUT signal from the scan test circuit 802, and performs the shift operation test. The result of is output to the outside from the JUDGE terminal. In addition,
Supply of input signals to the NT terminal and TEST terminal of the semiconductor integrated circuit device 801, and its END terminal, JUDGE
Read the output signal from the terminal and Cycle terminal with L
The SI tester is used.

FIG. 17A shows the BIST circuit 803 of FIG.
3 is a circuit diagram showing an example of the internal configuration of FIG. In FIG. 17A, 911 is a clock generator, 912 is a shift counter capable of setting the maximum count value necessary for counting the shift operation of the FF chain by the number of FF stages, and 913 is the number of tests for the number of FF chain stages. A cycle counter capable of setting the maximum count value required for the operation, 914 and 915 are comparators, 916 is a delay element, 917 and 918 are D-type flip-flops (hereinafter abbreviated as D-FF) with a reset terminal, and 922 is It is an AND gate. Where 91
7 is a D-FF for expected value comparison, which constitutes an expected value comparison circuit.

The clock generator 911 is composed of a PLL circuit, a self-oscillation circuit, etc., and outputs a clock signal Po. In this embodiment, the clock generator 911 is set to B
Although provided inside the IST circuit 803, an external clock signal may be used.

The clock signal Po from the clock generator 911 is supplied to the CK terminal of the D-FF 918, and its D
The TEST signal supplied to the terminal rises from the logic "0" to the logic "1" at the next rising edge of the clock signal Po, the FFQ signal from the Q terminal becomes the logic "1", and the AND gate 922 and the delay element 916 are connected. The clock signal Po is supplied as a CLK signal from the CLK terminal to the scan test circuit 802 via the.

The shift counter 912 counts the clock signal Po from the clock generator 911 and outputs the count value S
O reaches the set value (m + 1) of the SET terminal (F of m stages
When the shift operation of F is completed), the Cos signal of logic “1” is output to the CK terminal as the clock signal of the cycle counter 913 and the D-FF 917.

The comparator 914 is a shift counter 9
The count value SO from 12 is compared with the logic "1", and when the values match, the signal of the logic "1" is output to the SDIN terminal as the SDIN signal of the scan test circuit 802. Here, the delay element 916 is provided to adjust the phases of the SDIN signal and the CLK signal to the scan test circuit 802.

The shift counter 912 and the comparator 9
14 and the delay element 916 constitute a shift test signal generating circuit.

The cycle counter 913 counts the Cos signal from the shift counter 912, and the counted value is S.
When the set value (m + 1) of the ET terminal is reached (the test for m times is completed), the Coc signal of logic "1" is output to the END terminal as the END signal.

The comparator 915 is a shift counter 9
12 count value SO and cycle counter 913 count value C
O is compared, and when the values match, a signal of logic "1" is output to the S terminal as a power supply voltage switching signal (S signal) of the power supply voltage switching circuits 804 to 807.

The shift counter 912 and the cycle counter 913 form a test number counting circuit, and the shift counter 912, the cycle counter 913 and the comparator form a power supply voltage switching signal generating circuit.

The D-FF 917 for expected value comparison is the D
SDOUT, which is shift data from the scan test circuit 802 input to the terminal, is latched by the Cos signal from the shift counter 912 input to the CK terminal, and the FF chain of the scan test circuit 802 performs a normal shift operation. If a shift error occurs in the FF chain of the scan test circuit 802, a logic "0" is output as a JUDGE signal and JUDG is output as a JUDGE signal.
Output to E terminal.

Next, in addition to FIGS. 16 and 17A, a method for identifying an FF having a defective shift operation by the BIST circuit 803 configured as described above will be described with reference to FIG.
This will be described with reference to B. FIG. 17B shows B shown in FIG. 17A.
FIG. 11 is a diagram showing an operation timing of the IST circuit 803.

First, when the TEST signal from the TEST terminal changes from the logic "0" to the logic "1", the reset is released and the D-FF 918 outputs the next rising timing of the clock signal Po from the clock generator. FFQ
The signal becomes logic “1”, and the clock signal Po is supplied to the shift counter 912 via the AND gate 922. The shift counter 912 starts counting the clock signal Po and outputs the count value SO.

When the count value SO of the shift counter 912 is "1", the logic "1" is output from the comparator 914, the input data SDIN of the scan test circuit is generated and output from the SDIN terminal. Further, after the reset is released, the clock signal Po from the clock generator 911
Is output from the CLK terminal via the delay element 916 with a delay of the timing indicated by Delay in the figure. This D
The delay value is set to a value in which the hold margin of the input data SDIN with respect to the CLK signal is sufficient in the first stage FF1 in the FF chain of the scan test circuit 802.

The cycle counter 913 counts the carry-out signal Cos output each time the count value SO from the shift counter 912 becomes m, and outputs the count value CO. When the count value SO of the shift counter 912 reaches m, one shift test of the scan FF chain ends, so that the cycle counter 913 is completed.
The Cycle signal, which is the count value CO of, indicates the number of tests.

The count value SO from the shift counter 912 and the count value CO from the cycle counter 913 are compared by the comparator 915, and the count value SO of the shift counter 912 becomes i at the i-th (i = 1 to m) test. At this time, a logic "1" is output to the S terminal, and the power supply voltage switching circuits 804-8
The power supply switching of 07 is performed.

When the predetermined number of tests (m + 1) is completed, the carry-out signal Coc of logic "1" from the cycle counter 913 indicates END indicating the end of the shift test.
The signal is output to an external device such as an LSI tester via the END terminal.

The output data SDOUT from the scan test circuit 802 has a count value SO of the shift counter 912 of m when the shift operation test of each time is normally completed.
When a shift error (Error) occurs in a certain test, the shift counter 9
It is output before the count value SO of 12 reaches m.
Therefore, when the CK signal of the D-FF 917, which is the Cos signal from the shift counter 912, rises,
In the normal operation, the output data SDOUT of logic “0” is input to the D terminal of the D-FF 917, but when a shift error occurs, the output data SDOUT of logic “1” is input to the D terminal of the FF 917. Is output from the Q terminal of the D-FF 917 to the JUDG of logic “1”.
The E signal is output to the JUDGE terminal. Therefore, JUG
By monitoring the DE signal with an LSI tester or the like and reading the value of the Cycle signal at the time when the logic "1" is output, that is, the number of times of testing, the FF having the shift operation failure can be specified.

In this embodiment, the case where the master and the test circuit 802 have one FF chain is exemplified. However, when there are a plurality of FF chains, a plurality of expected value comparison circuits are provided or one is provided. A selector may be provided for selectively switching the FF chain to be tested with respect to one expected value comparison circuit.

If the FF chains have different lengths, the shift counter 912 and the cycle counter 91 are
The count setting value m of 3 may be changed according to the number of stages in the chain.

As described above, according to the present embodiment, by incorporating the BIST circuit for the scan test circuit in the semiconductor integrated circuit device, the operation limit of the semiconductor integrated circuit device does not depend on the operation speed of the external control device. High-speed shift operation test is possible.

(Sixth Embodiment) Next, as a sixth embodiment of the present invention, referring to FIGS. 18, 19A and 19B, in the case of incorporating a power supply voltage drop circuit into a semiconductor integrated circuit device. explain.

FIG. 18 is a schematic diagram showing the internal structure of a semiconductor integrated circuit device to which the scan test circuit analyzing method according to the sixth embodiment of the present invention is applied.

In FIG. 18, 1001 is a semiconductor integrated circuit device, 1002 is a scan test circuit, 1003, 1
004, 1005, 1006 are power supply voltage drop circuits, 10
Reference numeral 07 is a power supply (VDD) line. The output terminals of the power supply voltage drop circuits 1003 to 1006 are scan test circuits 1
002 VDD line 1007. The TEST terminal and the S terminal of the semiconductor integrated circuit device 1001 are connected to the input terminals of the power supply voltage dropping circuits 1003 to 1006.

The power supply line 1007 is formed of metal such as aluminum and has a small resistance value Rr. The resistivity is about 0.1Ω, the wiring width is 100 μm, and the length is 500.
If it is μm, the resistance value Rr becomes 0.5Ω.

FIG. 19A shows an internal structure of power supply voltage down circuits 1003 to 1006 shown in FIG. 18 and a connection relation between scan power supply circuit and scan test circuit 1002.

In FIG. 19A, the power supply voltage dropping circuit 10
03 to 1006 are connected to the VDD line 1007 and the ground (GN
D) arranged between the AND gate 1010 for receiving the TEST signal and the S signal, the transistor 1011 having the gate connected to the output terminal of the AND gate 1010 and the drain connected to the VDD power line, and the transistor 1011 at one end. 1011 connected to the source and the other end is GN
A resistance element 101 having a resistance value Rt connected to the D terminal
2 and. Here, the resistance element 1012 is formed in the semiconductor integrated circuit using a semiconductor integrated circuit manufacturing process, and is formed of a polysilicon wiring or a MOS transistor.

During normal operation, the power supply current Id flows from the VDD terminal of the semiconductor integrated circuit device 1001 to the VDDs terminal of the scan test circuit 1002, and the transistor 101
When 1 is turned on, a current It (= VDDs / Rt) flows. The voltage drop value of VDDs due to the current It is It is 1
Assuming that 00 mA and Rt are 0.5Ω, it becomes 50 mV.

Next, the power supply voltage drop circuits 1003 to 1003 to 10 at the time of analysis for identifying the FF having the shift operation failure.
The operation of 06 will be described with reference to FIG. 19B. 19B is a diagram showing operation timings of the TEST signal, the S signal, and the power supply voltage VDDs of FIG. 19A.

In FIG. 19B, first, when the TEST signal becomes the logic "1", the S signal becomes valid by the AND gate 1010. Next, if the S signal is a logic "0", the transistor 1011 is off and VDDs
= VDD−Id × Rr, and when the S signal has a logic “1”, the transistor 1011 is on and VD
Ds = VDD- (Id + It) * Rr. In this way, the power supply voltage VDDs is within the range of the voltage drop value of It × Rr.
Can be switched. Power supply current Id during normal operation
Can be estimated at the time of design, and the resistance value Rt can be determined from the voltage drop value required at the time of analysis and incorporated in the design in advance.

As described above, according to this embodiment, one power supply voltage can be supplied by incorporating the power supply voltage down circuit in the semiconductor integrated circuit.

[0119]

As described above, according to the present invention,
Specified F at the time of shift operation test of scan FF chain
By changing the power supply voltage in accordance with the shift operation of F, it is possible to specify a defective FF that causes a shift error in a short time without using a special analysis device such as an EB tester. This is very effective especially for analysis of contact formation and analysis of timing design issues that occur as the manufacturing of semiconductor integrated circuits shifts to a fine process.

Further, by providing a power supply voltage switching circuit between the LSI tester and the device under test, and further incorporating the power supply voltage switching circuit in the semiconductor integrated circuit device as the device under test, the power supply voltage can be switched at high speed. Therefore, the shift operation test can be performed in a shorter time and at an actual speed.

Further, by incorporating the self-test circuit in the semiconductor integrated circuit device, if a PLL circuit or the like is used for clock generation, analysis at an actual speed independent of the LSI tester or failure analysis at the operation limit of the semiconductor integrated circuit is performed. It becomes possible to perform the design verification for the operating frequency and the performance evaluation of the manufacturing of the semiconductor integrated circuit device.

Therefore, the present invention has the above-mentioned special effects which have not been obtained conventionally.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a scan test circuit to which a scan test circuit analysis method according to a first embodiment of the present invention is applied.

FIG. 2 is a configuration diagram of a test device for a scan test circuit using an LSI tester according to the first embodiment of the present invention.

FIG. 3A shows a delay time of input data (DT) at a DT terminal and a delay time of a clock signal (CK) at a CK terminal in FFs other than FFn108 in FIG. , Power supply voltage (VD
A graph showing the dependence characteristics on D)

FIG. 3B is a diagram illustrating the power supply voltage (VDD) of the delay time of the input data (DT) at the DT terminal and the delay time of the clock signal (CK) at the CK terminal in the FFn 108 of FIG. ) Graph showing the dependence characteristics on

FIG. 4A is a diagram showing a power supply voltage VDD and a clock signal CLK in the first test performed by the test apparatus of FIG.
Timing diagram corresponding to the hold margin HM of FIG. 3A

4B shows the power supply voltage VDD and the clock signal CLK in the n-th test by the test apparatus of FIG.
Timing diagram corresponding to the hold margin HM of FIG. 3B

FIG. 5A is a FF chain 102 in the 1st to (n−1) th and (n + 1) th to mth tests in which the shift operation is normally performed for FFs other than FFn108 in which the hold margin is reduced on the high power supply voltage side. Input data SDI
Diagram showing the timing relationship between N and the output data SDOUT

FIG. 5B: F with no hold margin on the high power supply voltage side
A diagram showing a timing relationship between the input data SDIN and the output data SDOUT of the FF chain 102 in the nth test in which a shift error occurs in Fn108.

FIG. 6A shows a delay time of input data (DT) at a DT terminal and a delay time of a clock signal (CK) at a CK terminal in FFs other than FFn108 in FIG. , Power supply voltage (VD
A graph showing the dependence characteristics on D)

FIG. 6B is a diagram showing the power supply voltage (VDD) of the delay time of the input data (DT) at the DT terminal and the delay time of the clock signal (CK) at the CK terminal in the FFn 108 of FIG. ) Graph showing the dependence characteristics on

7A is a diagram illustrating a power supply voltage VDD and a clock signal CLK in a first test performed by the test apparatus of FIG.
Timing diagram showing the hold margin HM of FIG. 6A in association with each other.

7B shows the power supply voltage VDD and the clock signal CLK in the n-th test by the test apparatus of FIG.
Timing diagram showing the hold margin HM of FIG. 6B in association with each other.

FIG. 8A is a FF chain 102 in the 1st to (n−1) th and (n + 1) th to mth tests in which the shift operation is normally performed for the FFs other than the FFn108 in which the hold margin decreases on the low power supply voltage side. Input data SDI
Diagram showing the timing relationship between N and the output data SDOUT

FIG. 8B: F with no hold margin on the low power supply voltage side
A diagram showing a timing relationship between the input data SDIN and the output data SDOUT of the FF chain 102 in the nth test in which a shift error occurs in Fn108.

FIG. 9 is a configuration diagram of a test device for a scan test circuit using an LSI tester according to a second embodiment of the present invention.

FIG. 10 is a timing diagram of signals at various parts in FIG. 9 in the n-th test.

11A is a circuit diagram showing an example of an internal configuration of a power supply voltage switching circuit 201 shown in FIG.

11B is an S diagram of the power supply voltage switching circuit 201 shown in FIG.
Timing diagram of power supply voltage switching signal at S terminal and power supply voltage output from SY terminal

FIG. 12 is a schematic diagram showing an internal configuration of a semiconductor integrated circuit device to which a scan test circuit analysis method according to a third embodiment of the present invention is applied.

FIG. 13A is a power supply voltage switching circuit 403 shown in FIG.
Circuit diagram showing the internal configuration of 406 and its operation timing diagram

13B is a diagram showing the power supply voltage switching circuit 403 shown in FIG.
406 operation timing chart

FIG. 14 is a schematic diagram showing an internal configuration of a semiconductor integrated circuit device to which a scan test circuit analysis method according to a fourth embodiment of the present invention is applied.

FIG. 15A is a power supply voltage switching circuit 603 shown in FIG.
Circuit diagram showing the internal configuration of 606 and its operation timing diagram

FIG. 15B is a diagram showing the power supply voltage switching circuit 603 shown in FIG.
Operation timing chart of 606

FIG. 16 is a schematic diagram showing an internal configuration of a semiconductor integrated circuit device to which a scan test circuit analyzing method according to a fifth embodiment of the present invention is applied.

17A is a circuit diagram showing an example of an internal configuration of a BIST circuit 803 shown in FIG.

FIG. 17B is a diagram showing an operation timing of the BIST circuit 803 shown in FIG. 17A.

FIG. 18 is a schematic diagram showing an internal configuration of a semiconductor integrated circuit device to which a scan test circuit analyzing method according to a sixth embodiment of the present invention is applied.

FIG. 19A is a power supply voltage down circuit 1003 shown in FIG.
To 1006 and a connection relationship between the internal configuration and scan test circuit 1002

FIG. 19B is a diagram showing operation timings of the TEST signal, the S signal, and the power supply voltage VDDs of FIG. 19A.

FIG. 20 is a configuration diagram of a conventional scan test circuit.

21A is a DT other than FFn1208 in FIG. 20, and FIG. 21B is a DT in FFn1208.
The power supply voltage (V) of the delay time of the input data (DT) at the terminal and the delay time of the clock signal (CK) at the CK terminal
A graph showing the dependency characteristic for DD)

FIG. 21B shows a DT in the FFn 1208 of FIG.
The power supply voltage (V) of the delay time of the input data (DT) at the terminal and the delay time of the clock signal (CK) at the CK terminal
A graph showing the dependency characteristic for DD)

22A is a diagram showing a timing relationship between DT and CK when the power supply voltage of FFn1208 in FIG. 20 is lower than 2.0V.

22B is a diagram showing a timing relationship between DT and CK when the power supply voltage of FFn1208 of FIG. 20 is higher than 2.0V.

23A is a diagram showing an operation timing of the FF chain 1202 of FIG. 20 when the power supply voltage VDD is 1.8V.

23B is a diagram showing an operation timing of the FF chain 1202 in FIG. 20 when the power supply voltage VDD is 2.2V.

[Explanation of symbols]

101, 402, 602, 802, 1002 Scan test circuit 102 Flip-flop (FF) chain 103 of scan test circuit 101 Combination circuit 111, 401, 601, 801, 1001 Semiconductor integrated circuit device 112 LSI tester 201, 403-406, 603 ~ 606, 804-8
07 power supply voltage switching circuit 407 VDD1 power supply line 408 VDD2 power supply line 409, 609, 810 delay element 607 VDDI power supply line 608 for internal logic circuit VDDIO power supply line 803 for input / output circuit built-in self test (BIST) circuit 1003 to 1006 power supply Voltage drop circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA05 AB06 AK07 AK15 AL12                 5B048 AA20 AA23 CC18 EE02 FF02                 5F038 BB01 BE09 DF01 DT06 DT07                       DT09 DT15 EZ20                 5J056 AA03 BB60 CC00 CC04 CC05                       CC14 DD12 DD29 EE06 FF01                       FF07 FF08 GG08 GG13 KK01                       KK02 KK03

Claims (9)

[Claims] 1. A semiconductor integrated circuit device including a scan test circuit having a logic circuit and a flip-flop chain in which a plurality of flip-flops are connected in series to perform a scan test on the logic circuit, in the flip-flop chain. A method of analyzing whether or not a shift error has occurred, wherein a first power supply voltage at which the flip-flop chain normally shifts and a second power supply voltage at which the shift error operation occurs in the flip-flop chain are obtained in advance. And a power supply voltage is set to the second power supply voltage during a shift operation of the flip-flop to be analyzed in the flip-flop chain, and a power supply voltage is set to the first power supply voltage during a shift operation of a flip-flop other than the analysis target. Setting steps and power The voltage is switched between the first power supply voltage and the second power supply voltage to perform a shift operation test on all flip-flops included in the flip-flop chain, and a flip-flop having a defect in the shift operation. A method of analyzing a scan test circuit, comprising: 2. A test apparatus using the method for analyzing a scan test circuit according to claim 1, wherein the semiconductor integrated circuit device includes a power supply terminal to which the power supply voltage is supplied and input data for a scan test. An input data terminal to be supplied, a clock signal terminal to which a clock signal is commonly supplied to the plurality of flip-flops, an enable signal terminal to which an enable signal is commonly supplied to the plurality of flip-flops, and a plurality of flip-flops. An output data terminal to which shift data is output from the flip-flop at the final stage of the group, and generates the power supply voltage, the input data, the clock signal, and the enable signal to be supplied to the semiconductor integrated circuit device. , There is a problem in the shift operation based on the shift data from the output data terminal. Testing apparatus for a semiconductor integrated circuit, characterized in that to identify the flip flop. 3. A test apparatus using the method for analyzing a scan test circuit according to claim 1, wherein the semiconductor integrated circuit device includes a power supply terminal to which the power supply voltage is supplied and input data for scan test. An input data terminal to be supplied, a clock terminal to which a clock signal is commonly supplied to the plurality of flip-flops, an enable terminal to which an enable signal is commonly supplied to the plurality of flip-flops, and a plurality of flip-flops of the plurality of flip-flops. An output data terminal to which shift data from the final stage flip-flop is output, and the test device always supplies a power supply voltage to the power supply terminal of the semiconductor integrated circuit device during the shift operation of the flip-flop chain. And the first power supply voltage and the second
A power supply voltage switching circuit for switching the power supply voltage to the power supply terminal and controlling the power supply voltage switching circuit, and supplying the input data, the clock signal, and the enable signal to the semiconductor integrated circuit device. And a flip-flop having a defect in the shift operation is specified based on the shift data from the output data terminal. 4. A semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to claim 1 is applied, wherein the semiconductor integrated circuit device is a power supply terminal to which the first power supply voltage is supplied during normal operation. An input data terminal to which input data for a shift operation test is supplied; a clock terminal to which a clock signal is commonly supplied to the plurality of flip-flops; and an enable signal that is commonly supplied to the plurality of flip-flops. An enable terminal, an output data terminal to which shift data is output from a final stage flip-flop among the plurality of flip-flops, a first power supply line connected to the first power supply terminal, and the second power supply line. A second power supply line to which a power supply voltage is applied and one input terminal are connected to the first power supply line, and the other input terminal is connected to the first power supply line. A plurality of power supply voltage switching circuits that are connected to the power supply line and switch between the first power supply voltage and the second power supply voltage and supply the scan test circuit with control signals. And a control terminal for controlling the semiconductor integrated circuit device. 5. A semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to claim 1 is applied, wherein the semiconductor integrated circuit device is supplied with a power supply voltage for an input / output circuit during normal operation. 1
, A second power supply terminal to which the power supply voltage for the internal logic circuit is supplied during normal operation, an input data terminal to which the input data for the shift operation test is supplied, and a common terminal for the plurality of flip-flops. A clock terminal to which a clock signal is supplied, an enable terminal to which an enable signal is commonly supplied to the plurality of flip-flops, and output data from which shift data is output from a final stage flip-flop among the plurality of flip-flops. A terminal, a first power supply line connected to the first power supply terminal, a second power supply line connected to the second power supply terminal, and one input terminal connected to the first power supply line The other input terminal is connected to the second power supply line, and the power supply voltage for the input / output circuit and the power supply voltage for the internal logic circuit are switched. Serial scan test circuit a plurality of power supply voltage switching circuit for supplying a, and a control terminal to which a control signal is supplied to said plurality of power supply voltage switching circuit, when the shift operation of the analysis target of the flip-flop,
When the second power supply voltage obtained in advance is lower than the first power supply voltage, the plurality of power supply voltage switching circuits are used as the second power supply voltage for the internal logic circuit according to the control signal. When a power supply voltage is selected and the second power supply voltage obtained in advance is higher than the first power supply voltage, the second power supply voltage
2. A semiconductor integrated circuit device, wherein the power supply voltage for the input / output circuit is selected as the power supply voltage for the. 6. A semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to claim 1 is applied, wherein the semiconductor integrated circuit device is a power supply terminal to which the first power supply voltage is supplied during normal operation. A first power supply line connected to the first power supply terminal, a second power supply line to which the second power supply voltage is applied, and one input terminal connected to the first power supply line. , The other input terminal is connected to the second power supply line, a plurality of power supply voltage switching circuits for switching between the first power supply voltage and the second power supply voltage and supplying the scan test circuit, and the scan test. A test signal generation circuit that supplies scan test input data and a clock signal to the circuit, and a signal that indicates the number of repetitions of the shift operation test of the flip-flop chain. A test signal counting circuit for outputting to the outside of the integrated circuit, and a control signal for supplying the plurality of power supply voltage switching circuits with a control signal for switching the power supply voltage during the shift operation of the flip-flop to be analyzed according to the number of repetitions. A generation circuit, and an expected value comparison circuit for comparing the timing of the shift data output from the scan test circuit with the timing of the expected value signal and outputting the comparison result to the outside of the semiconductor integrated circuit, A semiconductor integrated circuit device, wherein a flip-flop having a defect in a shift operation is specified based on output signals from a counting circuit and the expected value comparison circuit. 7. A semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to claim 1 is applied, wherein the semiconductor integrated circuit device is supplied with a power supply voltage for an input / output circuit during normal operation. 1
Power supply terminal, a second power supply terminal to which a power supply voltage for an internal logic circuit is supplied during normal operation, a first power supply line connected to the first power supply terminal, and a second power supply terminal A second power supply line connected to the first power supply line, one input terminal connected to the first power supply line, the other input terminal connected to the second power supply line, the power supply voltage for the input / output circuit and the A plurality of power supply voltage switching circuits for switching the power supply voltage for the internal logic circuit to supply to the scan test circuit; a test signal generation circuit for supplying scan test input data and a clock signal to the scan test circuit; To a plurality of power supply voltage switching circuits, and a test number counting circuit for outputting a signal indicating the number of repetitions of the shift operation test of the chain to the outside of the semiconductor integrated circuit. A control signal generation circuit that supplies a control signal for switching a power supply voltage during a shift operation of a flip-flop to be analyzed according to the number of repetitions; and a timing of shift data output from the scan test circuit with an expected value signal. An expected value comparison circuit that compares the timing and outputs the comparison result to the outside of the semiconductor integrated circuit is provided, and during the shift operation of the analysis target flip-flop,
When the second power supply voltage obtained in advance is lower than the first power supply voltage, the plurality of power supply voltage switching circuits are used as the second power supply voltage for the internal logic circuit according to the control signal. When a power supply voltage is selected and the second power supply voltage obtained in advance is higher than the first power supply voltage, the second power supply voltage
The power supply voltage for the input / output circuit is selected as the power supply voltage for the flip-flop, and the flip-flop in which the shift operation is defective is identified based on the output signals from the test number counting circuit and the expected value comparison circuit. A semiconductor integrated circuit device characterized by the above. 8. The semiconductor integrated circuit device comprises a delay element that delays and supplies the control signal to at least one of the plurality of power supply voltage switching circuits. The semiconductor integrated circuit device according to claim 1. 9. A semiconductor integrated circuit device to which the method for analyzing a scan test circuit according to claim 1 is applied, wherein the semiconductor integrated circuit device includes a power supply terminal to which a power supply voltage is externally supplied, and the power supply terminal. A power supply line connected to the power supply line, a plurality of power supply voltage drop circuits connected to the power supply line, which lowers the power supply voltage in the scan test circuit below the power supply voltage during normal operation based on a control signal; With a control terminal to which a control signal for the power supply voltage drop circuit is supplied, during the shift operation of the flip-flop to be analyzed,
When the second power supply voltage obtained in advance is lower than the first power supply voltage, the plurality of power supply voltage dropping circuits sets the second power supply voltage as the second power supply voltage according to the control signal, and When the power supply voltage is lower than the power supply voltage and the second power supply voltage obtained in advance is higher than the first power supply voltage, the power supply voltage for the normal operation is set as the second power supply voltage. A characteristic semiconductor integrated circuit device.