JP2003309288A - Light-emitting element - Google Patents

Light-emitting element

Info

Publication number
JP2003309288A
JP2003309288A JP2002112989A JP2002112989A JP2003309288A JP 2003309288 A JP2003309288 A JP 2003309288A JP 2002112989 A JP2002112989 A JP 2002112989A JP 2002112989 A JP2002112989 A JP 2002112989A JP 2003309288 A JP2003309288 A JP 2003309288A
Authority
JP
Japan
Prior art keywords
layer
light emitting
light
side electrode
emitting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002112989A
Other languages
Japanese (ja)
Inventor
Shuichi Shinagawa
修一 品川
Hidenori Kamei
英徳 亀井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002112989A priority Critical patent/JP2003309288A/en
Publication of JP2003309288A publication Critical patent/JP2003309288A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting element which can raise intensity. <P>SOLUTION: The light-emitting element comprises: an n-type layer 3; a light emitting layer 4; and a p-type layer sequentially laminated on a substrate 1; a Pt layer 61 and an Rh layer 62 laminated on the layer 5. In this element, the film thickness of the Pt layer 61 is set to 1 to 5 nm. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子機器、ディス
プレー、照明、バックライトなどに用いられる発光素子
(LED、LD)に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device (LED, LD) used in electronic devices, displays, lighting, backlights and the like.

【0002】[0002]

【従来の技術】図2は従来の発光素子を示す側面図であ
る。
2. Description of the Related Art FIG. 2 is a side view showing a conventional light emitting device.

【0003】図2において、11は基板で、基板11は
透明或いは半透明となるように構成されている。12は
基板上に設けられたn型層、13はn層12の上に設け
られた発光層、14は発光層13の上に設けられたp型
層、15はp層14の上に設けられたp側電極で、p側
電極15は、Pt層16、Rh層17、Au層18をp
型層14側から順に積層して構成されている。19はn
層12に電気的に接続されたn側電極で、n側電極19
はn型層側からTi層20とAu層21を順に積層して
構成される。
In FIG. 2, 11 is a substrate, and the substrate 11 is configured to be transparent or semi-transparent. 12 is an n-type layer provided on the substrate, 13 is a light-emitting layer provided on the n-layer 12, 14 is a p-type layer provided on the light-emitting layer 13, and 15 is provided on the p-layer 14. The p-side electrode 15 includes a Pt layer 16, a Rh layer 17, and an Au layer 18.
The mold layers 14 are sequentially laminated from the mold layer 14 side. 19 is n
An n-side electrode electrically connected to the layer 12, the n-side electrode 19
Is formed by sequentially stacking a Ti layer 20 and an Au layer 21 from the n-type layer side.

【0004】この様に構成された発光素子は、回路基板
や載置部材などの実装基板22上に設けられた電極パタ
ーン23、24にそれぞれp側電極15及びn側電極1
9を半田等の接合材で面実装している。そして、発光層
13で放出された光の内、基板11側に放出された光は
そのまま外方へ放出され、p側電極15側に放出された
光は、p側電極15のRh層17等によって基板11側
に反射されることで、輝度を向上させていた。
In the light emitting element thus constructed, the p-side electrode 15 and the n-side electrode 1 are formed on the electrode patterns 23 and 24 provided on the mounting substrate 22 such as a circuit board and a mounting member, respectively.
9 is surface-mounted with a bonding material such as solder. Of the light emitted from the light emitting layer 13, the light emitted to the substrate 11 side is directly emitted to the outside, and the light emitted to the p-side electrode 15 side is the Rh layer 17 of the p-side electrode 15 and the like. By being reflected by the substrate 11 side, the brightness was improved.

【0005】先行例としては、特開平11−22016
8号公報等が挙げられる。
As a prior art example, Japanese Patent Laid-Open No. 11-22016
No. 8 publication and the like are listed.

【0006】[0006]

【発明が解決しようとする課題】しかしながら前記従来
の構成では、更に同じ駆動電圧で輝度を高めようとして
も、なかなか輝度を高くすることができなかった。
However, in the above-mentioned conventional structure, it is difficult to increase the brightness even if the same drive voltage is used to increase the brightness.

【0007】本発明は、上記の課題を解決するもので、
輝度を高めることができる発光素子に関するものであ
る。
The present invention solves the above-mentioned problems.
The present invention relates to a light emitting device capable of increasing brightness.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、光を透過可能な基板と、基板上に設け
られたn層及びp層と、n層と前記p層の間に設けられ
た発光層と、n層と前記p層にそれぞれ設けられたn側
電極とp側電極を有した発光素子であって、p側電極を
少なくともp層側からPt層、Rh層順に積層した構成
とするとともに、Pt層の膜厚を1nm〜5nmとし
た。
In order to achieve the above object, the present invention provides a substrate capable of transmitting light, an n layer and ap layer provided on the substrate, and an n layer and a p layer. What is claimed is: 1. A light-emitting device having a light-emitting layer provided between them, and an n-side electrode and a p-side electrode provided in the n-layer and the p-layer, respectively, wherein the p-side electrode is a Pt layer and a Rh layer at least from the p layer side. The Pt layer had a thickness of 1 nm to 5 nm while being laminated in this order.

【0009】[0009]

【発明の実施の形態】請求項1記載の発明は、光を透過
可能な基板と、前記基板上に設けられたn層及びp層
と、前記n層と前記p層の間に設けられた発光層と、前
記n層と前記p層にそれぞれ設けられたn側電極とp側
電極を有した発光素子であって、p側電極を少なくとも
p層側からPt層、Rh層順に積層した構成とするとと
もに、前記Pt層の膜厚を1nm〜5nmとしたことを
特徴とする発光素子とすることで、Pt層に入射してき
た光をPt層自体で吸収されるのを抑えることができ、
しかもRh層で十分に反射させることができるので、電
極構造の改良のみで輝度を向上させることができ、しか
もp側電極とp層との電気的接続は十分良好に行えるの
で、駆動電圧などを高くしなくても良い。
DETAILED DESCRIPTION OF THE INVENTION The invention according to claim 1 is characterized in that a substrate capable of transmitting light, an n layer and ap layer provided on the substrate, and an n layer and ap layer are provided. A light emitting device having a light emitting layer, and an n-side electrode and a p-side electrode provided in the n-layer and the p-layer, respectively, wherein the p-side electrode is laminated at least from the p-layer side in the order of Pt layer and Rh layer. In addition, the light-emitting element is characterized in that the Pt layer has a film thickness of 1 nm to 5 nm, whereby it is possible to prevent light incident on the Pt layer from being absorbed by the Pt layer itself.
Moreover, since the Rh layer can be sufficiently reflected, the brightness can be improved only by improving the electrode structure, and the p-side electrode and the p layer can be sufficiently electrically connected to each other, so that the driving voltage can be reduced. It doesn't have to be high.

【0010】請求項2記載の発明は、n層、p層、発光
層を少なくともGaとNを含む半導体層で構成したこと
を特徴とする請求項1記載の発光素子とすることで、緑
色、青色、紫色等の短波長の光を放出させることができ
る。
According to a second aspect of the present invention, the n layer, the p layer, and the light emitting layer are composed of a semiconductor layer containing at least Ga and N. It is possible to emit light of a short wavelength such as blue or violet.

【0011】請求項3記載の発明は、n層にp層が設け
られる第1の面と、前記第1の面と同一方向を向いた前
記第1の面よりも段落ちした第2の面とを備え、前記第
2の面にn側電極を設けたことを特徴とする請求項1記
載の発光素子とすることで、同一面方向において、p側
電極とn側電極の電気的接合を行うことができ、面実装
可能な発光素子を得ることができる。
According to a third aspect of the present invention, the first surface on which the p layer is provided in the n layer and the second surface which is stepped down from the first surface and is oriented in the same direction as the first surface. And the n-side electrode is provided on the second surface, whereby the p-side electrode and the n-side electrode are electrically connected in the same plane direction. It is possible to obtain a surface-mountable light emitting device.

【0012】請求項4記載の発明は、光を透過可能なn
型導電性基板と、前記n型導電性基板上に設けられたp
層と、前記n型導電性基板と前記p層の間に設けられた
発光層と、前記n型導電性基板と前記p層にそれぞれ設
けられたn側電極とp側電極を有した発光素子であっ
て、p側電極を少なくともp層側からPt層、Rh層順
に積層した構成とするとともに、前記Pt層の膜厚を1
nm〜5nmとしたことを特徴とする発光素子とするこ
とで、Pt層に入射してきた光をPt層自体で吸収され
るのを抑えることができ、しかもRh層で十分に反射さ
せることができるので、電極構造の改良のみで輝度を向
上させることができ、しかもp側電極とp層との電気的
接続は十分良好に行えるので、駆動電圧などを高くしな
くても良い。更に駆動電圧が低い素子を作製でき、低消
費電力の素子を得ることができる。
According to a fourth aspect of the present invention, n which can transmit light is used.
-Type conductive substrate and p provided on the n-type conductive substrate
Layer, a light emitting layer provided between the n-type conductive substrate and the p layer, and a light emitting device having an n-side electrode and a p-side electrode provided on the n-type conductive substrate and the p layer, respectively. In addition, the p-side electrode is laminated at least from the p-layer side in the order of Pt layer and Rh layer, and the thickness of the Pt layer is 1
By adopting a light emitting element characterized by having a thickness of 5 nm to 5 nm, it is possible to prevent light incident on the Pt layer from being absorbed by the Pt layer itself, and moreover, it is possible to sufficiently reflect the light on the Rh layer. Therefore, the brightness can be improved only by improving the electrode structure, and the electric connection between the p-side electrode and the p-layer can be sufficiently performed. Therefore, it is not necessary to increase the driving voltage. Further, an element with low driving voltage can be manufactured, and an element with low power consumption can be obtained.

【0013】請求項5記載の発明は、n型導電性基板、
p層、発光層を少なくともGaとNを含む半導体層で構
成したことを特徴とする請求項4記載の発光素子とする
ことで、緑色、青色、紫色等の短波長の光を放出させる
ことができる。
The invention according to claim 5 is an n-type conductive substrate,
5. The light emitting device according to claim 4, wherein the p layer and the light emitting layer are composed of a semiconductor layer containing at least Ga and N, and emit light having a short wavelength such as green, blue, and violet. it can.

【0014】請求項6記載の発明は、n型導電性基板に
p層が設けられる第1の面と、前記第1の面と同一方向
を向いた前記第1の面よりも段落ちした第2の面とを備
え、前記第2の面にn側電極を設けたことを特徴とする
請求項4記載の発光素子とすることで、同一面方向にお
いて、p側電極とn側電極の電気的接合を行うことがで
き、面実装可能な発光素子を得ることができる。
According to a sixth aspect of the present invention, the first surface on which the p layer is provided on the n-type conductive substrate and the first surface which is oriented in the same direction as the first surface are stepped down. 5. The light emitting device according to claim 4, further comprising a second surface, wherein an n-side electrode is provided on the second surface. It is possible to obtain a light-emitting element that can be surface-mounted and can be mechanically joined.

【0015】請求項7記載の発明は、Rh層の厚さを5
nm〜2000nmとした請求項1〜6いずれか1記載
の発光素子とすることで、所望の反射特性を得ることが
でき、しかも生産性を向上させることができる。
According to a seventh aspect of the invention, the Rh layer has a thickness of 5
By using the light emitting device according to any one of claims 1 to 6 having a thickness of nm to 2000 nm, desired reflection characteristics can be obtained and productivity can be improved.

【0016】請求項8記載の発明は、n型導電部とp型
導電部の間に発光部を設け、前記p型導電部に電気的に
接続されたp側電極を備えた発光素子であって、p側電
極を少なくともp型導電部側からPt層、Rh層順に積
層した構成とするとともに、前記Pt層の膜厚を1nm
〜5nmとしたことを特徴とする発光素子とすること
で、Pt層に入射してきた光をPt層自体で吸収される
のを抑えることができ、しかもRh層で十分に反射させ
ることができるので、電極構造の改良のみで輝度を向上
させることができ、しかもp側電極とp層との電気的接
続は十分良好に行えるので、駆動電圧などを高くしなく
ても良い。
The invention according to claim 8 is a light emitting device comprising a light emitting portion provided between an n-type conductive portion and a p-type conductive portion, and a p-side electrode electrically connected to the p-type conductive portion. And the p-side electrode is laminated at least from the p-type conductive portion side in this order to the Pt layer and the Rh layer, and the thickness of the Pt layer is 1 nm.
By using a light emitting device characterized by having a thickness of ˜5 nm, it is possible to prevent light incident on the Pt layer from being absorbed by the Pt layer itself, and moreover, it is possible to sufficiently reflect the light on the Rh layer. The brightness can be improved only by improving the electrode structure, and the electrical connection between the p-side electrode and the p layer can be sufficiently performed. Therefore, it is not necessary to increase the driving voltage.

【0017】請求項9記載の発明は、実装部材に電極パ
ターンが設けられ、前記実装部材の電極パターンに請求
項1〜8いずれか1記載の発光素子を面実装にて実装し
たことを特徴とする発光素子の実装構造とすることで、
輝度の高いLED等を容易に作製できる。
According to a ninth aspect of the present invention, an electrode pattern is provided on the mounting member, and the light emitting device according to any one of the first to eighth aspects is surface-mounted on the electrode pattern of the mounting member. By adopting the mounting structure of the light emitting element,
A high-brightness LED or the like can be easily manufactured.

【0018】図1は本発明の一実施の形態における発光
素子を示す側面図である。
FIG. 1 is a side view showing a light emitting device according to an embodiment of the present invention.

【0019】図1において、基板1としては少なくとも
光が通過可能な程度の透明度を有するものが用いられ
る。基板1の構成材料としては、サファイア基板、Si
C基板、GaN基板などが用いられる。
In FIG. 1, as the substrate 1, a substrate having a transparency that allows at least light to pass therethrough is used. As a constituent material of the substrate 1, a sapphire substrate, Si
A C substrate, a GaN substrate or the like is used.

【0020】3は基板1の上に直接あるいは図示してい
ないがバッファ層を介して設けられたn型層で、n型層
3は少なくともGaとNを含んだ半導体層で構成され、
しかもn型ドーパントとしては、Si又はGe等が好適
に用いられる。このn型層3は膜厚4μmで構成されて
いる。
Reference numeral 3 denotes an n-type layer provided directly on the substrate 1 or via a buffer layer (not shown). The n-type layer 3 is composed of a semiconductor layer containing at least Ga and N.
Moreover, Si, Ge, or the like is preferably used as the n-type dopant. The n-type layer 3 has a film thickness of 4 μm.

【0021】4はn型層3の上に設けられた発光層で、
発光層4はn型層3の上に直接或いは少なくともGaと
Nを含む半導体層を介して積層されている。発光層4は
少なくともGa、Nを含み、所望の発光波長を得る為に
必要な場合は適量のInを含む半導体からなる。また、
発光層4としては、図1においては1層構造としている
が、例えば、InGaN層とGaN層を交互に少なくと
も一対積層した多量子井戸構造とすることで、更に輝度
を向上させることができる。
Reference numeral 4 denotes a light emitting layer provided on the n-type layer 3,
The light emitting layer 4 is laminated directly on the n-type layer 3 or via a semiconductor layer containing at least Ga and N. The light emitting layer 4 is made of a semiconductor containing at least Ga and N, and a suitable amount of In when necessary to obtain a desired emission wavelength. Also,
Although the light emitting layer 4 has a single-layer structure in FIG. 1, for example, a multi-quantum well structure in which at least one pair of InGaN layers and GaN layers are alternately laminated is used to further improve the brightness.

【0022】5は発光層4の上に直接或いは少なくとも
GaとNを含んだ半導体層を介して積層されたp型層
で、p型層5は少なくともGaとNを含んだ半導体層で
構成され、しかもp型ドーパントとしては、Mg等が好
適に用いられる。このp型層5は膜厚0.2μmで構成
されている。
Reference numeral 5 denotes a p-type layer laminated directly on the light emitting layer 4 or via a semiconductor layer containing at least Ga and N. The p-type layer 5 is composed of a semiconductor layer containing at least Ga and N. Moreover, Mg or the like is preferably used as the p-type dopant. The p-type layer 5 has a film thickness of 0.2 μm.

【0023】6はp型層5の上に設けられたp側電極
で、p側電極6はp型層5側からPt層61、Rh層6
2、Au層63を順に積層して構成されている。
Reference numeral 6 denotes a p-side electrode provided on the p-type layer 5, and the p-side electrode 6 is a Pt layer 61 and a Rh layer 6 from the p-type layer 5 side.
2 and Au layer 63 are laminated in this order.

【0024】本発明の特徴の一つは、Pt層61の膜厚
を1nm〜5nmとしたことを特徴とする。すなわち、
Pt層61はp型層5と良好な電気的接続を得るために
1nm以上の膜厚で構成されており、Pt層61が5n
mより厚いと、Pt層61自体での光の吸収が大きくな
ってしまい、輝度が低下する。
One of the features of the present invention is that the thickness of the Pt layer 61 is set to 1 nm to 5 nm. That is,
The Pt layer 61 has a film thickness of 1 nm or more in order to obtain good electrical connection with the p-type layer 5, and the Pt layer 61 has a thickness of 5 n.
If it is thicker than m, the absorption of light by the Pt layer 61 itself becomes large, and the brightness is lowered.

【0025】また、本発明の特徴の一つは、Rh層62
の厚さを5nm〜2000nmとすることを特徴とす
る。すなわち、Rh層62の膜厚が5nmより薄いと十
分な反射特性を得ることはできず、逆に2000nmよ
り厚いと、反射特性に変化は無く、膜の形成に必要とな
る蒸発原料が多く必要となり、又この工程にかかる時間
が長くなる為、製造コストが高くなってしまう。
Further, one of the features of the present invention is that the Rh layer 62
The thickness is set to 5 nm to 2000 nm. That is, when the film thickness of the Rh layer 62 is thinner than 5 nm, sufficient reflection characteristics cannot be obtained, and when it is thicker than 2000 nm, the reflection characteristics do not change and a large amount of evaporation raw material required for film formation is required. In addition, since the time required for this process becomes long, the manufacturing cost becomes high.

【0026】この様に、Pt層61の膜厚を1〜5nm
とすることで発光層から放射された光がPt層61に入
射してもPt層61自体における光吸収を抑えることが
でき輝度を向上させることができ、しかもRh層62で
の反射特性を十分に得ることができる。従来の技術で示
した先行例では、Pt層は5nm以上であるので光吸収
が多く発生し、輝度が低下する。
Thus, the film thickness of the Pt layer 61 is set to 1 to 5 nm.
Thus, even if the light emitted from the light emitting layer enters the Pt layer 61, the light absorption in the Pt layer 61 itself can be suppressed and the brightness can be improved, and the reflection characteristics of the Rh layer 62 are sufficient. Can be obtained. In the prior art example shown in the related art, since the Pt layer has a thickness of 5 nm or more, a large amount of light absorption occurs, and the brightness decreases.

【0027】本発明はこのPt層61自体の光吸収が輝
度向上に影響を与えることに着目し、オーミック接合の
度合いなどを考慮することで、Pt層61の膜厚を規定
し、その結果p側電極6の改良の改良のみで輝度を向上
させることができる。
In the present invention, attention is paid to the fact that the light absorption of the Pt layer 61 itself influences the improvement of brightness, and the thickness of the Pt layer 61 is defined by considering the degree of ohmic junction and the like, and as a result, p The brightness can be improved only by improving the side electrode 6.

【0028】なお、p側電極6はp型層5の全面或いは
p型層5の表出面積の80%以上設けることが好まし
い。
The p-side electrode 6 is preferably provided on the entire surface of the p-type layer 5 or 80% or more of the exposed area of the p-type layer 5.

【0029】7はp型層5を設けた側に表出したn型層
3の一部に設けられたn側電極で、n側電極7はn型層
3側からTi層71、Au層72を順に積層して構成さ
れている。
Reference numeral 7 denotes an n-side electrode provided on a part of the n-type layer 3 exposed on the side where the p-type layer 5 is provided. The n-side electrode 7 is a Ti layer 71, an Au layer from the n-type layer 3 side. 72 are laminated in order.

【0030】8は上述の様に構成された発光素子が実装
される実装部材で、実装部材8としては、回路基板や載
置部材などが好適に用いられる。実装部材8上には少な
くとも電極パターン9、10が設けられており、この電
極パターン9、10には例えばそれぞれAu層63及び
Au層72が半田や鉛フリー半田等の導電性接合材にて
電気的に接合されている。
Reference numeral 8 denotes a mounting member on which the light emitting element configured as described above is mounted. As the mounting member 8, a circuit board or a mounting member is preferably used. At least electrode patterns 9 and 10 are provided on the mounting member 8. For example, the Au layer 63 and the Au layer 72 are electrically connected to the electrode patterns 9 and 10 by a conductive bonding material such as solder or lead-free solder. Are joined together.

【0031】以上の様に構成された発光素子は、発光層
4で放出された光がPt層61に入射してもPt層61
の厚みを5nm以下としていることでPt層61自体で
の光吸収を抑えることができ、しかも膜厚を1nm以上
とすることで、十分なp型層5との電気的接合を得るこ
とができる。
In the light emitting element having the above-described structure, even if the light emitted from the light emitting layer 4 enters the Pt layer 61, the Pt layer 61
By setting the thickness to 5 nm or less, it is possible to suppress light absorption in the Pt layer 61 itself, and by setting the thickness to 1 nm or more, sufficient electric connection with the p-type layer 5 can be obtained. .

【0032】従って、発光層4からp側電極6側に放出
された光は効率よく反射されて基板1から放出されるの
で、p側電極6の改良のみで、十分な輝度向上を実現で
きる。
Therefore, since the light emitted from the light emitting layer 4 to the p-side electrode 6 side is efficiently reflected and emitted from the substrate 1, sufficient improvement in luminance can be realized only by improving the p-side electrode 6.

【0033】なお、本実施の形態では、Pt層、Rh
層、Au層、Ti層等は各材料単体で構成される場合も
もちろんその元素を主成分とする層でも良い。すなわ
ち、例えばPt層であれば、Ptに特性に影響を与えな
い範囲で所定の元素が混入した材料でも良い。
In the present embodiment, the Pt layer, Rh
The layers, Au layers, Ti layers and the like may be composed of each material alone or may be layers containing the element as a main component. That is, for example, in the case of a Pt layer, a material in which a predetermined element is mixed with Pt in a range that does not affect the characteristics may be used.

【0034】[0034]

【実施例】本発明の実施例として、図3に示す窒化ガリ
ウム系化合物半導体発光素子の作製方法を記す。以下の
実施例においては、窒化ガリウム系化合物半導体の成長
方法として有機金属気相成長法を用いたものを示すが、
成長方法はこれに限定されるものではなく、分子線エピ
タキシー法や有機金属分子線エピタキシー法等を用いる
ことも可能である。
EXAMPLE As a practical example of the present invention, a method for manufacturing the gallium nitride-based compound semiconductor light emitting device shown in FIG. 3 will be described. In the following examples, a metalorganic vapor phase epitaxy method is used as a method for growing a gallium nitride-based compound semiconductor,
The growth method is not limited to this, and a molecular beam epitaxy method, an organometallic molecular beam epitaxy method, or the like can be used.

【0035】(実施例1)先ず、表面を鏡面に仕上げら
れたサファイアの基板1を反応管内の基板ホルダーに載
置した後、基板1の温度を1000℃に保ち、窒素と水
素を流しながら基板1を10分間加熱することにより、
基板1の表面に付着している有機物等の汚れや水分を取
り除いた。
Example 1 First, a sapphire substrate 1 having a mirror-finished surface was placed on a substrate holder in a reaction tube, and then the temperature of the substrate 1 was kept at 1000 ° C. while flowing nitrogen and hydrogen. By heating 1 for 10 minutes,
Dirt and water such as organic substances adhering to the surface of the substrate 1 were removed.

【0036】次に、基板1の温度を550℃にまで降下
させ、キャリアガスとして窒素を流しながら、アンモニ
アとTMGを供給して、GaNからなるバッファ層2を
25nmの厚さで成長させた。
Next, the temperature of the substrate 1 was lowered to 550 ° C., while supplying nitrogen as a carrier gas, ammonia and TMG were supplied to grow a buffer layer 2 made of GaN with a thickness of 25 nm.

【0037】次に、TMGの供給を止めて1050℃ま
で昇温させた後、キャリアガスとして窒素と水素を流し
ながら、アンモニア、TMGそしてSiH4を供給し
て、SiをドープしたGaNからなるn型層3を4μm
の厚さで成長させた。
Next, after the supply of TMG is stopped and the temperature is raised to 1050 ° C., while supplying nitrogen and hydrogen as a carrier gas, ammonia, TMG and SiH 4 are supplied to form n-doped GaN. Mold layer 3 is 4 μm
Grown to a thickness of.

【0038】n型層3を成長後、TMGとSiH4の供
給を止め、基板温度を750℃にまで降下させ、750
℃において、キャリアガスとして窒素を流しながら、ア
ンモニア、TMG、TMIを供給して、アンドープのI
nGaNからなる単一量子井戸構造の発光層4を2nm
の厚さで成長させた。
After growing the n-type layer 3, the supply of TMG and SiH 4 is stopped and the substrate temperature is lowered to 750 ° C.
At a temperature of ° C, while supplying nitrogen as a carrier gas, ammonia, TMG, and TMI are supplied to supply undoped I
The light emitting layer 4 having a single quantum well structure made of nGaN has a thickness of 2 nm.
Grown to a thickness of.

【0039】発光層4を成長後、TMIの供給を止め、
TMGを流しながら基板温度を1050℃に向けて昇温
させながら、引き続きアンドープのGaN(図示せず)
を4nmの厚さで成長させ、基板温度が1050℃に達
したら、キャリアガスとして窒素と水素を流しながら、
アンモニア、TMG、TMA、Cp2Mgを供給して、
MgをドープさせたAlGaNからなるp型クラッド層
51を0.2μmの厚さで成長させた。
After growing the light emitting layer 4, the supply of TMI is stopped,
While flowing TMG and raising the substrate temperature toward 1050 ° C., undoped GaN (not shown) is continued.
Was grown to a thickness of 4 nm, and when the substrate temperature reached 1050 ° C., while flowing nitrogen and hydrogen as carrier gases,
Supply ammonia, TMG, TMA, Cp 2 Mg,
A p-type cladding layer 51 made of AlGaN doped with Mg was grown to a thickness of 0.2 μm.

【0040】p型クラッド層51を成長後、基板1の温
度を1050℃に保持したままで、キャリアガスとして
窒素ガス及び水素ガスを流しながら、アンモニア、TM
G、TMA、及びCp2Mgを供給して、Mgをドープ
したAlGaNからなるp型コンタクト層52を0.1
μmの厚さで成長させた。
After the p-type clad layer 51 is grown, ammonia and TM are fed while the substrate 1 is kept at 1050 ° C. while flowing nitrogen gas and hydrogen gas as carrier gases.
G, TMA, and Cp 2 Mg are supplied so that the p-type contact layer 52 made of Mg-doped AlGaN is 0.1.
It was grown to a thickness of μm.

【0041】p型コンタクト層52を成長後、TMGと
TMAとCp2Mgの供給を止め、窒素ガスとアンモニ
アを流しながら、基板1の温度を室温程度にまで冷却さ
せて、基板1の上に窒化ガリウム系化合物半導体が積層
されたウェハーを反応管から取り出した。
After the growth of the p-type contact layer 52, the supply of TMG, TMA and Cp 2 Mg is stopped, the temperature of the substrate 1 is cooled to about room temperature while flowing nitrogen gas and ammonia, and The wafer on which the gallium nitride compound semiconductor was laminated was taken out from the reaction tube.

【0042】このようにして形成した窒化ガリウム系化
合物半導体からなる積層構造に対して、別途アニールを
施すことなく、その表面上にCVD法によりSiO2
を堆積させた後、フォトリソグラフィとウェットエッチ
ングにより略方形状にパターンニングしてエッチング用
のSiO2マスクを形成させた。そして、反応性イオン
エッチング法により、p型コンタクト層52とp型クラ
ッド層51と中間層と発光層4とn型層3の一部を約
0.4μmの深さで積層方向と逆の方向に向かって除去
させて、n型層3の表面を露出させた。
With respect to the laminated structure made of the gallium nitride-based compound semiconductor thus formed, a SiO 2 film is deposited on the surface thereof by the CVD method without performing additional annealing, and then photolithography and wet etching are performed. To form a SiO 2 mask for etching. Then, a part of the p-type contact layer 52, the p-type clad layer 51, the intermediate layer, the light emitting layer 4, and the n-type layer 3 is formed at a depth of about 0.4 μm in a direction opposite to the laminating direction by the reactive ion etching method. To expose the surface of the n-type layer 3.

【0043】そして、エッチング用のSiO2マスクを
ウェットエッチングにより除去させた後、積層構造の表
面上にフォトレジストを塗布し、フォトリソグラフィー
によりp型コンタクト層52の表面上のフォトレジスト
のみを取り除き、p型コンタクト層52の表面の80%
以上を露出させた。そして、積層構造を真空蒸着装置の
チャンバー内に装着し、チャンバー内を2×10-6To
rr以下にまで真空排気した後、電子ビーム蒸着法によ
り露出されたp型コンタクト層52の表面上およびフォ
トレジスト上に、3nmの厚さのPt層61を蒸着し
た。続いて、100nmの厚さのRh層62を蒸着し、
更に1μmの厚さのAu層63を蒸着した。次に、積層
構造をチャンバーから取り出し、フォトレジスト上のP
t層61とRh層62とAu層63をフォトレジストと
共に除去することによって、p型コンタクト層52の表
面上にPt層61とRh層62とAu層63が順次積層
されたp側電極6を形成した。
After removing the SiO 2 mask for etching by wet etching, a photoresist is applied on the surface of the laminated structure, and only the photoresist on the surface of the p-type contact layer 52 is removed by photolithography. 80% of the surface of the p-type contact layer 52
The above is exposed. Then, the laminated structure is mounted in the chamber of the vacuum vapor deposition apparatus, and the inside of the chamber is set to 2 × 10 −6 To.
After evacuation to rr or less, a Pt layer 61 having a thickness of 3 nm was deposited on the surface of the p-type contact layer 52 and the photoresist exposed by the electron beam evaporation method. Subsequently, a Rh layer 62 having a thickness of 100 nm is deposited,
Further, an Au layer 63 having a thickness of 1 μm was deposited. Next, the laminated structure is taken out of the chamber, and P on the photoresist is removed.
By removing the t layer 61, the Rh layer 62, and the Au layer 63 together with the photoresist, the p-side electrode 6 in which the Pt layer 61, the Rh layer 62, and the Au layer 63 are sequentially laminated on the surface of the p-type contact layer 52 is formed. Formed.

【0044】再び積層構造の表面上にフォトレジストを
塗布し、フォトリソグラフィーにより、露出させたn型
層3の表面一部の上のフォトレジストのみを取り除き、
n型層3の表面一部を露出させた。そして、積層構造を
真空蒸着装置のチャンバー内に装着し、チャンバー内を
2×10-6Torr以下にまで真空排気した後、電子ビ
ーム蒸着法により、露出されたn型層3の表面上および
フォトレジスト上に、100nmの厚さのTi層71を
蒸着し、更に1.5μmの厚さのAu層72を蒸着し
た。次に、積層構造をチャンバーから取り出し、フォト
レジスト上のTi層71とAu層72をフォトレジスト
と共に除去することによって、n型層3の表面一部の上
にTi層71とAu層72が順次積層されたn側電極7
を形成した。
A photoresist is applied again on the surface of the laminated structure, and only the photoresist on the exposed part of the surface of the n-type layer 3 is removed by photolithography.
A part of the surface of the n-type layer 3 was exposed. Then, the laminated structure is mounted in a chamber of a vacuum vapor deposition apparatus, the chamber is evacuated to 2 × 10 −6 Torr or less, and then the exposed surface of the n-type layer 3 and the photo layer are exposed by an electron beam vapor deposition method. A Ti layer 71 having a thickness of 100 nm was vapor-deposited on the resist, and an Au layer 72 having a thickness of 1.5 μm was vapor-deposited. Next, the laminated structure is taken out of the chamber, and the Ti layer 71 and the Au layer 72 on the photoresist are removed together with the photoresist, so that the Ti layer 71 and the Au layer 72 are sequentially formed on a part of the surface of the n-type layer 3. Layered n-side electrode 7
Was formed.

【0045】この後、基板1の裏面を研磨して100μ
m程度の厚さに調整し、スクライブによりチップ状に分
離した。このようにして、図3に示す窒化ガリウム系化
合物半導体発光素子が得られた。
Thereafter, the back surface of the substrate 1 is polished to 100 μm.
The thickness was adjusted to about m and the chips were separated by scribing. Thus, the gallium nitride-based compound semiconductor light emitting device shown in FIG. 3 was obtained.

【0046】この発光素子を、電極形成面側を下向きに
して、正負一対の電極を有するSiダイオードの上にA
uバンプにより接着させた。このとき、発光素子のp側
電極6およびn側電極7が、それぞれSiダイオードの
負電極および正電極と接続されるようして発光素子を搭
載する。この後、発光素子を搭載させたSiダイオード
を、Agペーストによりステム上に載置し、Siダイオ
ードの正電極をステム上の電極にワイヤで結線し、その
後樹脂モールドして発光ダイオードを作製した。この発
光ダイオードを20mAの順方向電流で駆動したとこ
ろ、ピーク発光波長470nmの青色で発光し、基板1
の積層構造を形成した側の反対側の面から均一な面発光
が得られた。このときの順方向動作電圧は3.4Vであ
り、発光出力は5mWであった。
This light-emitting element was placed on a Si diode having a pair of positive and negative electrodes with the electrode formation surface side facing downward.
Bonded by u-bump. At this time, the light emitting element is mounted so that the p-side electrode 6 and the n-side electrode 7 of the light emitting element are connected to the negative electrode and the positive electrode of the Si diode, respectively. Then, the Si diode on which the light emitting element was mounted was placed on the stem with Ag paste, the positive electrode of the Si diode was connected to the electrode on the stem with a wire, and then resin-molded to produce a light emitting diode. When this light emitting diode was driven with a forward current of 20 mA, it emitted blue light with a peak emission wavelength of 470 nm, and the substrate 1
A uniform surface emission was obtained from the surface opposite to the side on which the laminated structure was formed. The forward operating voltage at this time was 3.4 V, and the light emission output was 5 mW.

【0047】(実施例2)実施例2においては、上記実
施例1において、Pt層61の厚みを6nmとした以外
は、上記実施例1と同様の手順で発光素子を作製した。
この発光素子を20mAの順方向電流で駆動したとこ
ろ、ピーク発光波長470nmの青色で発光し、ピーク
発光波長470nmの青色で発光し、基板1の積層構造
を形成した側の反対側の面から均一な面発光が得られた
が、このときの順方向動作電圧は3.4Vであり、発光
出力は4.2mWであった。
(Example 2) In Example 2, a light emitting device was manufactured in the same procedure as in Example 1 except that the thickness of the Pt layer 61 in Example 1 was changed to 6 nm.
When this light emitting device was driven with a forward current of 20 mA, it emitted blue light with a peak emission wavelength of 470 nm and emitted blue light with a peak emission wavelength of 470 nm, and was uniform from the surface opposite to the side where the laminated structure of the substrate 1 was formed. However, the forward operation voltage at this time was 3.4 V, and the light emission output was 4.2 mW.

【0048】以上の様に説明した、Pt層の膜厚と発光
素子の輝度の関係と、Pt層の膜厚と駆動電圧の関係に
ついて、図4,図5を用いて説明する。
The relationship between the film thickness of the Pt layer and the brightness of the light emitting element and the relationship between the film thickness of the Pt layer and the driving voltage, which have been described above, will be described with reference to FIGS. 4 and 5.

【0049】図4に示すように、Pt層の膜厚が5nm
よりも厚くなると、Pt層自体での光吸収量が著しく多
くなると思われる原因で、輝度が低下する。更に図5か
ら解るように、Pt層の膜厚が1nmよりも薄いとp層
とのオーミック接合が確実に行われていないことが原因
と思われる駆動電圧の上昇が見られる。
As shown in FIG. 4, the thickness of the Pt layer is 5 nm.
When the thickness is larger than this, the brightness is lowered because the amount of light absorption in the Pt layer itself seems to be remarkably increased. Further, as can be seen from FIG. 5, when the film thickness of the Pt layer is thinner than 1 nm, an increase in the driving voltage, which is considered to be due to the fact that the ohmic contact with the p layer is not reliably performed, is observed.

【0050】従って、電気的な特性或いは輝度の面から
Pt層は1nm〜5nmとすることが好ましいことがわ
かる。
Therefore, it is understood that the Pt layer preferably has a thickness of 1 nm to 5 nm in terms of electrical characteristics or brightness.

【0051】[0051]

【発明の効果】光を透過可能な基板と、基板上に設けら
れたn層及びp層と、n層と前記p層の間に設けられた
発光層と、n層と前記p層にそれぞれ設けられたn側電
極とp側電極を有した発光素子であって、p側電極を少
なくともp層側からPt層、Rh層順に積層した構成と
するとともに、Pt層の膜厚を1nm〜5nmとしたこ
とで、Pt層に入射してきた光をPt層自体で吸収され
るのを抑えることができ、しかもRh層で十分に反射さ
せることができるので、電極構造の改良のみで輝度を向
上させることができ、しかもp側電極とp層との電気的
接続は十分良好に行えるので、駆動電圧などを高くしな
くても良い。
The substrate capable of transmitting light, the n layer and the p layer provided on the substrate, the light emitting layer provided between the n layer and the p layer, and the n layer and the p layer, respectively. A light-emitting element having an n-side electrode and a p-side electrode provided, wherein the p-side electrode is laminated at least from the p-layer side in this order to the Pt layer and the Rh layer, and the thickness of the Pt layer is 1 nm to 5 nm. By doing so, it is possible to suppress the light incident on the Pt layer from being absorbed by the Pt layer itself, and moreover, it is possible to sufficiently reflect the light on the Rh layer, so that the brightness can be improved only by improving the electrode structure. Since the electric connection between the p-side electrode and the p-layer can be performed sufficiently well, it is not necessary to increase the driving voltage.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態における発光素子を示す
側面図
FIG. 1 is a side view showing a light emitting element according to an embodiment of the present invention.

【図2】従来の発光素子を示す側面図FIG. 2 is a side view showing a conventional light emitting device.

【図3】本発明の一実施の形態における発光素子を示す
側面図
FIG. 3 is a side view showing a light emitting element according to an embodiment of the present invention.

【図4】本発明の一実施の形態における発光素子のPt
層の膜厚と輝度との関係を示すグラフ
FIG. 4 shows Pt of a light emitting device according to an embodiment of the present invention.
Graph showing the relationship between layer thickness and brightness

【図5】本発明の一実施の形態における発光素子のPt
層の膜厚と駆動電圧との関係を示すグラフ
FIG. 5 is a light emitting element Pt according to an embodiment of the present invention.
Graph showing the relationship between the layer thickness and the drive voltage

【符号の説明】[Explanation of symbols]

1 基板 2 バッファ層 3 n層 4 発光層 5 p層 6 p側電極 7 n側電極 8 実装部材 9、10 電極パターン 51 p型クラッド層 52 p型コンタクト層 61 Pt層 62 Rh層 63 Au層 71 Ti層 72 Au層 1 substrate 2 buffer layers 3 n layers 4 Light emitting layer 5 p layer 6 p-side electrode 7 n-side electrode 8 mounting members 9, 10 electrode pattern 51 p-type clad layer 52 p-type contact layer 61 Pt layer 62 Rh layer 63 Au layer 71 Ti layer 72 Au layer

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F041 AA04 CA03 CA40 CA49 CA57 CA65 CA74 CA82 CA85 CA92 CB05 DA04 DA09 DA12 DA19 FF11 5F073 AA74 BA09 CA07 CB05 CB06 CB23 DA05 EA24    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F041 AA04 CA03 CA40 CA49 CA57                       CA65 CA74 CA82 CA85 CA92                       CB05 DA04 DA09 DA12 DA19                       FF11                 5F073 AA74 BA09 CA07 CB05 CB06                       CB23 DA05 EA24

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】光を透過可能な基板と、前記基板上に設け
られたn層及びp層と、前記n層と前記p層の間に設け
られた発光層と、前記n層と前記p層にそれぞれ設けら
れたn側電極とp側電極を有した発光素子であって、p
側電極を少なくともp層側からPt層、Rh層順に積層
した構成とするとともに、前記Pt層の膜厚を1nm〜
5nmとしたことを特徴とする発光素子。
1. A substrate capable of transmitting light, an n layer and ap layer provided on the substrate, a light emitting layer provided between the n layer and the p layer, the n layer and the p layer. A light emitting device having an n-side electrode and a p-side electrode provided in each layer,
The side electrodes are laminated at least from the p-layer side in this order to the Pt layer and the Rh layer, and the film thickness of the Pt layer is 1 nm to
A light emitting device having a thickness of 5 nm.
【請求項2】n層、p層、発光層を少なくともGaとN
を含む半導体層で構成したことを特徴とする請求項1記
載の発光素子。
2. The n layer, the p layer, and the light emitting layer are at least Ga and N.
The light emitting device according to claim 1, wherein the light emitting device comprises a semiconductor layer containing.
【請求項3】n層にp層が設けられる第1の面と、前記
第1の面と同一方向を向いた前記第1の面よりも段落ち
した第2の面とを備え、前記第2の面にn側電極を設け
たことを特徴とする請求項1記載の発光素子。
3. A first surface on which an n layer is provided with a p layer, and a second surface, which is stepped down from the first surface and is oriented in the same direction as the first surface, The light emitting device according to claim 1, wherein an n-side electrode is provided on the second surface.
【請求項4】光を透過可能なn型導電性基板と、前記n
型導電性基板上に設けられたp層と、前記n型導電性基
板と前記p層の間に設けられた発光層と、前記n型導電
性基板と前記p層にそれぞれ設けられたn側電極とp側
電極を有した発光素子であって、p側電極を少なくとも
p層側からPt層、Rh層順に積層した構成とするとと
もに、前記Pt層の膜厚を1nm〜5nmとしたことを
特徴とする発光素子。
4. An n-type conductive substrate capable of transmitting light;
P layer provided on the type conductive substrate, a light emitting layer provided between the n type conductive substrate and the p layer, and n side provided on the n type conductive substrate and the p layer, respectively. A light-emitting element having an electrode and a p-side electrode, wherein the p-side electrode is laminated at least from the p-layer side in the order of Pt layer and Rh layer, and the Pt layer has a thickness of 1 nm to 5 nm. Characteristic light emitting element.
【請求項5】n型導電性基板、p層、発光層を少なくと
もGaとNを含む半導体層で構成したことを特徴とする
請求項4記載の発光素子。
5. The light emitting device according to claim 4, wherein the n-type conductive substrate, the p layer, and the light emitting layer are composed of a semiconductor layer containing at least Ga and N.
【請求項6】n型導電性基板にp層が設けられる第1の
面と、前記第1の面と同一方向を向いた前記第1の面よ
りも段落ちした第2の面とを備え、前記第2の面にn側
電極を設けたことを特徴とする請求項4記載の発光素
子。
6. An n-type conductive substrate is provided with a first surface on which a p layer is provided, and a second surface which is oriented in the same direction as the first surface and which is stepped down from the first surface. The light emitting device according to claim 4, wherein an n-side electrode is provided on the second surface.
【請求項7】Rh層の厚さを5nm〜2000nmとし
た請求項1〜6いずれか1記載の発光素子。
7. The light emitting device according to claim 1, wherein the Rh layer has a thickness of 5 nm to 2000 nm.
【請求項8】n型導電部とp型導電部の間に発光部を設
け、前記p型導電部に電気的に接続されたp側電極を備
えた発光素子であって、p側電極を少なくともp型導電
部側からPt層、Rh層順に積層した構成とするととも
に、前記Pt層の膜厚を1nm〜5nmとしたことを特
徴とする発光素子。
8. A light-emitting device comprising a p-side electrode electrically connected to the p-type conductive part, wherein a light-emitting part is provided between the n-type conductive part and the p-type conductive part. A light-emitting device having a structure in which at least a Pt layer and a Rh layer are stacked in this order from the p-type conductive portion side, and the Pt layer has a film thickness of 1 nm to 5 nm.
【請求項9】実装部材に電極パターンが設けられ、前記
実装部材の電極パターンに請求項1〜8いずれか1記載
の発光素子を面実装にて実装したことを特徴とする発光
素子の実装構造。
9. A mounting structure of a light emitting element, wherein an electrode pattern is provided on a mounting member, and the light emitting element according to claim 1 is surface-mounted on the electrode pattern of the mounting member. .
JP2002112989A 2002-04-16 2002-04-16 Light-emitting element Pending JP2003309288A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002112989A JP2003309288A (en) 2002-04-16 2002-04-16 Light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002112989A JP2003309288A (en) 2002-04-16 2002-04-16 Light-emitting element

Publications (1)

Publication Number Publication Date
JP2003309288A true JP2003309288A (en) 2003-10-31

Family

ID=29395299

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002112989A Pending JP2003309288A (en) 2002-04-16 2002-04-16 Light-emitting element

Country Status (1)

Country Link
JP (1) JP2003309288A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197670A (en) * 2003-12-10 2005-07-21 Showa Denko Kk Gallium nitride base compound semiconductor light emitting element and its negative electrode
JP2005303287A (en) * 2004-03-18 2005-10-27 Showa Denko Kk Group iii nitride semiconductor light emitting element, its manufacturing method, and led lamp
JP2005303285A (en) * 2004-03-18 2005-10-27 Showa Denko Kk Group iii nitride semiconductor light emitting element, its manufacturing method, and led lamp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197670A (en) * 2003-12-10 2005-07-21 Showa Denko Kk Gallium nitride base compound semiconductor light emitting element and its negative electrode
JP2005303287A (en) * 2004-03-18 2005-10-27 Showa Denko Kk Group iii nitride semiconductor light emitting element, its manufacturing method, and led lamp
JP2005303285A (en) * 2004-03-18 2005-10-27 Showa Denko Kk Group iii nitride semiconductor light emitting element, its manufacturing method, and led lamp

Similar Documents

Publication Publication Date Title
JP4091261B2 (en) Semiconductor light emitting device and manufacturing method thereof
JP2007234648A (en) Method of manufacturing nitride semiconductor light-emitting element
JP5047508B2 (en) Manufacturing method of nitride semiconductor light emitting device
WO2014167773A1 (en) Semiconductor light emitting element and method for manufacturing same
WO2011102450A1 (en) Method of manufacture for a compound semiconductor light-emitting element
JP2012129281A (en) Light-emitting device
JP2004063732A (en) Light-emitting element
JP3341576B2 (en) Group III nitride compound semiconductor light emitting device
JP3336855B2 (en) Group III nitride compound semiconductor light emitting device
TWI585993B (en) Nitride light emitting device and manufacturing method thereof
JPH11177135A (en) Gallium nitride semiconductor element and its manufacture
JP3589000B2 (en) Gallium nitride based compound semiconductor light emitting device
JP2012084667A (en) Compound semiconductor light-emitting element, method of manufacturing the same, lamp, electronic device, and mechanical apparatus
JP4062360B2 (en) Light emitting element
JP5379703B2 (en) Ultraviolet semiconductor light emitting device
JP2003309288A (en) Light-emitting element
JP3214367B2 (en) Method for manufacturing semiconductor light emitting device
JP2000174341A (en) Gallium nitride based compound semiconductor light- emitting element
JP3969378B2 (en) Light emitting element
JP2013243202A (en) Manufacturing method of semiconductor light-emitting element
WO2005038936A1 (en) Light-emitting device and method for manufacturing same
KR101068864B1 (en) Semiconductor light emitting device and menufacturing method thereof
JP2950316B2 (en) Gallium nitride based compound semiconductor light emitting device and method of manufacturing the same
JP2000049377A (en) Manufacture of gallium nitride compound semiconductor light-emitting device
JP2008103759A (en) Light emitting element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041001

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20050706

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060414

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060425

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060905