JP2003309133A - High thermostability semiconductor element and power converter using the same - Google Patents

High thermostability semiconductor element and power converter using the same

Info

Publication number
JP2003309133A
JP2003309133A JP2002113245A JP2002113245A JP2003309133A JP 2003309133 A JP2003309133 A JP 2003309133A JP 2002113245 A JP2002113245 A JP 2002113245A JP 2002113245 A JP2002113245 A JP 2002113245A JP 2003309133 A JP2003309133 A JP 2003309133A
Authority
JP
Japan
Prior art keywords
common electrode
semiconductor element
high heat
electrode plates
outer cylinder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002113245A
Other languages
Japanese (ja)
Other versions
JP3809550B2 (en
Inventor
Hironori Kodama
弘則 児玉
Daisuke Takayama
大輔 高山
Katsunori Asano
勝則 浅野
Yoshitaka Sugawara
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kansai Electric Power Co Inc
Hitachi Ltd
Original Assignee
Kansai Electric Power Co Inc
Hitachi Ltd
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Filing date
Publication date
Application filed by Kansai Electric Power Co Inc, Hitachi Ltd filed Critical Kansai Electric Power Co Inc
Priority to JP2002113245A priority Critical patent/JP3809550B2/en
Publication of JP2003309133A publication Critical patent/JP2003309133A/en
Application granted granted Critical
Publication of JP3809550B2 publication Critical patent/JP3809550B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element wherein a plurality of SiC semiconductor chips are incorporated in a flat package, for attaining high reliability in higher temperature use and also durability in higher temperature use without causing oxidation deterioration, and provide a power converter that exerts higher performance comparing with a conventional power converter using an Si semiconductor element. <P>SOLUTION: The semiconductor element of high thermostability has such an arrangement that; a plurality of semiconductor chips are incorporated, being juxtaposed, in the flat package whose interior is airtightly sealed by a pair of common electrode plates and an insulating outer cylinder made of ceramics; and a Pt layer is formed at least on the externally exposed surface of each of the common electrode plates. Such an element is used for a power converter for exerting high performance. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、複数個の半導体チ
ップを並列に接続して、一つのパッケージに組み込んだ
新規な高耐熱半導体素子及びこれを用いた電力変換器に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel high heat resistant semiconductor element in which a plurality of semiconductor chips are connected in parallel and incorporated in one package, and a power converter using the same.

【0002】[0002]

【従来の技術】Si半導体エレクトロニクスの技術を駆使
して主回路電流を制御するパワーエレクトロニクスの技
術は、その性能向上と共に幅広い分野で応用され、さら
にその適用拡大がなされつつある。ダイオード、サイリ
スタの他、MOS構造ゲートへの入力信号により主電流を
制御するためのMOS制御デバイスであるMOS型電界効果ト
ランジスタ(以下MOSFETと略す)や、絶縁ゲート型バイ
ポーラトランジスタ(以下IGBTと略す)等が注目され、
パワースイッチングデバイスとしてモータPWM制御イ
ンバータの応用等に幅広く使われている。
2. Description of the Related Art The technology of power electronics, which controls the main circuit current by making full use of the technology of Si semiconductor electronics, has been applied in a wide range of fields as its performance has been improved, and its application is being expanded. In addition to diodes and thyristors, MOS type field effect transistors (hereinafter abbreviated as MOSFET), which are MOS control devices for controlling the main current by the input signal to the MOS structure gate, and insulated gate bipolar transistors (hereinafter abbreviated as IGBT). And so on,
It is widely used as a power switching device for applications such as motor PWM control inverters.

【0003】しかしながら、近年では、Siデバイスの限
界にせまる高性能デバイスの開発もなされてきており、
さらなる飛躍的なパワーデバイスの性能向上を目指し
て、Siに代わるSiC、GaN、ダイヤモンド等の新しい半導
体材料を用いたパワーデバイスの検討も始まっている。
なかでもSiCは、最も有望なデバイスとして注目され、
研究開発が進められている。SiCは、Siに比べて絶縁破
壊電界が大きく、さらにバンドギャップが広いため、高
温での半導体動作が可能である等の特徴を有するため、
特に大電力制御用に好適な高耐圧化や、高温での使用、
すなわち冷却系を簡略化したシステムの実現等が期待さ
れている。
However, in recent years, high-performance devices that have reached the limit of Si devices have been developed,
Aiming to further improve the performance of power devices, studies on power devices using new semiconductor materials such as SiC, GaN, and diamond, which replace Si, have begun.
Among them, SiC attracts attention as the most promising device,
Research and development is in progress. Since SiC has a larger dielectric breakdown electric field and a wider band gap than Si, it has the characteristics that it can operate semiconductors at high temperatures.
Especially, high withstand voltage suitable for high power control, use at high temperature,
That is, it is expected to realize a system in which the cooling system is simplified.

【0004】従来のSi半導体パワーデバイス実装形態で
は、低電力容量用の1チップを放熱板上にマウントした
後、全体を樹脂モールドしたデイスクリート素子や、よ
り大きな容量向けのモジュール構造と呼ばれるIGBT等の
パッケージ形態が主流となっている。
In the conventional Si semiconductor power device mounting mode, a discrete element in which one chip for low power capacity is mounted on a heat dissipation plate and then the whole is resin-molded, an IGBT called a module structure for larger capacity, etc. The package form of is becoming mainstream.

【0005】前記モジュール構造では、一般に放熱体兼
用の金属ベース上に絶縁板を介して半導体チップの第二
主面の主電極を半田付けし、第一主面上の主電極(エミ
ッタ電極)、および制御電極(ゲート電極)は、樹脂製
ケースに装備されたエミッタ、およびゲート用の外部導
出端子との間をアルミ等の導線でワイヤボンディング
し、パッケージ外部へ引き出している。また、パッケー
ジ内部には、チップの信頼性を確保するため、シリコー
ンゲルを充填している。
In the above-mentioned module structure, the main electrode on the second main surface of the semiconductor chip is generally soldered on a metal base which also serves as a heat radiator via an insulating plate, and the main electrode (emitter electrode) on the first main surface is The control electrode (gate electrode) is wire-bonded with a conductor such as aluminum between the emitter provided in the resin case and the external lead-out terminal for the gate, and is led out to the outside of the package. The package is filled with silicone gel to ensure the reliability of the chip.

【0006】一方、パワーデバイスの別の実装形態とし
て、外部電極を平型素子の両面に形成した素子が開発さ
れており、ダイオード、サイリスタ、GTO(gate turn−
offthyristor)、IGBT(insulated gate bipolar trans
istor)に適用されている。特に前記IGBTの平型素子で
は、複数のSiチップをパッケージ内に並列に組み込み、
その主面に形成されたエミッタ電極、コレクタ電極をそ
れぞれパッケージ側に設けた上下の電極板に外部から加
圧力を加えて面接続させて引き出すようにした加圧接触
構造のパッケージが提案されており、特に大容量のデバ
イスに好適な実装形態である。
On the other hand, as another mounting form of a power device, an element in which external electrodes are formed on both sides of a flat element has been developed, and a diode, a thyristor, a GTO (gate turn-).
offthyristor), IGBT (insulated gate bipolar trans)
istor) has been applied. Especially in the flat element of the IGBT, a plurality of Si chips are installed in parallel in a package,
A package with a pressure contact structure has been proposed in which the emitter electrode and the collector electrode formed on the main surface of the package are connected to the upper and lower electrode plates provided on the package side by external pressure to be surface-connected and pulled out. In particular, it is a mounting form suitable for a large capacity device.

【0007】例えば、特開平8−088240号公報において
は、実施例に21個のSi半導体チップ(9個のIGBTと1
2個のダイオード)を搭載した平型IGBTパッケージが開
示されている。
For example, in Japanese Patent Laid-Open No. 08-088240, 21 Si semiconductor chips (9 IGBT and 1
A flat IGBT package having two diodes) is disclosed.

【0008】このパッケージ構造の例を図7に示す。半
導体チップ25の第二主面(コレクタ側)は、パッケー
ジの共通電極(Cu)22上に設けられた1枚の大型の電
極用基板(Mo)24に搭載され、第一主面(エミッタ
側)はチップ25ごとに分離した個別の小型の圧接板
(Mo)23を介して、パッケージの共通電極(Cu)21
に接続する構造となっている。さらに、半導体チップ2
5のパッケージ内での位置決めは、各半導体チップ25
の外周部分に設置した樹脂製のチップフレーム27及び
これと一体型の外部フレーム26を用いて一括で行われ
ている。
An example of this package structure is shown in FIG. The second main surface (collector side) of the semiconductor chip 25 is mounted on one large electrode substrate (Mo) 24 provided on the common electrode (Cu) 22 of the package, and the first main surface (emitter side). ) Is a common electrode (Cu) 21 of the package via a separate small pressure contact plate (Mo) 23 separated for each chip 25.
It has a structure to connect to. Furthermore, the semiconductor chip 2
5 is positioned in the package by each semiconductor chip 25.
The chip chip 27 made of resin and the external frame 26 integrated with the resin chip frame 27 installed on the outer periphery of the chip are collectively processed.

【0009】WO98/43301号公報には、共通電極間に設け
られた中間電極間にIGBTチップを有し、共通電極間の外
周に絶縁外筒で覆ってフランジで接合した半導体装置が
示されている。
[0009] WO98 / 43301 discloses a semiconductor device having an IGBT chip between intermediate electrodes provided between common electrodes, and a flange between the common electrodes covered with an insulating outer cylinder. There is.

【0010】[0010]

【発明が解決しようとする課題】SiC、GaN、ダイヤモン
ド等の高耐熱半導体を用いて、その性能を最大限に活か
すためには、Siの場合(稼働温度150℃以下)に比べて
格段に高い300℃以上の高温での動作が必要となる。
[Problems to be Solved by the Invention] In order to maximize the performance of high heat-resistant semiconductors such as SiC, GaN, diamond, etc., it is much higher than that of Si (operating temperature of 150 ° C or less). It is necessary to operate at a high temperature of 300 ° C or higher.

【0011】ところが、上記公知例に見られるような従
来のSi半導体で用いられている実装形態のままでは、内
蔵する実装部品として樹脂部品を多用している等、元々
の材料自体の耐熱性の点で問題がある。更に、上記の平
型IGBTパッケージの実装では、共通電極基板の材料とし
て無酸素銅を用いており、300℃以上の高温での使用に
は、加圧による変形が大きく問題がある。又、パッケー
ジの外部に露出している共通電極や気密封止のためのフ
ランジ部品などの金属部分は、酸化して電気抵抗が増加
したり、酸化膜の剥離等で劣化が進行する等の種々の問
題がある。無酸素銅電極にNiめっき膜を施す例はある
が、Niでは300℃以上の高温での酸化を防止することが
できない。
However, in the mounting form used in the conventional Si semiconductor as seen in the above-mentioned known example, resin components are frequently used as built-in mounting parts, and the heat resistance of the original material itself is There is a problem in terms. Furthermore, in the mounting of the flat IGBT package described above, oxygen-free copper is used as the material of the common electrode substrate, and when used at a high temperature of 300 ° C. or higher, deformation due to pressure is a serious problem. In addition, the common electrode exposed to the outside of the package and the metal parts such as the flange parts for hermetic sealing are oxidized to increase the electric resistance, or are deteriorated due to peeling of the oxide film. I have a problem. Although there is an example of applying a Ni plating film to an oxygen-free copper electrode, Ni cannot prevent oxidation at a high temperature of 300 ° C or higher.

【0012】本発明の目的は、複数個のSiC半導体チッ
プを一つの平型パッケージに組み込んだ半導体素子を対
象に、より高い温度での使用に対して信頼性が高く、又
酸化劣化がなくより高温での使用に耐える半導体素子を
提供することにある。
An object of the present invention is to provide a semiconductor device in which a plurality of SiC semiconductor chips are incorporated in one flat package, which is highly reliable for use at a higher temperature and is free from oxidative deterioration. An object is to provide a semiconductor device that can be used at high temperatures.

【0013】又、本発明の目的は、Si半導体素子を用い
た従来の電力変換器に比べて、より高性能な電力変換器
を提供することにある。
Another object of the present invention is to provide a power converter with higher performance than the conventional power converter using a Si semiconductor element.

【0014】[0014]

【課題を解決するための手段】本発明は、一対の共通電
極板と、該共通電極板間に中間電極を介して併置して設
けられた複数個のシリコンより高い耐熱性を有する半導
体チップと、前記共通電極板間の外周に接合された絶縁
性セラミックス製外筒と、前記各々の半導体チップと中
間電極とを収納する絶縁性セラミックス製内筒とを有
し、該絶縁性セラミックス製外筒内に非酸化性ガスが充
填されていることを特徴とする高耐熱半導体素子にあ
る。
The present invention is directed to a pair of common electrode plates and a semiconductor chip having a higher heat resistance than a plurality of silicons provided side by side with the intermediate electrodes between the common electrode plates. An insulating ceramic outer cylinder joined to the outer periphery between the common electrode plates, and an insulating ceramic inner cylinder accommodating each of the semiconductor chips and the intermediate electrodes, the insulating ceramic outer cylinder A high heat-resistant semiconductor element having a non-oxidizing gas filled therein.

【0015】又、本発明は、一対の銅合金製共通電極板
と、該共通電極板間に中間電極を介して併置して設けら
れた複数個の半導体チップと、前記共通電極板間の外周
に接合された絶縁性セラミックス製外筒と、前記各々の
半導体チップと中間電極とを収納する絶縁性セラミック
ス製内筒とを有することを特徴とする高耐熱半導体素子
にある。
Further, according to the present invention, a pair of copper alloy common electrode plates, a plurality of semiconductor chips provided in parallel between the common electrode plates via an intermediate electrode, and an outer periphery between the common electrode plates. A high heat-resistant semiconductor element, comprising: an insulating ceramic outer cylinder joined to each other; and an insulating ceramic inner cylinder accommodating each of the semiconductor chips and the intermediate electrodes.

【0016】前記絶縁性セラミックス製外筒は、その外
周に電気絶縁性を高めるフィンが一体に設けられている
こと、前記半導体チップは、その各々が絶縁性セラミッ
クス製内筒内に設けられていること、前記絶縁性セラミ
ックス製外筒は、前記共通電極板に金属製フランジを介
してろう付け又は前記共通電極板に直接ろう付けされて
いること、前記金属製フランジの少なくとも一方は、径
方向に伸縮可能な構造を有すること、前記絶縁性セラミ
ックス製外筒に非酸化性ガスを供給する供給口が設けら
れていること、前記共通電極板の少なくとも外気に晒さ
れる表面に外気による酸化を防止する皮膜が設けられて
いることが好ましい。
The insulating ceramic outer cylinder is integrally provided with fins for enhancing electric insulation on the outer circumference thereof, and each of the semiconductor chips is provided in the insulating ceramic inner cylinder. That the insulating ceramic outer cylinder is brazed to the common electrode plate via a metal flange or directly brazed to the common electrode plate, at least one of the metal flanges is in a radial direction. Having an expandable structure, providing a supply port for supplying a non-oxidizing gas to the insulating ceramic outer cylinder, and preventing at least the surface of the common electrode plate exposed to the outside air from being oxidized by the outside air. It is preferable that a film is provided.

【0017】更に本発明は、一対の共通電極板と絶縁性
セラミックス製外筒により内部を気密封止された平型パ
ッケージ内の前記共通電極板間に複数個の半導体チップ
が並置して設けられ、少なくとも前記共通電極板の外部
に露出する表面にPt層が形成されていることを特徴とす
る高耐熱半導体素子にある。前記Ptコーティングは、そ
の下地にNi層が施されていることが好ましい。
Further, according to the present invention, a plurality of semiconductor chips are arranged side by side between the common electrode plates in a flat package whose inside is hermetically sealed by a pair of common electrode plates and an insulating ceramic outer cylinder. The Pt layer is formed on at least the surface of the common electrode plate exposed to the outside, which is a high heat resistant semiconductor element. It is preferable that the Pt coating has a Ni layer on its base.

【0018】前記一対の共通電極板が、析出硬化型銅合
金からなること、前記一対の共通電極板が、Cuを主成分
とし、Zr、Fe、Cr、Ti、Ag及びSnから選ばれる少なくと
も1種を0.1〜5重量%、好ましくは0.3〜1.5重量%含む合
金からなること、前記共通電極板と絶縁性セラミックス
の外筒とが、Agを主成分とするろう材によって接合され
ていること、前記共通電極板と絶縁性セラミックス製外
筒とは、熱膨張係数が2〜5×10−6/℃である鉄−ニッケ
ル合金、Fe-32〜42wt%Ni合金及びFe-30〜40wt%Ni−5〜2
0wt%Co合金製フランジ部材を介してAgを主成分とするろ
う材によって接合されていること、前記半導体チップの
少なくとも一つが、外部からの制御信号によって主電流
を制御する主電流制御機能を有すること、前記半導体チ
ップがSiCであることが好ましい。
The pair of common electrode plates are made of a precipitation hardening type copper alloy, and the pair of common electrode plates contain Cu as a main component and at least one selected from Zr, Fe, Cr, Ti, Ag and Sn. It is made of an alloy containing 0.1 to 5% by weight, preferably 0.3 to 1.5% by weight, and the common electrode plate and the outer cylinder of the insulating ceramics are joined by a brazing material containing Ag as a main component, The common electrode plate and the insulating ceramic outer cylinder have an iron-nickel alloy having a coefficient of thermal expansion of 2 to 5 × 10 −6 / ° C., Fe-32 to 42 wt% Ni alloy, and Fe-30 to 40 wt% Ni. −5 to 2
It is bonded by a brazing material containing Ag as a main component through a 0 wt% Co alloy flange member, and at least one of the semiconductor chips has a main current control function of controlling a main current by an external control signal. It is preferable that the semiconductor chip is SiC.

【0019】本発明の高耐熱半導体素子は、一対の共通
電極板と絶縁性セラミックスの外筒により内部を気密封
止された平型パッケージの中に、第一主面に少なくとも
第一の主電極、第二主面に少なくとも第二の主電極を有
する複数個の半導体チップを並置して組み込んだ半導体
素子であって、該一対の共通電極板の少なくともパッケ
ージの外部に露出する表面に露出する金属部分の表面に
Pt層が施されていることを特徴とする。
The high heat-resistant semiconductor element of the present invention comprises a flat package whose inside is hermetically sealed by a pair of common electrode plates and an outer cylinder of insulating ceramics, and at least the first main electrode on the first main surface. A semiconductor element in which a plurality of semiconductor chips having at least a second main electrode are juxtaposed on a second main surface, and the metal is exposed on at least the surface of the pair of common electrode plates exposed to the outside of the package. On the surface of the part
It is characterized by having a Pt layer.

【0020】また、本発明の電力変換器は、前記記載の
高耐熱半導体素子を主変換素子として用いたことを特徴
とする。
The power converter of the present invention is characterized by using the above-mentioned high heat-resistant semiconductor element as a main conversion element.

【0021】共通電極用の材料としては、高温での加圧
変形抵抗が大きい金属で、かつ電気抵抗の低い材料が好
ましい。上記の観点で、種々の試験、検討を行なった結
果、銅合金の中でも特に析出硬化型の銅合金が好ましい
事がわかった。中でも、Cuを主成分とし、Zr、Fe、Cr、
Ti、Ag、Snから選ばれる少なくとも1種以上の元素を0.1
〜5.0wt%含む合金が好ましく、特にZr、Fe、Crを含む銅
系合金が加圧変形抵抗が大きくより好ましい。
The material for the common electrode is preferably a metal having a high resistance to pressure deformation at high temperature and a low electric resistance. From the above viewpoints, as a result of various tests and studies, it was found that the precipitation hardening type copper alloy is particularly preferable among the copper alloys. Among them, the main component is Cu, Zr, Fe, Cr,
0.1 or more of at least one element selected from Ti, Ag, and Sn
Alloys containing ˜5.0 wt% are preferable, and copper-based alloys containing Zr, Fe, and Cr are particularly preferable because they have large pressure deformation resistance.

【0022】耐熱性の高い銅合金として、一般にベリリ
ウム銅があるが、銀ろう材とのぬれ性が悪く、フランジ
材やセラミックス材料と気密で信頼性の良い構造体を製
造するには不適であることが分かった。これに比べて、
上記した銅合金では、このような問題の発生がなく、信
頼性に優れる高耐熱半導体素子を製造することができる
ことが確認できた。
Beryllium copper is generally used as a heat-resistant copper alloy, but it has poor wettability with a silver brazing material and is not suitable for manufacturing a hermetically sealed and reliable structure with a flange material or a ceramic material. I found out. Compared to this,
It has been confirmed that the above-described copper alloy can produce a highly heat-resistant semiconductor element having excellent reliability without causing such a problem.

【0023】表面酸化保護膜としては、種々の材料構成
を検討した結果、高温での長期動作に対してもPtが耐熱
性、耐酸化性、電気伝導性に最も優れている事がわかっ
た。
As a result of examining various material constitutions for the surface oxidation protection film, it was found that Pt has the best heat resistance, oxidation resistance and electric conductivity even for long-term operation at high temperature.

【0024】本発明のような複雑な構造体の場合には、
外部に露出する金属の材料もいろいろな材料が混在する
ことになる。従って、いろいろな材料に対して密着性を
それぞれ充分確保してPt保護膜を形成するためには、Ni
膜をPt膜の下地膜としてさらに設けることも有効であ
る。Niは、Pt膜との密着性を確保すると共に、上記銅合
金との高温での拡散反応をよく抑制できるので、高温で
の長期信頼性がさらに向上できることが分かった。ま
た、Niは、銅合金とPtの中間の熱膨張係数を有すること
から、熱ストレスを緩和できるので、より保護膜の信頼
性を向上できる。熱サイクル等の条件がより過酷な条件
での使用が想定される場合には、Ni膜とPt膜の間に、よ
り密着性を向上するための薄いAuストライクめっきを施
すことも有効である。
In the case of a complex structure such as the present invention,
Various materials are mixed as the metal material exposed to the outside. Therefore, in order to form a Pt protective film with sufficient adhesion to various materials, Ni is required.
It is also effective to further provide the film as a base film of the Pt film. It has been found that Ni secures the adhesion to the Pt film and can well suppress the diffusion reaction with the copper alloy at high temperature, so that the long-term reliability at high temperature can be further improved. Further, since Ni has a coefficient of thermal expansion intermediate between that of the copper alloy and Pt, the thermal stress can be relaxed, and therefore the reliability of the protective film can be further improved. When it is expected to be used under more severe conditions such as heat cycle, it is also effective to apply thin Au strike plating between the Ni film and the Pt film to improve the adhesion.

【0025】膜の形成方法としては、めっきの他、スパ
ッタ、蒸着等の方法のいずれかでも良いが、本実施例の
ような複雑な形状を有する金属面に全面に保護膜をつけ
るためには、めっき法が最も好ましい。膜厚は、使用す
る温度条件、及び補償すべき時間条件によって最適なも
のが選ばれる。
The method of forming the film may be plating, sputtering, vapor deposition, or the like. However, in order to form a protective film on the entire metal surface having a complicated shape as in this embodiment, The plating method is most preferable. The optimum film thickness is selected depending on the temperature conditions used and the time conditions to be compensated.

【0026】前記絶縁性セラミックス製外筒内に充填さ
れる非酸化性ガスとしては、窒素ガスやSFガス、又
はこれらの混合ガスが好ましい。
The non-oxidizing gas filled in the insulating ceramic outer cylinder is preferably nitrogen gas, SF 6 gas, or a mixed gas thereof.

【0027】高耐熱半導体として、SiC半導体が好まし
いが、SiC以外のGaN、ダイヤモンド等のSiよりも高温で
動作可能な高耐熱半導体についても同様に実施可能であ
る。
As the high heat resistant semiconductor, a SiC semiconductor is preferable, but a high heat resistant semiconductor that can operate at a temperature higher than that of Si such as GaN and diamond other than SiC can be similarly implemented.

【0028】本発明は第一主面に第一の主電極と第二主
面に第二の主電極を有する高耐熱半導体素子全般を対象
としており、PNダイオード、ショットキーダイオード、
SID等の各種ダイオードの他、絶縁ゲート形トランジス
タ(MOSトランジスタ)、絶縁ゲート形サイリスタ(MOS
制御サイリスタ)等の制御電極付き半導体素子、すなわ
ち第一主面に第一の主電極と制御電極、第二主面に第二
の主電極を有し、外部からの制御信号による主電流制御
機能を有する等に対しても同様に実施できる。
The present invention is intended for general high heat-resistant semiconductor devices having a first main electrode on the first main surface and a second main electrode on the second main surface, and includes a PN diode, a Schottky diode,
In addition to various diodes such as SID, insulated gate transistor (MOS transistor), insulated gate thyristor (MOS
A semiconductor element with a control electrode such as a control thyristor, that is, a first main electrode and a control electrode on the first main surface and a second main electrode on the second main surface, and a main current control function by a control signal from the outside. The same can be applied to the case of having.

【0029】また、本発明は、ダイオードチップのみを
多数個平型パッケージに位置決めして実装した素子、MO
SFET等のスイッチング半導体のみからなる半導体素子、
およびダイオードチップとスイッチング半導体チップを
複数個逆並列に並べた半導体素子、等の各種素子に適用
できる。
Further, according to the present invention, a device in which a large number of diode chips alone are positioned and mounted in a flat package, MO
Semiconductor element consisting only of switching semiconductors such as SFET,
Also, it can be applied to various elements such as a semiconductor element in which a plurality of diode chips and switching semiconductor chips are arranged in antiparallel.

【0030】[0030]

【発明の実施の形態】(実施例1)図1は、本発明の平
型半導体素子の中央部縦断面図である。本実施例では、
複数個のSiCチップを組み込んだ例である。SiCチップ3
には両主面(図では上側面と下側面)に各々主電極が形
成されている。SiCチップ3には、放熱と電気的接続を
兼ねた中間電極4がチップ3の各主電極と接する形で上
下に配置されており、これが平型半導体素子の外部電極
となる第1の共通電極1と第2の共通電極1に挟まれて
いる。図面の上がプラス極、下がマイナス極となってい
る。これらの一対の共通電極1の間は、円筒形状の絶縁
性セラミックス製外筒2により外部絶縁され、さらに共
通電極1と絶縁性セラミックス製外筒2の間は、低熱膨
張性のFe-36wt%Ni合金製フランジ部材6によりパッケー
ジ内部をシール封止したハーメチック構造となってい
る。上部のフランジ部材6は径方向に伸縮可能に蛇腹形
状を有し、それと共通電極1、及び絶縁性セラミックス
製外筒2の間は、銀(Ag)ろう材で気密接合されてい
る。また、共通電極の材料には、Crを0.4〜1.2wt%含有
するクロム銅合金を用いた。下部のフランジ部材6に対
しても同様に径方向に伸縮可能に蛇腹形状とするのが好
ましく、径方向の応力を緩和する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a vertical sectional view of a central portion of a flat semiconductor device of the present invention. In this embodiment,
This is an example of incorporating a plurality of SiC chips. SiC chip 3
The main electrodes are formed on both main surfaces (upper side surface and lower side surface in the figure) of each. On the SiC chip 3, an intermediate electrode 4 that also serves as heat dissipation and electrical connection is arranged above and below in contact with each main electrode of the chip 3, and this is the first common electrode that serves as an external electrode of the flat semiconductor device. It is sandwiched between 1 and the second common electrode 1. The top of the drawing is the positive pole and the bottom is the negative pole. The pair of common electrodes 1 are externally insulated by a cylindrical insulating ceramics outer cylinder 2, and the common electrode 1 and the insulating ceramics outer cylinder 2 have a low thermal expansion property of Fe-36wt%. It has a hermetic structure in which the inside of the package is sealed and sealed by the Ni alloy flange member 6. The upper flange member 6 has a bellows shape capable of expanding and contracting in the radial direction, and the common electrode 1 and the insulating ceramic outer cylinder 2 are airtightly joined with a silver (Ag) brazing material. A chromium copper alloy containing 0.4 to 1.2 wt% of Cr was used as the material of the common electrode. Similarly, it is preferable that the lower flange member 6 also has a bellows shape so that it can be expanded and contracted in the radial direction, and the stress in the radial direction is relaxed.

【0031】これらの金属製フランジ部材6は上部の共
通電極の上部に設けられた凹み部、下部の共通電極の下
部に設けられた凹み部に各々ろう付けされ、絶縁性セラ
ミックス製外筒2には、上部の共通電極6に対応して別
途ろう付けして設けられた金属製フランジ6によって互
いに溶接されて結合され、下部の共通電極1には下部の
フランジ部材6がろう付けされる。上部の金属製フラン
ジ6の互いの溶接結合部が所望の長さをもつことによっ
て上部の共通電極1が上方に熱膨張しても伸びる構造に
なっている。
These metal flange members 6 are brazed to the recesses provided in the upper part of the upper common electrode and the recesses provided in the lower part of the lower common electrode, respectively. Are welded to each other by metal flanges 6 separately provided by brazing corresponding to the upper common electrode 6, and the lower flange member 6 is brazed to the lower common electrode 1. Since the welded joints of the upper metal flanges 6 have desired lengths, the upper common electrode 1 is extended even when it is thermally expanded upward.

【0032】SiCチップ3の各々は、各中間電極4の大
きさ、形状に対応した内周面側を有する四角形状のセラ
ミックス絶縁支持体5に収納されており、共通電極に接
しないような高さになっている。SiCチップ3への接触
面積は、中間電極4の上が小さく、下が上より大きく形
成されている。この接触構造は、SiCチップ3の耐圧の
点から設定される。
Each of the SiC chips 3 is housed in a quadrangular ceramic insulating support 5 having an inner peripheral surface side corresponding to the size and shape of each intermediate electrode 4, and has a height that does not contact the common electrode. It is The contact area with the SiC chip 3 is formed such that the upper part of the intermediate electrode 4 is smaller and the lower part is larger than the upper part. This contact structure is set in terms of the breakdown voltage of the SiC chip 3.

【0033】絶縁性セラミックス製外筒2には炭化ケイ
素、窒化ケイ素、窒化アルミニウム、ムライト、アルミ
ナ等が好適である。
Silicon carbide, silicon nitride, aluminum nitride, mullite, alumina and the like are suitable for the insulating ceramic outer cylinder 2.

【0034】図1に示すように、絶縁性セラミックス製
外筒2のそと表面の下部に沿面距離を大きくするリング
状の突起としてフィンが全周に設けられている。
As shown in FIG. 1, fins are provided around the entire circumference of the outer surface of the insulating ceramic outer cylinder 2 as ring-shaped projections for increasing the creepage distance.

【0035】SiCチップ3の半導体チップほかの部品を
内蔵した後、前記フランジ間を溶接封止14する。その
後、内部ガス置換用パイプ8を用いて半導体素子内部を
窒素ガス等の非酸化性ガスによって置換、充填した後、
最後に内部ガス置換用パイプ8の外部先端を溶接して完
全に半導体素子内部を封止する。次に、この半導体素子
の外部に露出している金属部分(共通電極、フランジ、
ろう材、パイプ、溶接部)に電極を取り付けて、めっき
浴中で電気Niめっき(厚さ5〜10μm)を施した後、さら
に同様に厚さ2〜5μmのPtめっき9を施した。Ptめっ
き9は共通電極1とフランジ部材6の金属面の外表面全
面に形成した。
After the semiconductor chip and other parts such as the SiC chip 3 are built in, the flanges are welded and sealed 14 together. Then, after the inside of the semiconductor element is replaced and filled with a non-oxidizing gas such as nitrogen gas using the internal gas replacement pipe 8,
Finally, the outer tip of the internal gas replacement pipe 8 is welded to completely seal the inside of the semiconductor element. Next, the metal portion exposed to the outside of this semiconductor element (common electrode, flange,
An electrode was attached to a brazing material, a pipe, and a welded portion, and electroplating with Ni (thickness: 5 to 10 μm) was performed in a plating bath, and then Pt plating 9 with a thickness of 2 to 5 μm was similarly applied. The Pt plating 9 was formed on the entire outer surface of the metal surface of the common electrode 1 and the flange member 6.

【0036】図2は、本実施例の半導体素子の半導体チ
ップ部を通る横断面図を示しており、図中に示したA−
A'位置は図1の縦断面位置に対応している。又、SiCチ
ップ3は四角絶縁性セラミックス製内筒のセラミックス
絶縁支持体内に挿入され、支持され、その高さはSiCチ
ップ3を介して両側に設けられた中間電極4との全体の
高さより低く設定される。又、中間電極4は上と下で異
なった大きさを有し、上を下より小さくすることによっ
て両者のSiCチップ3に対する接触をより高めることが
できる。
FIG. 2 is a cross-sectional view showing a semiconductor chip portion of the semiconductor device of this embodiment, which is taken along line A- in FIG.
The position A'corresponds to the position of the vertical cross section in FIG. Further, the SiC chip 3 is inserted into and supported by a ceramics insulating support body of an inner cylinder made of a square insulating ceramics, and its height is lower than the entire height with the intermediate electrodes 4 provided on both sides through the SiC chip 3. Is set. Further, the intermediate electrode 4 has different sizes on the upper side and the lower side, and by making the upper side smaller than the lower side, the contact between the both can be further enhanced.

【0037】(実施例2)図3は本発明の平型半導体素
子の縦断面図である。複数個のSiCダイオードチップ3
1、32を組み込んだ例である。SiCダイオードチップ
31、32には、SiCチップの一方の側にアノード電
極、他方の面にカソード電極が形成されており、これら
が半導体素子の外部電極となる第1の共通電極11と第
2の共通電極12に挟まれている。本実施例では、上記
実施例1で用いた中間電極部品を用いておらず、代わり
に図に示すような共通電極の突起部13を設けている。
本実施例における断面構造は図2と同様であり、SiCチ
ップが7個配置されている。
(Embodiment 2) FIG. 3 is a vertical sectional view of a flat semiconductor device of the present invention. Multiple SiC diode chips 3
This is an example in which 1 and 32 are incorporated. Each of the SiC diode chips 31 and 32 has an anode electrode formed on one side of the SiC chip and a cathode electrode formed on the other surface thereof, and these electrodes serve as external electrodes of the semiconductor element. It is sandwiched between the common electrodes 12. In this embodiment, the intermediate electrode part used in the above-mentioned first embodiment is not used, and instead the protrusion 13 of the common electrode as shown in the figure is provided.
The cross-sectional structure in this embodiment is similar to that of FIG. 2, and seven SiC chips are arranged.

【0038】これらの一対の共通電極11、12の間
は、絶縁性のセラミックス製外筒2により外部絶縁さ
れ、さらに共通電極と絶縁外筒の間は、低熱膨張性Fe-N
i-Co合金製フランジ部材61、62によりパッケージ内
部をシール封止したハーメチック構造となっている。フ
ランジ部材61、62と共通電極11、12、及び絶縁
外筒2の間は、銀ろう材(JIS BAg-8)で気密接合され
ている。また、本実施例では共通電極11、12の材料
に、Zrを0.1〜0.15wt%含有するジルコニウム銅合金を用
いた。上部フランジ部材61は実施例1と同様に径方向
に伸縮可能な形状を有すると共に、絶縁性セラミックス
製外筒2の上部に対しても同じ合金のフランジがろう付
けによって設けられ、共通電極11が共通電極12に対
して上下方向に伸縮可能な適当な長さを有して溶接接合
構造を有する。絶縁性セラミックス製外筒2の下部に対
しても同じ合金のフランジがろう付けによって設けられ
径方向に伸縮可能な構造を有する。
The pair of common electrodes 11 and 12 are externally insulated by an insulating ceramic outer cylinder 2, and the common electrode and the insulating outer cylinder have a low thermal expansion Fe-N.
The i-Co alloy flange members 61 and 62 form a hermetic structure in which the inside of the package is sealed and sealed. The flange members 61 and 62, the common electrodes 11 and 12, and the insulating outer cylinder 2 are airtightly joined with a silver brazing material (JIS BAg-8). Further, in this embodiment, a zirconium-copper alloy containing 0.1 to 0.15 wt% of Zr is used as the material of the common electrodes 11 and 12. The upper flange member 61 has a shape capable of expanding and contracting in the radial direction similarly to the first embodiment, and a flange of the same alloy is provided by brazing also on the upper portion of the insulating ceramic outer cylinder 2, and the common electrode 11 is The common electrode 12 has an appropriate length that can be expanded and contracted in the vertical direction and has a welded joint structure. A flange made of the same alloy is also provided by brazing on the lower part of the insulating ceramic outer cylinder 2, and has a structure capable of expanding and contracting in the radial direction.

【0039】SiCチップ32は断面が四角円筒状のセラ
ミックス絶縁部材内に挿入され、SiCチップ32に対す
る接触は上部の共通電極11に設けられた突起によって
行われ、下部の共通電極12には搭載によって行われ
る。
The SiC chip 32 is inserted into a ceramic insulating member having a rectangular cylindrical cross section, and the contact with the SiC chip 32 is made by a protrusion provided on the upper common electrode 11 and mounted on the lower common electrode 12 by mounting. Done.

【0040】半導体チップほかの部品を内蔵した後、前
記フランジ間を溶接封止15する。その後、内部ガス置
換用パイプ8を用いて半導体素子内部を窒素ガス置換、
充填した後、最後に内部ガス置換用パイプ8の外部先端
を溶接して完全に半導体素子内部を封止する。次に、こ
の半導体素子の外部に露出している金属部分に電極を取
り付けて、めっき浴中で電気Ptめっき9を外部に露出し
ている金属部分(共通電極、フランジ、ろう材、パイ
プ、溶接部)全面に施した。めっき膜の平均厚さは5μ
mであった。
After the semiconductor chip and other parts are built in, the flanges are sealed by welding 15. After that, the inside of the semiconductor element is replaced with nitrogen gas by using the internal gas replacement pipe 8,
After filling, finally, the outer tip of the internal gas replacement pipe 8 is welded to completely seal the inside of the semiconductor element. Next, an electrode is attached to the metal part exposed to the outside of this semiconductor element, and the metal part (common electrode, flange, brazing material, pipe, welding, etc.) where the electric Pt plating 9 is exposed to the outside in the plating bath. Part) applied to the entire surface. Average thickness of plating film is 5μ
It was m.

【0041】(実施例3)図4及び図5は本発明の高耐
熱半導体素子の共通電極と絶縁性セラミックスの外筒部
分の拡大縦断面図である。いずれのSiCチップ、中間電
極及びセラミックス絶縁支持体の構造は実施例1又は2
と同様に構成される。本実施例では、共通電極板1と絶
縁性セラミックスの外筒2を繋ぐ封止部材として、フラ
ンジ部材を用いず、共通電極板1と絶縁性セラミックス
の外筒2を直接Agを主成分とするろう材で接合している
例を示している。この場合にも、完全に半導体素子内部
を気密封止した後、この半導体素子の外部に露出してい
る金属部分(共通電極、ろう材、パイプ、溶接部)の全
面に、Ptめっき9を施してある。接合の例として、図4
では、ストレートな接合であり、図5では共通電極板1
にリング状の突起が設けられ、絶縁性セラミックス製外
筒2の内周面に対応する位置に溝が設けられている。絶
縁性セラミックス製外筒2の一部外周に図1と同様にリ
ング状の突起を有するフィンが形成されている。
(Embodiment 3) FIGS. 4 and 5 are enlarged vertical cross-sectional views of the common electrode of the high heat-resistant semiconductor element of the present invention and the outer cylinder portion of the insulating ceramics. The structure of any of the SiC chips, the intermediate electrode, and the ceramics insulating support is the same as in Example 1 or
Is constructed in the same way as. In this embodiment, a flange member is not used as a sealing member that connects the common electrode plate 1 and the outer cylinder 2 of insulating ceramics, and the common electrode plate 1 and the outer cylinder 2 of insulating ceramics contain Ag as a main component. An example of joining with a brazing material is shown. Also in this case, after completely hermetically sealing the inside of the semiconductor element, Pt plating 9 is applied to the entire surface of the metal portion (common electrode, brazing material, pipe, welded portion) exposed to the outside of this semiconductor element. There is. As an example of joining, FIG.
Then, it is a straight joint, and in FIG.
Is provided with a ring-shaped projection, and a groove is provided at a position corresponding to the inner peripheral surface of the insulating ceramic outer cylinder 2. As in FIG. 1, fins having ring-shaped protrusions are formed on a part of the outer circumference of the insulating ceramic outer cylinder 2.

【0042】実施例では、共通電極、あるいはパッケー
ジの外形が丸型の例を示したが、4角形の半導体装置も
当然可能であり、この場合は絶縁性の外筒も4角形がよ
い。パッケージング材料の製造コスト等の種々の他の要
因も勘案して望ましい形状を選択すればよい。
In the embodiment, the outer shape of the common electrode or the package is round, but a quadrilateral semiconductor device is naturally possible, and in this case, the insulating outer cylinder is also preferably quadrangular. A desired shape may be selected in consideration of various other factors such as the manufacturing cost of the packaging material.

【0043】(実施例4)図6は、実施例1〜3に記載
の本発明の高耐熱半導体素子を用いた電力用自励式変換
器の1ブリッジ分の構成回路図である。主変換素子とな
るSiC MOSFET18とSiCダイオード19が逆並列に配置
され、さらにn個直列に接続された構成となっている。
これらMOSFETとダイオードは、多数のSiC半導体チップ
を並列実装した平型半導体素子を示している。前述の逆
導通型SiC平型半導体素子を用いた場合には、図中のMOS
FET18とダイオード19がまとめて一つのパッケージ
に収められた形となる。
(Embodiment 4) FIG. 6 is a circuit diagram of one bridge of a self-excited converter for electric power using the high heat resistant semiconductor element of the present invention described in Embodiments 1 to 3. A SiC MOSFET 18 and a SiC diode 19, which are main conversion elements, are arranged in antiparallel, and n pieces are connected in series.
These MOSFETs and diodes represent flat semiconductor elements in which many SiC semiconductor chips are mounted in parallel. When the reverse conduction type SiC flat semiconductor device is used, the MOS in the figure
The FET 18 and the diode 19 are put together in one package.

【0044】なお、前記半導体素子は、電力系統に用い
られる自励式変換器、ミル用変換器や、可変速揚水発
電、圧延機、ビル内変電所設備、電鉄用変電設備、ナト
リウム硫黄(NaS)電池システム等の変換器にも用いる
ことができる。
The semiconductor element is a self-exciting converter used in an electric power system, a converter for a mill, a variable speed pumped hydro, a rolling mill, a substation facility, a substation facility for electric railway, sodium sulfur (NaS). It can also be used in converters such as battery systems.

【0045】さらに、前記したごとき高い信頼性を有す
る高耐熱半導体素子を用いることにより、Si半導体素子
を用いた従来の電力変換器に比べて、より高性能な電力
変換器が実現できる。すなわち、本発明の半導体素子を
用いた電力変換器は、Si半導体素子を用いた場合に比べ
て、特に高耐圧化した場合に損失が大幅に低減でき省エ
ネルギー化が実現できるだけでなく、さらに素子の高温
での使用が可能となるため、冷却等の負担が軽減でき、
変換器がコンパクトにできるので、コストを大幅に低減
できる。
Further, by using the highly heat-resistant semiconductor element having high reliability as described above, a higher performance power converter can be realized as compared with the conventional power converter using the Si semiconductor element. That is, the power converter using the semiconductor element of the present invention, compared with the case of using the Si semiconductor element, not only can achieve a significant reduction in loss and energy saving when the breakdown voltage is increased, and further Since it can be used at high temperatures, the burden of cooling etc. can be reduced,
Since the converter can be made compact, the cost can be significantly reduced.

【0046】[0046]

【発明の効果】本発明によれば、複数個の半導体チップ
を一つの平型パッケージに組み込んだ半導体素子を対象
に、従来にない高い温度での使用に対して信頼性の高い
高耐熱半導体素子を提供することができる。
According to the present invention, a semiconductor device in which a plurality of semiconductor chips are incorporated in one flat package is targeted, and a highly heat-resistant semiconductor device which is highly reliable for use at a high temperature which has never been used in the past. Can be provided.

【0047】又、上述の高い信頼性を有するSiC半導体
素子を用いることにより、従来、高耐圧、大電流容量の
分野で使用されてきたSi半導体素子を用いた変換器に比
べて、より高温での安定な動作が可能な電力変換器を提
供することができる。
Further, by using the above-mentioned highly reliable SiC semiconductor element, it is possible to operate at a higher temperature than the converter using the Si semiconductor element which has been conventionally used in the field of high breakdown voltage and large current capacity. It is possible to provide a power converter capable of stable operation.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の半導体素子の縦断面図である。FIG. 1 is a vertical cross-sectional view of a semiconductor device of the present invention.

【図2】 本発明の半導体素子の横断面図である。FIG. 2 is a cross-sectional view of a semiconductor device of the present invention.

【図3】 本発明の半導体素子の縦断面図である。FIG. 3 is a vertical sectional view of a semiconductor device of the present invention.

【図4】 本発明の共通電極と絶縁性セラミックスの外
筒部分の拡大縦断面図である。
FIG. 4 is an enlarged vertical cross-sectional view of a common electrode of the present invention and an outer cylinder portion of insulating ceramics.

【図5】 本発明の共通電極と絶縁性セラミックスの外
筒部分の拡大縦断面図である。
FIG. 5 is an enlarged vertical cross-sectional view of an outer cylinder portion of the common electrode and the insulating ceramics of the present invention.

【図6】 本発明の半導体素子を用いた変換器の1ブリ
ッジ分の構成回路図である。
FIG. 6 is a configuration circuit diagram of one bridge of a converter using the semiconductor device of the present invention.

【図7】 従来の半導体装置の縦断面図である。FIG. 7 is a vertical cross-sectional view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1、11、12、21、22…共通電極、2…絶縁性セ
ラミックスの外筒、3、25、31、32…半導体チッ
プ、4、23、24…中間電極、5…セラミック絶縁支
持体、6、61、62…フランジ、7…不活性ガス、8
…内部ガス置換用パイプ、9、91…コーティング膜、
10…ロウ材、13…共通電極の突起部、14、15…
溶接部、18…SiCMOSFET、19…SiCダイオード、20
…スナバ、21、22…共通電極、23、24…中間電
極、25…半導体チップ、26…樹脂製外部フレーム、
27…樹脂製チップフレーム、41…耐熱絶縁性部材。
1, 11, 12, 21, 22, ... Common electrode, 2 ... Insulating ceramic outer cylinder, 3, 25, 31, 32 ... Semiconductor chip, 4, 23, 24 ... Intermediate electrode, 5 ... Ceramic insulating support, 6 , 61, 62 ... Flange, 7 ... Inert gas, 8
... Internal gas replacement pipes, 9, 91 ... Coating film,
10 ... Brazing material, 13 ... Common electrode protrusion, 14, 15 ...
Welded portion, 18 ... SiC MOSFET, 19 ... SiC diode, 20
... snubber 21, 21, 22 ... common electrode, 23, 24 ... intermediate electrode, 25 ... semiconductor chip, 26 ... resin outer frame,
27 ... Resin chip frame, 41 ... Heat-resistant insulating member.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 高山 大輔 大阪府大阪市北区中之島3丁目3番22号 関西電力株式会社内 (72)発明者 浅野 勝則 大阪府大阪市北区中之島3丁目3番22号 関西電力株式会社内 (72)発明者 菅原 良孝 大阪府大阪市北区中之島3丁目3番22号 関西電力株式会社内 Fターム(参考) 5F047 JA02 JA11 JA20    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Daisuke Takayama             3-3-22 Nakanoshima, Kita-ku, Osaka City, Osaka Prefecture             Kansai Electric Power Co., Inc. (72) Inventor Katsunori Asano             3-3-22 Nakanoshima, Kita-ku, Osaka City, Osaka Prefecture             Kansai Electric Power Co., Inc. (72) Inventor Yoshitaka Sugawara             3-3-22 Nakanoshima, Kita-ku, Osaka City, Osaka Prefecture             Kansai Electric Power Co., Inc. F-term (reference) 5F047 JA02 JA11 JA20

Claims (19)

【特許請求の範囲】[Claims] 【請求項1】一対の共通電極板と、該共通電極板間に中
間電極を介して併置して設けられた複数個のシリコンよ
り高耐熱性の半導体チップと、前記共通電極板間の外周
に接合された絶縁性セラミックス製外筒と、前記各々の
半導体チップと中間電極とを収納する絶縁性セラミック
ス製内筒とを有し、該絶縁性セラミックス製外筒内に非
酸化性ガスが充填されていることを特徴とする高耐熱半
導体素子。
1. A pair of common electrode plates, a plurality of semiconductor chips having a heat resistance higher than that of silicon provided in parallel between the common electrode plates via an intermediate electrode, and an outer periphery between the common electrode plates. A joined insulating ceramic outer cylinder and an insulating ceramic inner cylinder for accommodating the semiconductor chips and the intermediate electrodes are provided, and the insulating ceramic outer cylinder is filled with a non-oxidizing gas. A high heat-resistant semiconductor element characterized in that
【請求項2】一対の銅合金製共通電極板と、該共通電極
板間に中間電極を介して併置して設けられた複数個の半
導体チップと、前記共通電極板間の外周に接合された絶
縁性セラミックス製外筒と、前記各々の半導体チップと
中間電極とを収納する絶縁性セラミックス製内筒とを有
することを特徴とする高耐熱半導体素子。
2. A pair of copper alloy common electrode plates, a plurality of semiconductor chips provided in parallel between the common electrode plates via an intermediate electrode, and joined to the outer periphery between the common electrode plates. A high heat-resistant semiconductor element comprising an insulating ceramic outer cylinder and an insulating ceramic inner cylinder accommodating each of the semiconductor chips and the intermediate electrode.
【請求項3】一対の共通電極板と、該共通電極板間に共
通電極板に直接接し併置して設けられた複数個の半導体
チップと、前記共通電極板間の外周に接合された絶縁性
セラミックス製外筒とを有し、該絶縁性セラミックス製
外筒内に非酸化性ガスが充填されていることを特徴とす
る高耐熱半導体素子。
3. A pair of common electrode plates, a plurality of semiconductor chips provided in direct contact with the common electrode plates between the common electrode plates and provided side by side, and an insulating property bonded to the outer periphery between the common electrode plates. A high heat-resistant semiconductor element, comprising: a ceramic outer cylinder, wherein the insulating ceramic outer cylinder is filled with a non-oxidizing gas.
【請求項4】請求項1〜3のいずれかにおいて、前記絶
縁性セラミックス製外筒は、その外周面に沿面距離を大
きくするリング状のフィンが一体に設けられていること
を特徴とする高耐熱半導体素子。
4. An insulating ceramic outer cylinder according to claim 1, wherein a ring-shaped fin for increasing a creepage distance is integrally provided on an outer peripheral surface of the outer cylinder. Heat-resistant semiconductor element.
【請求項5】請求項1〜4のいずれかにおいて、前記絶
縁性セラミックス製内筒は、ストレートな筒状、又は内
周面が前記中間電極の上下の形状に沿った四角筒状又は
円筒状を有することを特徴とする高耐熱半導体素子。
5. The inner cylinder made of insulating ceramics according to any one of claims 1 to 4, wherein the inner cylinder is made of a straight cylinder, or the inner peripheral surface thereof is a quadrangular cylinder or a cylinder having the upper and lower shapes of the intermediate electrode. A high heat-resistant semiconductor element having:
【請求項6】請求項1〜5のいずれかにおいて、前記絶
縁性セラミックス製外筒は、前記共通電極板に金属製フ
ランジを介してろう付け又は前記共通電極板に直接ろう
付けされていることを特徴とする高耐熱半導体素子。
6. The outer cylinder made of insulating ceramics according to claim 1, which is brazed to the common electrode plate via a metal flange or directly brazed to the common electrode plate. High heat resistance semiconductor device characterized by:
【請求項7】請求項1〜6のいずれかにおいて、前記金
属製フランジの少なくとも一方は、径方向に伸縮可能な
構造を有することを特徴とする高耐熱半導体素子。
7. The high heat-resistant semiconductor element according to claim 1, wherein at least one of the metal flanges has a structure capable of expanding and contracting in a radial direction.
【請求項8】請求項1〜7のいずれかにおいて、前記絶
縁性セラミックス製外筒に非酸化性ガスを供給する供給
口が設けられていることを特徴とする高耐熱半導体素
子。
8. A high heat-resistant semiconductor element according to claim 1, wherein the insulating ceramic outer cylinder is provided with a supply port for supplying a non-oxidizing gas.
【請求項9】請求項1〜8のいずれかにおいて、少なく
とも前記共通電極板の外気に晒される表面、又は少なく
とも前記共通電極板の外気に晒される表面と前記金属製
フランジの外気に晒される表面に外気による酸化を防止
する皮膜又はPt層が設けられていることを特徴とする高
耐熱半導体素子。
9. The surface of at least the common electrode plate exposed to the outside air, or at least the surface of the common electrode plate exposed to the outside air and the surface of the metal flange exposed to the outside air according to any one of claims 1 to 8. A high heat-resistant semiconductor element, characterized in that a film or a Pt layer for preventing oxidation due to outside air is provided on the inside.
【請求項10】一対の共通電極板と絶縁性セラミックス
製外筒により内部を気密封止された平型パッケージ内の
前記共通電極板間に複数個の半導体チップが並置して設
けられ、前記共通電極板の少なくとも外部に露出する表
面にPt層が形成されていることを特徴とする高耐熱半導
体素子。
10. A plurality of semiconductor chips are juxtaposed between the common electrode plates in a flat package whose inside is hermetically sealed by a pair of common electrode plates and an insulating ceramic outer cylinder. A high heat-resistant semiconductor element, wherein a Pt layer is formed on at least a surface of the electrode plate exposed to the outside.
【請求項11】請求項10において、前記Pt層は、その
下地にNi層が施されていることを特徴とする高耐熱半導
体素子。
11. The high heat-resistant semiconductor element according to claim 10, wherein the Pt layer is provided with a Ni layer as an underlayer.
【請求項12】請求項1〜11のいずれかにおいて、前
記一対の共通電極板が析出硬化型銅合金からなることを
特徴とする高耐熱半導体素子。
12. A high heat-resistant semiconductor element according to claim 1, wherein the pair of common electrode plates are made of a precipitation hardening type copper alloy.
【請求項13】請求項1〜12のいずれかにおいて、前
記一対の共通電極板が、Cuを主成分とし、Zr、Fe、Cr、
Ti、Ag及びSnから選ばれる少なくとも1種を0.1〜5重量
%含む合金からなることを特徴とする高耐熱半導体素
子。
13. The pair of common electrode plates according to claim 1, wherein the pair of common electrode plates contains Cu as a main component, and Zr, Fe, Cr,
0.1-5 weight of at least one selected from Ti, Ag and Sn
High heat-resistant semiconductor element characterized by being made of an alloy containing 100%.
【請求項14】請求項1〜13のいずれかにおいて、前
記共通電極板と絶縁性セラミックスの外筒とが、Agを主
成分とするろう材によって接合されていることを特徴と
する高耐熱半導体素子。
14. The high heat-resistant semiconductor according to claim 1, wherein the common electrode plate and an insulating ceramic outer cylinder are joined by a brazing material containing Ag as a main component. element.
【請求項15】請求項1〜14のいずれかにおいて、前
記金属製フランジは、熱膨張係数が2〜5×10−6/℃であ
る鉄−ニッケル合金、Fe-32〜42wt%Ni合金及びFe-30〜4
0wt%Ni−5〜20wt%Co合金のいずれかから成ることを特徴
とする高耐熱半導体素子。
15. The iron flange according to claim 1, wherein the metal flange has a coefficient of thermal expansion of 2 to 5 × 10 −6 / ° C., an Fe-32 to 42 wt% Ni alloy, and Fe-30 ~ 4
A high heat-resistant semiconductor device, characterized by comprising one of 0 wt% Ni-5 to 20 wt% Co alloy.
【請求項16】請求項1〜15のいずれかにおいて、前
記半導体チップの少なくとも一つが、外部からの制御信
号によって主電流を制御する主電流制御機能を有するこ
とを特徴とする高耐熱半導体素子。
16. A high heat resistant semiconductor element according to claim 1, wherein at least one of the semiconductor chips has a main current control function of controlling a main current by a control signal from the outside.
【請求項17】請求項1〜15のいずれかにおいて、前
記複数個の半導体チップが、ダイオードであることを特
徴とする高耐熱半導体素子。
17. The high heat resistant semiconductor element according to claim 1, wherein the plurality of semiconductor chips are diodes.
【請求項18】請求項1〜17のいずれかにおいて、前
記半導体チップがSiC、GaN又はダイヤモンドであること
を特徴とする高耐熱半導体素子。
18. A high heat-resistant semiconductor element according to claim 1, wherein the semiconductor chip is SiC, GaN or diamond.
【請求項19】主変換素子が、請求項1〜18のいずれ
かに記載の高耐熱半導体素子から成ることを特徴とする
電力変換器。
19. A power converter characterized in that the main conversion element comprises the high heat-resistant semiconductor element according to any one of claims 1 to 18.
JP2002113245A 2002-04-16 2002-04-16 High heat resistant semiconductor element and power converter using the same Expired - Fee Related JP3809550B2 (en)

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