JP2003297931A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To incorporate a large capacity capacitor into an SOI substrate. <P>SOLUTION: A depletion layer 12, which is formed in the interface on one side (near a silicon oxide film 2) of a silicon substrate 1, is used as a bypass capacitor CJVB. That is, one side (near the silicon oxide film 2) of the depletion layer 12 is electrically connected to a power supply line (not shown) via a high concentration impurity region 1a, a wire 10b, the drain (an impurity region 3b), channel region (an impurity region 3c), source (an impurity region 3a) of a transistor, and a wire 10a. The other side (far from the silicon oxide film 2) of the depletion layer 12 is electrically connected to a ground line via a high concentration impurity region 1b and a wire 10c. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a large capacity capacitor formed on a chip without using external parts.

[0002]

2. Description of the Related Art In a semiconductor circuit using SOI (Silicon on Insulator) technology, conventionally, when a capacitor is formed in a semiconductor chip, a two-layer polycapacitance in which a polysilicon layer and a metal layer are laminated and a gate are formed. A gate capacitance using an oxide film is used. And in such a case, the capacitor has the same layer as the MOS transistor,
That is, it is formed by utilizing the semiconductor layer on the buried oxide film and the wiring layer on the semiconductor layer.

[0003]

However, in the conventional capacitor structure as described above, a large area in the semiconductor layer on the buried oxide film of the SOI substrate or in the wiring area on the semiconductor layer is used as the capacitor. Since it is used for the purpose, even if an attempt is made to make a large-capacity capacitor, it is naturally limited. For this reason, a capacitor such as a bypass capacitor that requires a large capacity has to be provided as an external component.

The present invention has been made by paying attention to the unsolved problems of the conventional techniques as described above.
In a semiconductor device having a substrate structure such as a structure, an object thereof is to provide a structure and a manufacturing method of a semiconductor device suitable for forming a large-capacity capacitor in a chip.

[0005]

To achieve the above object, the invention according to claim 1 provides a semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are laminated in this order on a semiconductor substrate, A depletion layer formed at the interface of the semiconductor substrate on the side of the buried oxide film was used as a capacitor.

In order to achieve the above object, the invention according to claim 2 is a semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are laminated in this order on a semiconductor substrate. The depletion layer formed at the interface on the embedded oxide film side was used as a bypass capacitor. In order to achieve the above object, the invention according to claim 3 is a semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are stacked in this order on a semiconductor substrate, wherein the buried oxide film of the semiconductor substrate is provided. The tip of the contact was inserted into each of both sides in the thickness direction of the depletion layer formed at the side interface, and the depletion layer was used as a capacitor through the contacts.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect of the invention, the tip of the contact formed of the impurity region of the opposite type to the semiconductor substrate has the buried oxide film of the depletion layer. And the tip of the contact made of an impurity region of the same type as the semiconductor substrate reaches the side of the depletion layer far from the buried oxide film. According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the tip of the contact on the side of the depletion layer far from the buried oxide film has an elongated shape in the depth direction. I did it.

In order to achieve the above object, the invention according to claim 6 is a semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are stacked in this order on a semiconductor substrate. The tip of the contact was inserted into the depletion layer formed on the interface on the buried oxide film side to the buried oxide film side, the semiconductor substrate was connected to the ground potential, and the depletion layer was used as a capacitor via the contact.

In order to achieve the above object, a method of manufacturing a semiconductor device according to a seventh aspect of the present invention comprises a step of forming a plurality of contact high-concentration impurity regions on a semiconductor substrate,
Forming a buried oxide film on the semiconductor substrate; forming a semiconductor layer on the buried oxide film; forming a contact hole leading to the high-concentration impurity region for contact; Burying the inside with a contact metal, the one high-concentration impurity region for contact is an impurity region of a type opposite to the semiconductor substrate, and the interface on the buried oxide film side of the semiconductor substrate. The depletion layer formed on the side closer to the buried oxide film, and the other high-concentration impurity region for contact is an impurity region of the same type as the semiconductor substrate, and the buried oxide film of the depletion layer is formed. It was made to form on the side far from.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the contact high concentration impurity region on the side far from the buried oxide film of the depletion layer has a depth. The shape was elongated in the direction. In order to achieve the above object, a method of manufacturing a semiconductor device according to a ninth aspect of the present invention is a method of forming a high concentration impurity region for contact on a semiconductor substrate, and forming a buried oxide film on the semiconductor substrate. A step, a step of forming a semiconductor layer on the buried oxide film, a step of forming a contact hole leading to the contact high-concentration impurity region,
Filling the inside of the contact hole with a metal for contact, the high-concentration impurity region for contact is an impurity region of a type opposite to that of the semiconductor substrate, and the high-impurity impurity region for contact on the buried oxide film side of the semiconductor substrate. The depletion layer formed at the interface is formed on the side close to the buried oxide film, and the semiconductor substrate is connected to the ground potential.

In the present invention, a semiconductor layer on a buried oxide film of an SOI substrate on which elements such as transistors are formed,
A structure in which a depletion layer formed at the interface of the buried oxide film side of the semiconductor substrate below the buried oxide film as a support substrate is used to form a capacitor, not on the uppermost surface of the SOI substrate on which wirings and the like are formed. Therefore, a large capacity capacitor is S
It can be easily created in the OI substrate.

Therefore, as in the invention according to claim 2,
It is particularly suitable to use as a bypass capacitor which requires a large capacity.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention,
The manufacturing process of the semiconductor device of the present embodiment will be described with reference to FIG. That is, as shown in FIG. 1A, a P-type silicon substrate 1 serving as a support substrate for an SOI substrate is prepared, and a high-concentration impurity region for contact (tip of contact) is provided on the surface portion of the silicon substrate 1. Is formed as an N-type high-concentration impurity region 1a, and a P-type high-concentration impurity region as a contact high-concentration impurity region (contact tip) is formed at a position slightly intruding from the surface of the silicon substrate 1 in the depth direction. Impurity region 1b is formed.

These high-concentration impurity regions 1a, 1b are formed by an ion implantation method using a resist pattern (not shown) formed by a known photolithography process, and the position in the depth direction depends on the energy at the time of ion implantation. adjust. Further, the high-concentration impurity region 1b formed in the deep portion gradually changes the energy at the time of ion implantation from the initial stage to the final stage so that it becomes elongated in the depth direction. The high-concentration impurity region 1b is formed at the same depth as the lower end of the depletion layer formed on the surface of the silicon substrate 1 later.

Next, as shown in FIG. 1B, on the silicon substrate 1, a silicon oxide film 2 as a buried oxide film, and
The silicon film 3 as a semiconductor layer is formed in this order. The silicon oxide film 2 and the silicon film 3 are similar to those in a normal SOI substrate, and a known method may be applied as a film forming method. In addition, as shown in FIG. 1B, the source of the transistor
The high-concentration N-type diffusion regions 3a and 3b to be the drain and the P-type diffusion region 3c to be the channel of the transistor are formed, and the gate oxide film 4 is formed on the surface of the silicon film 3. Although FIG. 1 shows only the N-type diffusion regions 3a and 3b and the P-type diffusion region 3c that form one transistor, in reality, the diffusion regions for transistors that form various circuits are shown. However, a large number are formed in the silicon film 3.

Next, as shown in FIG. 1C, etching is performed by using a resist pattern (not shown) formed by a known photolithography process to form a contact hole 5 reaching the high concentration impurity region 1a. , And the contact hole 6 reaching the high concentration impurity region 1b. Since the contact holes 5 and 6 have different depths, they are opened in another etching process. Further, the contact holes 7 and 8 which reach the N-type diffusion regions 3a and 3b to be the source region and the drain region of each transistor are also formed at this stage.
Since the contact holes 7 and 8 have different depths from the contact holes 5 and 6, they are also opened in another etching process.

Then, as shown in FIG. 1D, the wiring patterns 10a, 10b, 10c made of aluminum are formed by using a known photolithography process. At this time,
Aluminum, which is the metal forming the wiring, is also allowed to enter the contact holes 5 to 8. Further, a gate electrode 11 made of polysilicon is formed on the impurity region 3c which will be the channel region of the transistor.

Wiring 10 conducting to the high-concentration impurity region 1a
b is electrically connected to the N-type diffusion region 3b which is the drain of the transistor formed close to it. The N-type diffusion region 3a, which is the source of the transistor, is connected to a power supply line (not shown) via the wiring 10a. And
The wiring 10c that is electrically connected to the high concentration impurity region 1b is electrically connected to the ground line GND. After that, the entire surface of the substrate is covered with a protective oxide film or the like (not shown) to complete a chip.

With the structure of FIG. 1D, a depletion layer 12 is formed at the interface of the silicon substrate 1 on the silicon oxide film 2 side. The depletion layer 12 exists in the entire chip area immediately below the silicon oxide film 2. The upper boundary of the depletion layer 12 is the lower surface of the silicon oxide film 2, and the lower boundary is
It depends on the impurity concentration of the silicon substrate 1 and the silicon oxide film 2. However, in this embodiment, since the high-concentration impurity region 1b is elongated in the depth direction, the dimension of the depletion layer 12 in the thickness direction is slightly shifted in the depth direction due to the influence of reverse bias as described later. Even in this case, conduction can be secured between the high-concentration impurity region 1b and the side of the depletion layer 12 remote from the silicon oxide film 2.

Therefore, on the side of the depletion layer 12 close to the silicon oxide film 2, the high concentration impurity region 1a, the wiring 10b, the drain (impurity region 3b) of the transistor, the channel region (impurity region 3c), the source (impurity region 3a). And the wiring 10a to the power line (not shown), and the side of the depletion layer 12 away from the silicon oxide film 2 is connected to the ground line GND via the high-concentration impurity region 1b and the wiring 10c. When the channel is ON, the depletion layer 12 is reverse-biased between the power supply line and the ground line, so that the depletion layer 12 is equivalent to a capacitance as a circuit element. Moreover, since the depletion layer 12 extends over the entire chip, the capacity is large. Therefore, the depletion layer 12 functions as a large-capacity bypass capacitor C _JVB .

Although the entire depletion layer 12 has a large capacitance, the capacitance value that can be extracted to the outside through the wirings 10b and 10c is actually determined by the concentration and size of the high concentration impurity regions 1a and 1b. Therefore, in order to secure a large capacity as a bypass capacitor,
It is desirable to provide a plurality of configurations as shown in (d) in the chip and use the plurality of bypass capacitors C _JVB connected in parallel.

As described above, according to the configuration of this embodiment, a large-capacity bypass capacitor is formed in a chip without using a large area in the transistor formation region or the wiring formation region in the SOI substrate. Can be crowded.
Therefore, it is not necessary to provide a large-capacity capacitor with an external component, or the number of capacitors to be provided can be reduced, which can contribute to a reduction in the number of components. If the number of external parts is reduced, the number of pins provided on the chip can be reduced.

Even _if the capacitance of the bypass capacitor C _JVB formed by the depletion layer 12 is large, the capacitance C _JVD formed by the silicon oxide film 2 is connected in series, so The AC (high frequency) characteristics of the circuit formed in the upper part are hardly affected. In addition, in the first embodiment,
Although the case where the depletion layer 12 is used as a bypass capacitor has been described, the depletion layer 12 is not limited to this and can be used as a coupling capacitor, for example. In such a case, the wiring 10c can be used. The destination of conduction is not the ground GND but the signal input portion of a predetermined circuit (not shown).

FIG. 2 is a diagram showing a second embodiment of the present invention. The same components as those in the first embodiment are designated by the same reference numerals, and the duplicated description will be omitted. That is, in the present embodiment, the high-concentration impurity region 1b, the contact hole 6, and the wiring 10c, which are provided in the first embodiment, are omitted, and the silicon substrate 1 itself is grounded.
It is configured to be connected to D.

Also with this structure, the side of the depletion layer 12 close to the silicon oxide film 2 is electrically connected to a power source line (not shown) through the high concentration impurity region 1a, the wiring 10b, the impurity regions 3b, 3c, 3a and the wiring 10a. , The ground line G through the silicon substrate 1 on the side far from the silicon oxide film 2.
Since it is connected to ND, the depletion layer 12 functions as a large capacity bypass capacitor C _JVB . Therefore, it is possible to enjoy the same advantages as those of the first embodiment.

FIG. 3 is a diagram showing a third embodiment of the present invention. The same components as those in the first and second embodiments are designated by the same reference numerals, and the duplicated description will be omitted.
That is, in this embodiment, a plurality (only two are shown in the drawing) of capacitors C _JVB1 and C in the depletion layer 12.
_JVB2 is provided. These capacitors C _{JVB 1} and C _{JVB 2}
Is not a bypass capacitor but a general capacitor used in, for example, a filter circuit. However, it is limited to one in which one terminal of the capacitor is connected to the ground GND. The other terminals of the capacitors C _JVB1 and C _JVB2 are
It is connected to a connection portion of a predetermined circuit (not shown) via the wirings 10d and 10e.

The capacities of the capacitors C _JVB1 and C _JVB2 can be adjusted by the impurity concentration and size of the respective high concentration impurity regions 1a. In the case of producing a large capacitor also in the case of the present embodiment, a large number of capacitors as shown in FIG. 3 may be formed in a chip and connected in parallel as necessary to have a large capacitance. Also in this embodiment, similarly to the above-described embodiments, capacitors having various capacities can be built in a chip without using a transistor formation region or a wiring formation region in an SOI substrate. Therefore, it is not necessary to provide a large-capacity capacitor by using external parts, or the number provided is small
It can also contribute to the reduction of the number of parts.

In addition, according to the present embodiment, the capacitors required for each circuit can be formed immediately below the transistors forming the circuits, which has the advantage that the chip area can be reduced, and between the capacitors and the circuits. Since the wiring becomes shorter, the wiring capacitance can be reduced and the high frequency characteristics of the circuit can be expected to be improved. The N-type and P-type semiconductors shown in each of the above embodiments are examples, and the conductivity types may be reversed.

[0029]

As described above, according to the present invention,
Since the capacitor is built using the depletion layer formed directly below the buried oxide film of the SOI substrate, a large-capacity capacitor can be formed in the chip, and the number of external parts is reduced accordingly. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

[Explanation of symbols]

1 Silicon Substrate (Semiconductor Substrate) 1a High Concentration Impurity Region (Contact High Concentration Impurity Region) 1b High Concentration Impurity Region (Contact High Concentration Impurity Region) 2 Silicon Oxide Film (Buried Oxide Film) 3 Silicon Film (Semiconductor Film) 12 _Depletion layer GND Ground line (ground potential) C _JVB Bypass capacitors C _JVB1 , C _JVB2 capacitors

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H01L 27/12 (72) Inventor Atsushi Matsumoto 3-3-5 Yamato, Suwa City, Nagano Prefecture Seiko Epson Corporation F-term (reference) 5F038 AC03 AC10 AV06 EZ06 EZ20 5F048 AC04 AC10 BA16 BB05 BF16 BF17

Claims (9)

[Claims] 1. A semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are laminated in this order on a semiconductor substrate, wherein a depletion layer formed at an interface of the semiconductor substrate on the buried oxide film side is a capacitor. A semiconductor device characterized by being used as. 2. In a semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are stacked in this order on a semiconductor substrate, a depletion layer formed at an interface of the semiconductor substrate on the buried oxide film side is bypassed. A semiconductor device characterized by being used as a capacitor. 3. A semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are stacked in this order on a semiconductor substrate, wherein the thickness of a depletion layer formed at an interface of the semiconductor substrate on the buried oxide film side. A semiconductor device in which the tips of contacts are inserted into both sides in the depth direction, and the depletion layer is used as a capacitor through the contacts. 4. A tip of a contact made of an impurity region of an opposite type to the semiconductor substrate reaches the buried oxide film of the depletion layer, and a tip of a contact made of an impurity region of the same type as the semiconductor substrate is 4. The semiconductor device according to claim 3, wherein a depletion layer reaches a side far from the buried oxide film. 5. The semiconductor device according to claim 4, wherein a tip of the contact on a side of the depletion layer far from the buried oxide film has a shape elongated in the depth direction. 6. A semiconductor device having a substrate structure in which a buried oxide film and a semiconductor layer are stacked in this order on a semiconductor substrate, wherein a depletion layer formed at an interface of the semiconductor substrate on the buried oxide film side is included. A semiconductor device, wherein a tip of a contact is inserted into a buried oxide film side, the semiconductor substrate is connected to a ground potential, and the depletion layer is used as a capacitor through the contact. 7. A step of forming a plurality of high-concentration impurity regions for contacts on a semiconductor substrate, a step of forming a buried oxide film on the semiconductor substrate, and a step of forming a semiconductor layer on the buried oxide film. A step of forming a contact hole communicating with the contact high-concentration impurity region, and a step of filling the contact hole with a contact metal.
One of the contact high-concentration impurity regions is an impurity region of a reverse type to the semiconductor substrate, and the buried oxide of the depletion layer formed at the interface of the semiconductor substrate on the side of the buried oxide film. The other high-concentration impurity region for contact is formed on the side closer to the film, is the same type of impurity region as the semiconductor substrate, and is formed on the side of the depletion layer far from the buried oxide film. Manufacturing method of semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the contact high-concentration impurity region on the side of the depletion layer far from the buried oxide film has an elongated shape in the depth direction. 9. A step of forming a high-concentration impurity region for contact on a semiconductor substrate, a step of forming a buried oxide film on the semiconductor substrate, and a step of forming a semiconductor layer on the buried oxide film, A step of forming a contact hole communicating with the contact high-concentration impurity region; and a step of filling the contact hole with a contact metal, wherein the contact high-concentration impurity region is of a reverse type to the semiconductor substrate. The impurity region of the semiconductor substrate, the depletion layer formed at the interface of the semiconductor substrate on the side of the buried oxide film is formed on the side close to the buried oxide film, and the semiconductor substrate is connected to a ground potential. Of manufacturing a semiconductor device.