JP2003296187A - Memory access switching device, memory access switching method and ic chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory access switching device, a memory access switching method and an IC chip capable of sharing a substrate without using a socket between different designations, and realizing this without using a rewritable memory. <P>SOLUTION: A printer 1 has built therein a CPU 18, a ROM 19, a RAM 20, an EEPROM 21, an ASIC 22, and a drive circuit 23, which are mounted on a substrate 24. A plurality of control programs are stored in the ROM 19. A logic circuit for switching the access designation of the CPU 18 is built in the ASIC 22. When power is inputted to the printer 1, the CPU 18 sets a resister 37 in the ASIC 22 based on a data value written in the EEPROM 21, and the ASIC 22 switches the access designation of the CPU 18 according to this register value. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access switching device, a memory access switching method and an IC chip.

[0002]

2. Description of the Related Art A printer has a CPU, a ROM, a RAM, and an A.
A control device including an SIC, a drive circuit, and the like is provided, and the control device drives a recording head, a carriage motor, a paper feed motor, and the like to execute various processes such as a printing process and a maintenance process. A control program is stored in the ROM, and the CPU operates the printer by accessing the ROM and executing the control program when the power of the printer is turned on. The control program is uniquely determined according to the destination, and one control program is written in one ROM.

[0003]

By the way, a plurality of programs are required when there are many kinds of destinations even for the same product. At present, only one program can be written in one ROM, so R depending on the destination
Each OM was required, and each ROM had to be prepared. Also, CPU, ROM, RAM, ASI
A device such as C is mounted on a substrate, and in order to share the substrate among a plurality of types of ROMs, a method of mounting a socket on the substrate and retrofitting the ROM is used. However, when this method is used, there is a problem that the socket cost is required and the cost is increased accordingly.

Here, as a method of avoiding these problems, it is conceivable to adopt a rewritable memory such as an EEPROM or a flash ROM and write a program in this memory. If a rewritable memory is adopted, it is not necessary to prepare a ROM depending on the destination, and further, the substrate can be shared between different destinations without using a socket, which does not increase the cost. However, since this type of rewritable memory is expensive, it is difficult to apply this method to, for example, low-priced products.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a rewritable memory in which a substrate can be shared between different destinations without using a socket. It is an object to provide a memory access switching device, a memory access switching method, and an IC chip that can be realized without using them.

[0006]

In order to solve the above problems, in the invention according to claim 1, a storage means storing a plurality of programs, and the storage means can be accessed to execute the programs. And a switching means for switching the access destination of the control means to the storage means based on the selection information so that a predetermined program is selected from among the plurality of programs. .

According to the present invention, when the control means accesses the storage means, the switching means switches the access destination to the storage means, and the control means is the switching means among the plurality of programs stored in the storage means. Read and execute the program determined by the switching state. Therefore, since a plurality of programs are written in the storage means and a desired one of them can be executed by switching selection of the switching means,
Even if there are multiple destinations, it is only necessary to prepare one storage means. Therefore, the board having the storage means mounted on the board can be used among a plurality of destinations, and the board can be shared without using a socket. Further, since the board can be shared even if a non-rewritable memory is used as the storage means, even if the board is shared, the rewritable memory is not used.

According to a second aspect of the present invention, in the first aspect of the present invention, the plurality of programs are operation programs related to operations of a control device on which the control means is mounted.

According to the present invention, in addition to the operation of the invention described in claim 1, a plurality of operation programs are stored in the storage means, and a desired one of these operation programs can be switched by the switching means. Become.

According to a third aspect of the invention, in the first or second aspect of the invention, the switching means is interposed between the control means and the storage means, and the control means accesses the storage means. In this case, the gist is to switch the access destination of the control means to the storage means by changing the address designated by the control means to the address based on the selection information.

According to this invention, in addition to the operation of the invention described in claim 1 or 2, when the control means fetches the program from the storage means, it accesses the top address of the storage means. At this time, although the control means executes the access, the access destination is switched by the switching means in the process of sending the address signal to the storage means. Therefore, since the control means changes the access destination without being aware,
It is not necessary for the control means to execute a special program for switching.

In the invention described in claim 4, claims 1 to 3 are provided.
In the invention described in any one of the above, there is provided a second storage means in which a data value is stored as the selection information,
The control means sets a register based on the data value of the second storage means, and the switching means switches the access destination of the control means to the storage means based on the register.

According to this invention, in addition to the operation of the invention described in any one of claims 1 to 3, the control means is based on the data value stored in the second storage means. By setting the register, a desired program can be selected from the plurality of programs stored in the storage means.

In the invention described in claim 5, claims 1 to 3 are provided.
In the invention described in any one of the above, there is provided a signal output means for outputting a switch signal as the selection information to the control means, and the control means sets a register based on the switch signal from the signal output means. However, the gist of the switching means is to switch the access destination of the control means to the storage means based on the register.

According to the present invention, in addition to the function of the invention described in any one of claims 1 to 3, the control means outputs the switch signal from the signal output means, and the control means sets the register based on the switch signal. By setting, a desired program can be selected from the plurality of programs stored in the storage means.

According to the invention described in claim 6, claims 1 to 3 are provided.
In the invention described in any one of the above, there is provided a second signal output means for outputting a switch signal as the selection information to the switching means, and the switching means is a switch signal from the second signal output means. Based on the above, the gist is to switch the access destination of the control means to the storage means.

According to this invention, in addition to the operation of the invention described in any one of claims 1 to 3, the switching means is the second.
Since the switching state can be directly changed based on the switch signal from the signal output means, the switching of the switching means can be performed without intervention of the control means.

In a seventh aspect of the invention, a plurality of programs are stored in the storage means, and when the control means accesses the storage means and acquires the programs stored in the storage means, the plurality of the programs are stored. The gist is that the switching means switches the access destination of the control means to the storage means based on the selection information so that a predetermined program is selected from the programs.

According to the present invention, the same effect as that of the first aspect can be obtained. According to an eighth aspect of the present invention, an IC chip connected to a storage unit in which a plurality of programs are stored, controlled by a control unit, and accessible to the storage unit, the predetermined program among the plurality of programs. It is a gist to provide a switching means for switching the access destination of the control means to the storage means based on the selection information so that the selection will be made.

According to the present invention, substantially the same operation as the first aspect can be obtained.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which a memory access switching device, a memory access switching method, and an IC chip of the present invention are embodied in a printer is shown in FIG.
~ It demonstrates according to FIG.

FIG. 1 is a perspective view showing the internal structure of the printer 1. A printer 1 as a control device includes a printer body 2 inside, and a carriage 3 is provided in the printer body 2.
Is installed. The carriage 3 is attached to an endless timing belt 6 stretched by a drive pulley 4 and a driven pulley 5, and the timing belt 6 is driven by a carriage motor 7 as an actuator to be guided by a carriage shaft 8. Moves back and forth in the main scanning direction. A paper feed motor 9 is provided on the lower end side of the printer 1.
Is mounted, and the recording paper 10 is fed in the sub-scanning direction by driving the paper feed motor 9.

A recording head 11 is disposed on the lower surface of the carriage 3 facing the recording paper 10, and an ink cartridge 12 (in this example, for black ink) that supplies ink to the recording head 11 is provided above the carriage 3. 2 for color
Types) are detachably attached. Recording head 1
A plurality of nozzles (not shown) are formed in the nozzle 1, and ink is ejected from the nozzles toward the recording paper 10 at a predetermined timing when the printing process is executed.

At the home position (right end in FIG. 1) of the carriage 3, a cap 14 capable of sealing the nozzles of the recording head 11 is provided. The cap 14 has a mechanical mechanism that seals the recording head 11 by pushing up the cap 14 by the carriage 3 itself when the carriage 3 is located at the home position (HP).
That is, the recording head 11 is automatically capped when the carriage 3 is at the home position.

The cap 14 has a suction pump 1 for applying a negative pressure to the internal space of the cap 14 during the cleaning operation.
5 are connected via a pump tube 16. The suction pump 15 is connected to the paper feed motor 9 via a gear mechanism (not shown), and the paper feed mechanism and the pump mechanism are the same drive source. A wiping member 17 made of an elastic plate such as rubber is disposed between the print area of the recording head 11 and the home position, and the wiping member 17 is used by the wiping member 17 when the recording head 11 moves toward the print area.
The surface of No. 1 is wiped.

FIG. 2 is an electrical block diagram of the printer 1. The printer 1 includes a CPU 18 as a control unit, a ROM 19 and a RAM 20 as a storage unit, an EEPROM 21 as a second storage unit, an ASIC 22 as an IC chip,
A drive circuit 23 is built in, and these devices are mounted on a substrate 24. The CPU 18 is connected to the ROM 19, the RAM 20 and the ASIC 22 via a signal line (including a data bus and a control bus) 25, and the EEPROM via a signal line 26.
21 is connected. Here, although there are a plurality of signal lines 25 and 26, only one of each is shown in FIG.

The CPU 18 and the ASIC 22 are connected via a plurality (10 in this example) of address buses 27. Further, the ASIC 22 and the ROM 19 are connected via a plurality (10 in this example) of address buses 28, and these address buses 28 correspond to the address buses 27 on the upstream side. Here, in the ASIC 22, the terminal Z _a is connected to the terminal T a of the ROM 19 via the address bus 28 _a, and the terminal Z _b is connected to the terminal T _{b of} the ROM 19 via the address bus 28 _b . The drive circuit 23 is connected to the ASIC 22 via a signal line 29.

The CPU 18 is an address bus 27, an ASIC
22, an address signal is output to the ROM 19 via the address bus 28, a program (or data) corresponding to the address signal is acquired from the signal line 25, and the printer 1 is operated. Further, when print data is sent from the host computer (not shown) to the printer 1, the CPU 18
Causes the ASIC 22 to execute a printing process using the RAM 20 as a work area. At this time, the ASIC 22 drives the drive circuit 23 based on the control signal from the CPU 18 to operate the various motors 7 and 9 and the recording head 11 to execute the printing process.

FIG. 3 is a circuit diagram showing a logic circuit of the ASIC 22. The ASIC 22 has two logic circuits 30 and 31.
Is equipped with. Of these, the logic circuit 30 includes one OR circuit 32 and four AND circuits 33 to 36.
The circuits 33 to 36 have five input terminals and one output terminal. The output terminals of the AND circuits 33 to 36 are OR
It is connected to the input terminal of the circuit 32 and the output terminal of the OR circuit 32 is connected to the terminal Z _a . In addition, the ASIC 22 has a built-in register 37, which is a CPU
18 allows a 4-bit data value to be set.

In the AND circuit 33, one of the five input terminals is grounded, and one of the other input terminals is connected to the holding section R ₁ of the register 37. The AND circuit 33 inputs the output value from the holding unit R _{1 as} it is, and the AND circuit 34-
The output value of 36 is inverted by the NOT circuit 38 and input. In the AND circuit 34, one of the five input terminals is connected to the power supply, and one of the other input terminals is connected to the holding unit R ₂ of the register 37. The AND circuit 34 inputs the output value from the holding unit R _{2 as} it is, and the AND circuit 33,
The output values of 35 and 36 are inverted by the NOT circuit 39 and input.

The AND circuit 35 has one of five input terminals.
One is grounded and one of the other input terminals is connected to the holding portion R ₃ of the register 37. The AND circuit 35 has a holding unit R ₃
The output value from the AND circuit 33, 3 is input as it is.
The output values 4 and 36 are inverted by the NOT circuit 40 and input. AND circuit 36 is one of the five input terminals
One is connected to the power supply and one of the other input terminals is register 3
7 is connected to the holding portion R ₄ . The AND circuit 36 inputs the output value from the holding unit R _{4 as} it is, and outputs the AND circuit 3
The output values 3 to 35 are inverted by the NOT circuit 41 and input.

Further, one logic circuit 31 includes one OR circuit 42 and four AND circuits 43 to 46, and each AN
The D circuits 43 to 46 have five input terminals and one output terminal. The output terminals of the AND circuits 43 to 46 are O
It is connected to the input terminal of the R circuit 42 and the output terminal of the OR circuit 42 is connected to the terminal Z _b . The logic circuit 3
0 and 31 correspond to the switching means.

In the AND circuit 43, one of the five input terminals is grounded and one of the other input terminals is connected to the holding portion R ₁ of the register 37. The AND circuit 43 inputs the output value from the holding unit R _{1 as} it is, and the AND circuit 44 to
The output value of 46 is inverted by the NOT circuit 47 and input. In the AND circuit 44, one of the five input terminals is grounded and one of the other input terminals is connected to the holding unit R ₂ of the register 37. The AND circuit 44 inputs the output value from the holding unit R _{2 as} it is, and the AND circuit 43, 45, 4
6, the output value is inverted by the NOT circuit 48 and input.

The AND circuit 45 has one of five input terminals.
One is connected to the power supply and one of the other input terminals is register 3
7 is connected to the holding portion R ₃ . The AND circuit 45 inputs the output value from the holding unit R _{3 as} it is, and outputs it to the AND circuit 4
The output values of 3, 44, and 46 are inverted by the NOT circuit 49 and input. In the AND circuit 46, one of the five input terminals is connected to the power supply, and one of the other input terminals is connected to the holding unit R ₄ of the register 37. AND circuit 4
6 inputs the output value from the holding unit R _{4 as} it is, AND
The output values of the circuits 43 to 45 are inverted by the NOT circuit 50 and input.

FIG. 4 is a memory map of the ROM 19. ROM19 denotes a memory of read-only, the control program P _a between the storage area address 0000~FFFF
~ P _d are stored. Incidentally, since the program content of the control program for each even purchaser a same printer may be different situation, in the present example writes the each destination into four control program P _a to P _d in ROM 19. Therefore, for example, the control program P _a is A
Company, the control program P _b to P _d, respectively B company, C company, D
Become a company.

[0036] These control programs P _a to P _d is an operation program related to the operations of the printer 1. The operation program mentioned here is a program that controls the sequence of the printer 1 and does not include a display program that simply switches the display between Japanese and English. Also, ROM
4 is the top address of the 19 single control program P _a to P _d
A setting program P _X for selecting one of the above is stored.

Next, the operation of this embodiment will be described with reference to FIG. First, the destination of printer 1 is destination A
If it is, the EEPROM is used as the previous step as shown in FIG.
The data value of “1000” is written in 21. In this state, the printer 1 is powered on and the ROM 19
When the access to the
The setting program P _X is executed to read the EEPROM 21. Then, the CPU 18 sets the register 37 of the ASIC 22 to "1, 0, 0, 0" based on the data value of the EEPROM 21.
(= “R ₁ , R ₂ , R ₃ , R ₄ ”).

At this time, in the logic circuit 30 in the ASIC 22 shown in FIG. 3, all AND circuits 33 to 36 are inactive, and all the AND circuits 43 to 46 in the logic circuit 31 are also inactive. Then, as shown in FIG. 5, signals of L level (that is, “0”) are output from both terminals Z _a and Z _b . Therefore, the access destination of the CPU 18 is the head position of the control program P _a , and the CPU 18 reads the control program P _a as an execution program,
The control program P _a is executed to operate the printer 1.

On the other hand, when the destination is destination B
As shown in FIG. 5, "01
The data value of "00" is written. In this state
When the access to the ROM 19 is started, the CPU 18
ROM 19 setting program P _XTo execute EEPROM2
Based on the data value of 1, the register 37 of the ASIC 22
Set it to "0,1,0,0".

At this time, in the logic circuit 30 in the ASIC 22 shown in FIG. 3, only the AND circuit 34 is in the active state, and in the logic circuit 31, all the AND circuits 43 to 46 are in the inactive state. Then, as shown in FIG.
H-level signal from _a (i.e. "1") is, from the terminal Z _b L level signal is output. Therefore, the CPU 18
Access destination jumps from the end position of the setting program P _X to the start address of the control program P _b , and the CPU 1
8 reads and executes the control program P _b as an execution program.

The same applies when the destination is destination C or destination D. When the destination is destination C, "0010" is written in the EEPROM 21, and when the ROM 19 is accessed, the register 37 is set by the data value of the EEPROM 21. It is set to "0,0,1,0". And ASIC
22 terminal Z _a becomes L level, terminal Z _b becomes H level,
The access destination of the CPU 18 becomes the start address of the control program P _c , and the CPU 18 reads the control program P _c from the ROM 19 and executes it.

In the case of the destination D, "0001" is written in the EEPROM 21, and the register 37 is set to "0, 0, 0, 1" based on the data value of the EEPROM 21 when the ROM 19 is accessed. And ASIC
Both terminals Z _a and Zb of 22 become H level,
The access destination of 18 is the start address of the control program P _d , and the CPU 18 reads the control program P _d from the ROM 19 and executes it.

Therefore, four control programs P _{a to} P _d are stored in the ROM 19 and data of the control programs P _{a to} P _d is changed depending on the connection state of the logic circuits 30 and 31 of the ASIC 22 based on the data value of the EEPROM 21. The one according to the value is executed. Therefore, the data value according to the destination
By setting in the EEPROM 21, the desired control program in the ROM 19 can be processed as an execution program. Therefore, even if there are a plurality of destinations, only the ROM 19 is the memory to be mounted on the substrate 24. Thus, the substrate 24 can be shared.

[0044] Further, since the ROM19 carrying the plurality of programs P _a to P _d is used, the ROM19 substrate 2
4 is mounted by mounting. Therefore, even if the board 24 is shared, it is not necessary to use a socket, so that the cost is low because the socket is not used. Further, since the memory for storing the control programs P _{a to} P _d is the read-only ROM 19, the non-rewritable memory is cheaper than the rewritable memory, so the cost of the memory can be low. .

Therefore, the following effects can be obtained in the first embodiment. (1) a plurality of control programs into a single ROM 19 P _a ~
Since it becomes possible to store P _d , this ROM
Even if 19 is mounted without a socket, the board 24 can be shared among a plurality of destinations. Further, since the memory used for sharing the substrate 24 is the read-only ROM 19, the cost of the memory is low.

(2) Logic circuits 30 and 31 of the ASIC 22
The selection target in the ROM 19 selected by the printer 1 is
Since the operating program that controls the operation, it is possible to select the operation program corresponding to the destination destination among the plurality of control programs P _a to P _d.

(3) When the CPU 18 reads the ROM 19, the ASI interposed between the CPU 18 and the ROM 19
The access destination of the CPU 18 is switched by the logic circuits 30 and 31 in the C22. Therefore, the CPU 18 changes the address destination to the ROM 19 without being aware of it.
The CPU 18 does not have to execute a special program for changing the address destination.

[0048] (4) access destination switching to ROM19 the CPU18 may store the data values in the EEPROM 21, the control program based on the data value of the EEPROM 21 of the four control program P _a to P _d in ROM19 is It is executed by being selected. Therefore, R of the CPU 18
The access destination to the OM 19 can be switched by software.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. In this embodiment, the same components as those in the first embodiment are designated by the same reference numerals, detailed description thereof will be omitted, and only different portions will be described.

FIG. 6 is an electrical block diagram of the printer 1. Switches S ₁ and S ₂ as signal output means are connected in parallel to the CPU 18. First, when the destination of the printer 1 is the destination A, both the switches S ₁ and S ₂ are turned off as shown in FIG. 5, for example.
In this state, the printer 1 is powered on and the ROM
When the access to the CPU 19 is started, the CPU 18 stores the ROM
The setting program P _{X of} 19 is executed to execute the switches S ₁ and S _2.
Read the connection status of the ASIC, and based on this connection status
The register 37 of 22 is set to “ ₁ , 0, 0, 0” (= “R ₁ ,
R ₂ , R ₃ , R ₄ ").

At this time, the logic circuit 30 of the ASIC 22,
Depending on the energization state of 31, the signals of L level (that is, “0”) are output from both terminals Z _a and Z _b of the ASIC 22. Therefore, the access destination of the CPU 18 becomes the head position of the control program P _a, CPU 18 is a control program reads the P _a as an execution program executes the control program P _a for operating the printer 1.

When the destination is destination B, the switch S ₁ is turned off and the switch S ₂ is turned on as shown in FIG. ROM in this state
When the access to the CPU 19 is started, the CPU 18 stores the ROM
Execute the setting program P _{X of} 19 to switch S ₁ , S
Based on the connection state of ₂ , the register 37 of the ASIC 22 is set to "0, 1, 0, 0".

At this time, an H level signal (that is, "1") is output from the terminal Z _{a of} the ASIC 22 and an L level signal is output from the terminal Z _b . Thus, it jumps to the start address of the control program P _b from the address destination end position setting program P _X of CPU 18, CPU 18 performs reads the control program P _b as an execution program.

When the destination is destination C, the switch S ₁ is turned on and the switch S ₂ is turned off. When access to the ROM 19 is started in this state, the connection state of the switches S ₁ and S ₂ is started. Causes the register 37 to show "0,
0,1,0 ". At this time, ASIC22
An L level signal is output from the terminal Z _{a of the above,} and an H level signal is output from the terminal Z _b , the address destination of the CPU 18 becomes the head address of the control program P _c , and the CPU 18 outputs R
The control program P _c is read from the OM 19 and executed.

When the destination is destination D, both switches S ₁ and S ₂ are turned on, and in this state, RO
When the access to M19 is started, the switches S ₁ and S _{2 are}
The register 37 is set to "0, 0, 0, 1" depending on the connection state of. At this time, the terminals Z _a and Z _{b of the} ASIC 22 are
Both of them output H-level signals, and the address destination of the CPU 18 becomes the head address of the control program P _d , and the CPU 18 reads the control program P _d from the ROM 19 and executes it.

The second embodiment has the following effects in addition to the same effects as (1) to (3) described in the first embodiment. (5) Since the switching of the access destination of the CPU 18 to the ROM 19 is executed by the connection state of the switches S ₁ and S ₂ connected to the CPU 18, the access destination of the CPU 18 is changed by switching the switches S ₁ and S _2. You can switch.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS. In this embodiment, the same components as those in the first and second embodiments are designated by the same reference numerals, detailed description thereof will be omitted, and only different portions will be described.

FIG. 8 is a circuit diagram showing a logic circuit of the ASIC 22. The switches S _a , S _b , S _c , and S _d as the second signal output means are connected to one of the five input terminals of each of the AND circuits 33 to 36, respectively. In addition, one of the five input terminals of each of the AND circuits 43 to 46 has _a switch _Sa ,
S _b , S _c and S _d are connected. These switches S _a ~
S _d is formed as a separate component from the ASIC 22, and is mounted on the substrate 24.

First, when the destination of the printer 1 is the destination A, the switch Sa is turned on and the switches Sb to Sd are turned off as shown in FIG. 9, for example. In this state, the printer 1 is powered on and R
When access to the OM 19 is started, the AS shown in FIG.
In the logic circuit 30 in the IC 22, all the AND circuits 33 to 36 are inactive, and all the AND circuits 43 to 46 in the logic circuit 31 are also inactive.

Then, as shown in FIG. 5, signals of L level (that is, "0") are output from both terminals Z _a and Z _b . Therefore, the access destination of the CPU 18 becomes the head position of the control program P _a, CPU 18 is a control program reads the P _a as an execution program executes the control program P _a for operating the printer 1.

If the destination is destination B, then FIG.
The switch S _b is turned on and the switches S _a , S _c and S _d are turned off as shown in FIG. When access to the ROM 19 is started in this state, only the AND circuit 34 of the logic circuit 30 in the ASIC 22 shown in FIG.
All of to 46 are inactive.

Therefore, as shown in FIG.
An H level signal (that is, "1") is output from the terminal Za and an L level signal is output from the terminal Zb. Therefore, C
The access destination of the PU 18 jumps from the end position of the setting program P _X to the start address of the control program P _b ,
The CPU 18 reads the control program P _b as an execution program and executes it.

When the destination is destination C, FIG.
As shown in, switch Sc is turned on, and switch S
The a, Sc and Sd are turned off. When the access to the ROM 19 is started in this state, the switch S
L-level signal from the terminal Z _a of ASIC22 the connection state of a~Sd, H level signal is output from the terminal Z _b. Therefore, the address destination of the CPU 18 becomes the start address of the control program P _c , and the CPU 18 reads R
The control program P _c is read from the OM 19 and executed.

When the destination is destination D, FIG.
The switch S _d in the ON state as shown in, the switch S _a
Keep S _d off. ROM in this state
If access to 19 is started, the switch S _a to S _d terminal Z _a of ASIC22 the connection state, both H-level signal from the Z _b is output. Therefore, the CPU 18
Becomes the start address of the control program P _d , and the CPU 18 reads the control program P _d from the ROM 19.
Read and execute.

In addition to the same effects as (1) to (3) described in the first embodiment, the third embodiment has the following effects. (6) Since the switching of the access destination of the CPU 18 to the ROM 19 is executed by the connection state of the switches S _{a to} S _d connected to the ASIC 22, it is possible to control the CP without using the CPU 18.
The access destination of U18 can be changed.

The embodiment is not limited to the above, but may be modified into the following modes. (Modification 1) In each of the above embodiments, the logic circuit 30,
31 is not limited to be integrally formed with the ASIC 22. For example, as shown in FIG.
The switching circuit 61 including the register 37 and the register 37 may be provided as a separate component from the ASIC 22. In this case, the ROM of the CPU 18
Switching means for switching the access destination to 19 (switching circuit 6
1) can be handled separately from the ASIC 22.

(Modification 2) In each of the above embodiments, R
OM19 number of the control program stored in the is not limited to four of the control program P _a to P _d. That is, the number of control programs may be two, three, five or more, and may be freely set according to the specifications.

(Modification 3) In the second and third embodiments, the switches S ₁ and S ₂ and the switches S _{a to} S _d are manually switched on and off or soldered directly to the board 24. Either of the soldering methods for turning on by turning on may be used.

(Modification 4) In each of the above-described embodiments, the program is not limited to the operation program that controls the operation of the printer 1, but may be another program such as a display program.

(Modification 5) In the first and second embodiments, the register 37 is not limited to being provided in the ASIC 22, and may have a configuration in which a register (not shown) of the CPU 18 is set.

(Modification 6) In each of the above-described embodiments, the object of the present invention is not limited to the printer 1, and the present invention may be applied to equipment other than the printer. Further, the type of the printer to be adopted is not particularly limited, and the present invention may be applied to a plurality of types of printers such as an inkjet type and a laser type.

The technical ideas that can be understood from the above-described embodiment and other examples will be described below along with their effects. (1) In claims 1 to 6, the switching means is interposed between the storage means and the control means, and an address signal output from the control means when the storage means of the control means is accessed is The address is changed by jumping to the address determined from the selection information, and the access destination of the control means to the storage means is switched.

(2) In Claims 1 to 3, a second storage means in which a data value is stored as the selection information, and the storage value is set by the control means based on the data value in the second storage means. The switching means switches the access destination of the control means to the storage means based on the register. In this case, for example, the switching means and the register can be integrated.

(3) In claims 1 to 3, a signal output means for outputting a switch signal as the selection information to the control means, and a stored value by the control means based on the switch signal from the signal output means. A register to be set, and the switching means switches the access destination of the control means to the storage means based on the register. In this case, for example, the switching means and the register can be integrated.

(4) In claim 7, the plurality of programs are operation programs related to the operation of a control device on which the control means is mounted. (5) In claim 7 and the technical idea (4), the switching means is interposed between the control means and the storage means, and when the control means accesses the storage means, the control means. By changing the address specified by the address based on the selection information, the access destination of the control means to the storage means is switched.

(6) Claim 7, the technical idea (4),
In (5), the control means is connected to a second storage means in which a data value is stored as the selection information, and the control means sets a register based on the data value in the second storage means, The switching means switches the access destination of the control means to the storage means based on the register.

(7) Claim 7, the technical idea (4) to
In (6), a signal output means for outputting a switch signal as the selection information is connected to the control means, the control means sets a register based on the switch signal from the signal output means, and the switching means is The access destination of the control means to the storage means is switched based on the register.

(8) Claim 7, the technical idea (4) to
In (7), a second signal output means for outputting a switch signal as the selection information is connected to the switching means, and the switching means is configured to control the control means based on the switch signal from the second signal output means. The access destination to the storage means is switched.

(9) In claim 8, the plurality of programs are operation programs relating to the operation of a control device on which the control means is mounted. (10) In the technical idea (9), the control means is connected to a second storage means in which a data value is stored as the selection information, and the control means is the second storage means.
A register is set based on the data value of the storage means, and the switching means switches the access destination of the control means to the storage means based on the register.

(11) In the eighth aspect and the technical ideas (9) and (10), the control means is connected to a signal output means for outputting a switch signal as the selection information, and the control means controls the signal. A register is set based on the switch signal from the output means, and the switching means switches the access destination of the control means to the storage means based on the register.

(12) Claim 8, the technical idea (9)
In (11), a second signal output means for outputting a switch signal as the selection information is connected to the switching means, and the switching means is based on the switch signal from the second signal output means, and the control means is provided. The access destination of the storage means is switched.

[0082]

As described in detail above, according to the present invention, a plurality of programs are stored in the storage means and a desired program among these programs is selected by the switching means. The board can be shared without using a socket, and it can be realized without using a rewritable memory.

[Brief description of drawings]

FIG. 1 is a perspective view showing an internal configuration of a printer according to a first embodiment.

FIG. 2 is an electrical configuration diagram of the printer.

FIG. 3 is a circuit diagram showing a logic circuit of an ASIC.

FIG. 4 is a memory map of a ROM.

FIG. 5 is an explanatory diagram showing a relationship between a state of each device and an execution program.

FIG. 6 is an electrical configuration diagram of a printer according to a second embodiment.

FIG. 7 is an explanatory diagram showing a relationship between a state of each device and an execution program.

FIG. 8 is a circuit diagram showing a logic circuit of an ASIC according to the third embodiment.

FIG. 9 is an explanatory diagram showing the relationship between the state of each device and an execution program.

FIG. 10 is an electrical configuration diagram of a printer in another example.

[Explanation of symbols]

1 Printer 18 as a control device CPU 19 as a control means ROM 21 as a storage means EEPROM 22 as a second storage means ASIC 30 as an IC chip 30 Logic circuit constituting a switching means 31 Logic circuit constituting a switching means 37 register S _1, switch P _a as a switch S _a to S _d second signal output means as S ₂ signal output means to P _d program (operation program) as a control program for

Claims (8)

[Claims] 1. A storage unit storing a plurality of programs, a control unit capable of accessing the storage unit to execute the program, and a selection unit for selecting a predetermined program from the plurality of the programs. A memory access switching device comprising: switching means for switching an access destination of the control means to the storage means based on information. 2. The memory access switching device according to claim 1, wherein the plurality of programs are operation programs related to operations of a control device on which the control means is mounted. 3. The switching means is interposed between the control means and the storage means, and when the control means accesses the storage means, the address designated by the control means is an address based on the selection information. By changing to
3. The memory access switching device according to claim 1, wherein an access destination of the control means to the storage means is switched. 4. A second storage means in which a data value is stored as the selection information is provided, the control means sets a register based on the data value in the second storage means, and the switching means is the register. 4. The memory access switching device according to claim 1, wherein an access destination of the control means to the storage means is switched based on the above. 5. A signal output means for outputting a switch signal as said selection information to said control means, said control means sets a register based on the switch signal from said signal output means, and said switching means 4. The memory access switching device according to claim 1, wherein an access destination of the control means to the storage means is switched based on a register. 6. A second signal output means for outputting a switch signal as the selection information to the switching means, the switching means being based on the switch signal from the second signal output means, the control means of the control means. 4. The memory access switching device according to claim 1, wherein an access destination to the storage means is switched. 7. The storage means stores a plurality of programs, and when the control means accesses the storage means and acquires the program stored in the storage means, a predetermined program among the plurality of programs is stored. A memory access switching method, wherein the switching means switches the access destination of the control means to the storage means so as to be selected. 8. An IC chip which is connected to a storage means in which a plurality of programs are stored and which is controlled by a control means and can access the storage means, wherein a predetermined program is selected from the plurality of the programs. As described above, the IC chip is provided with the switching means for switching the access destination of the control means to the storage means based on the selection information.