JP2003288204A - Arithmetic processing unit, method of constructing it, and method of arithmetic processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To operate an assembly of registers like RAMs when the functions of a CPU, RAMs, ROMs and the like are assembled onto one chip, while also making these functional components occupy less substrate area than if they are separately positioned on substrates. <P>SOLUTION: This arithmetic processing unit includes a register array 11 having a plurality of registers for retaining certain values according to a write address Aw and a write control signal Sw and outputting the values according to a read address Ar; an ALU 12 for computing the values; a decoder 13 for decoding arithmetic instructions from an arithmetic program AP intended for operating the ALU 12; and an instruction execution control part 50 which controls the register array 11 and the ALU 12 to execute the arithmetic instructions. The instruction execution control part 50 executes a register-to- register addressing process for selecting one register according to the arithmetic instructions and selecting the other register according to the value retained by the one register. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit suitable for application to a programmable one-chip microcomputer or the like that can be incorporated in various electronic devices, a construction method thereof, and an arithmetic processing method.

More specifically, a register array for executing an operation instruction and an instruction execution control section for controlling the operation section are provided, and one register is selected based on the operation instruction, and another value is held by the other register. Performs register-relative register addressing to select registers, allowing the register array to operate like a memory that can write and read data at any time.
The board occupying area can be reduced as compared with the case where the CPU, the RAM, the ROM and the like are individually arranged on the board.

[0003]

2. Description of the Related Art In recent years, a microprocessor including a central processing unit (CPU) is often used in various electronic devices such as portable terminal devices, electronic cards, and information processing devices. When an attempt is made to access a storage device with this type of processor, different access methods are used depending on whether the access destination is a register or an external memory.

When the access destination is a register, for example, a copy register, a temporary register, etc. are arranged around an ALU (Arithmetic Logic Unit), and when the arithmetic processing is performed, the data is copied to the copy register. Alternatively, the processed data is temporarily stored in the temporary register. This is because the ALU is suitable for register-to-register arithmetic processing.

When the access destination is an external memory, for example, when information is written to the address of the external memory indicated by the register number, the CPU writes to the external memory a write address that specifies the storage address and a write address. And output signals. When reading information from the address of the external memory indicated by the register number, the CPU outputs a read address designating the storage address and a read signal to the external memory.

In this way, when storing information in the address of the external memory indicated by the register number or reading information from the address of the external memory indicated by the register number, the CPU
Specifies the storage address (write address or read address) of the external memory. Such processing is often called register-relative memory addressing. This is because the external memory is usually implemented in a device different from the processor.

[0007]

By the way, according to the conventional processing unit, the processing speed is lowered due to the following two reasons.

That is, it takes access time to access the external memory. In general, a storage device is rarely made specifically for a specific processor, so that the processor side must prepare an interface according to the storage device to be accessed. Therefore, each time the storage device is accessed, it goes through this interface, so that it takes access time and the processing speed decreases.

External memory to ALU, ALU
It takes time to transfer data from the memory to the external memory.
This is because the ALU generally corresponds to register-to-register arithmetic processing. Therefore, if there is data to be arithmetically operated on the external memory, the data is once copied from the external memory to the copy register, and then the ALU is copied from the copy register. Data is transferred to and arithmetic processing is performed (register-relative memory addressing). Therefore, it causes a decrease in the calculation processing speed.

When the functions of CPU, RAM, ROM, etc. are integrated into one chip to configure a one-chip microcomputer or the like, CP is formed on the same semiconductor chip.
A method of arranging U and arranging a RAM, a ROM, and the like on the periphery thereof can be considered. This method depends on the register-relative memory addressing process, and cannot expect an improvement in the operation processing speed.

Therefore, the present invention has solved such a conventional problem, and when the functions of the CPU, RAM, ROM and the like are integrated into one chip, the aggregate of registers is written with data at any time. And an arithmetic processing unit capable of operating like a readable memory and capable of reducing the board occupying area as compared with the case where these functional components are individually arranged on the substrate, its construction method and arithmetic processing The purpose is to provide a method.

[0012]

SUMMARY OF THE INVENTION The above-mentioned problem is an apparatus for performing arithmetic processing based on an arbitrary arithmetic program, which holds an arbitrary value based on a write address and a write control signal, and a read address. A register array having a plurality of registers for outputting the value based on the above, an arithmetic unit for operating the value read from the register array, and an instruction for decoding an arithmetic instruction from an arithmetic program for operating the arithmetic unit The instruction execution control unit includes a decoding unit and an instruction execution control unit that controls the register array and the operation unit to execute the operation instruction decoded by the instruction decoding unit. The instruction execution control unit stores one register based on the operation instruction. Select and select another register according to the value held in the register selected here Performs register-relative register addressing It is solved by the processing unit, characterized in that.

According to the arithmetic processing apparatus of the present invention, when the arithmetic processing is performed based on an arbitrary arithmetic program, the instruction decoding section decodes the arithmetic instruction from the arithmetic program for operating the arithmetic section. The instruction execution control unit controls the register array and the arithmetic unit to execute the arithmetic instruction decoded by the instruction decoding unit. Assuming this,
The instruction execution control unit executes a register relative register addressing process of selecting one register based on the operation instruction and selecting another register according to the value held in the selected register.

Each register of the register array holds an arbitrary value based on the write address and the write control signal designated by the register relative register addressing process, and outputs the value based on the read address. It The arithmetic unit operates the value read from the register array.

Therefore, since the register array can be treated like a memory (RAM) in which data can be written and read at any time, a conventional central processing unit (C) can be used.
Compared to PU), it becomes independent of the register-relative memory addressing process that specifies the storage address of the external memory.

Since the functions of RAM and ROM can be incorporated in a conventional CPU, high-speed arithmetic processing can be performed, and in comparison with the case where the CPU, RAM, ROM, etc. are individually arranged on the substrate. The area occupied by the substrate can be reduced. The application device to which the arithmetic processing device is applied can be made compact.

The construction method of the arithmetic processing unit according to the present invention is as follows:
A method of constructing an apparatus for performing arithmetic processing based on an arbitrary arithmetic program, which comprises previously forming a plurality of memory cells and arithmetic logic operation elements on the same semiconductor chip and combining the memory cells to form a register array and a read-only memory. And an arithmetic unit, an instruction decoding unit, and an instruction execution control unit are defined by combining arithmetic logic operation elements, and then a register array, a read-only memory, an arithmetic unit, an instruction decoding unit, and an instruction execution control unit are preset. It is characterized in that wiring is performed on the basis of the wired information and an arbitrary arithmetic program is written in the read-only memory.

According to the method for constructing the arithmetic processing unit of the present invention, for example, the register array, the read-only memory, the arithmetic unit, and the instruction decoding unit are based on the wiring information read from the nonvolatile storage device when the power is turned on. Also, the instruction execution control unit is connected.

Therefore, the instruction execution control unit selects a register based on the operation instruction and selects the other register according to the value held in this register. The device can be built with power on.

Moreover, it is possible to construct an arithmetic processing unit in which the functions of RAM and ROM are incorporated in the CPU of the conventional system, and to execute high-speed arithmetic processing.
Alternatively, the area occupied by the substrate can be reduced as compared with the case where the RAM, the ROM and the like are individually arranged on the substrate. The application device to which the arithmetic processing device is applied can be made compact.

The arithmetic processing method according to the present invention is a method for performing arbitrary arithmetic processing based on an arithmetic program, which holds an arbitrary value based on a write address and a write control signal, and based on a read address. Prepare multiple registers that output the value, then decode the operation instruction from the operation program, select one register based on the operation instruction, and select another register according to the value held by the register selected here. The register-relative register addressing process is executed, and other registers are selected based on the operation instruction.The values held by the other registers selected here and the register values selected by the register-relative register addressing process are selected. It is characterized by being calculated.

According to the arithmetic processing method of the present invention, when arbitrary arithmetic processing is performed on the basis of an arithmetic program, a plurality of registers can be treated like a memory in which data can be written and read at any time. Compared to a conventional central processing unit and an external memory, a register-relative memory addressing process is not required. As a result, it becomes possible to execute high-speed arithmetic processing as compared with the conventional method.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of an arithmetic processing device, a construction method thereof and an arithmetic processing method according to the present invention will be described with reference to the drawings. (1) Embodiment FIG. 1 shows an arithmetic processing unit 10 as an embodiment according to the present invention.
It is a block diagram which shows the structural example of 0.

In this embodiment, a register array for executing an operation instruction and an instruction execution control section for controlling the operation section are provided, and one register is selected based on the operation instruction, and another value is held by the value held by this register. The register relative register addressing process for selecting the register is performed so that the register array can operate like a memory (RAM) in which data can be written and read at any time, and the CPU, RAM, ROM, etc. are individually The area occupied by the substrate can be reduced as compared with the case where the substrate is arranged on the substrate.

The arithmetic processing unit 100 shown in FIG. 1 is a processor suitable for application to a programmable one-chip microcomputer or the like, and performs arithmetic processing based on an arbitrary arithmetic program. In this example, the arithmetic processing unit 1
00 constitutes a programmable logic device,
A memory cell and an arithmetic logic operation element formed on the same semiconductor chip are connected based on wiring information, a register array 11 and a ROM cell 14 are constituted by a plurality of memory cells, and an ALU 12 is constituted by a plurality of arithmetic logic operation elements. The decoder 13 and the instruction execution control unit 50 are configured. The arithmetic processing unit 100 is connected to an external system bus or the like through the interface 60.

The arithmetic processing unit 100 includes a register array 11
have. The register array 11 has a plurality of registers, each register holds an arbitrary value based on the write address Aw and the write control signal Sw, and based on the read address Ar, the augend X or the addend Y is obtained. Is output. The register array 11 is provided with, for example, 8192 × 32-bit registers.

The register array 11 has an arithmetic and logic unit (arithmetic and log) as an example of an arithmetic unit.
ic Unit: ALU (hereinafter referred to as ALU) 12 is connected through a data signal line L20, and calculates values such as X and Y read from a register designated in the register array 11. The value of the calculation result is Z.
The calculation items are addition, multiplication, subtraction, and division.
The operation type is set based on the ALU control signal S35 output from the instruction execution control unit 50.

In addition to the ALU 12, the data signal line L20 includes latch circuits 58, 511 and selectors 56, 57, 59.
Etc. are connected. DAT for the data signal line L20
A, augend X value, addend Y value, etc. are transmitted.

The arithmetic processing unit 100 has an instruction decoding unit (hereinafter referred to as a decoder) for operating the ALU 12.
13 are provided. A read-only memory (ROM cell) 14 is connected to the decoder 13, and the ALU 12
An arithmetic program AP necessary for the arithmetic operation of is stored in a machine language instruction (Instruction). The ROM cell 14 outputs the arithmetic program AP based on the count output signal S5 from the program counter 54. R
The OM cell 14 is also mounted inside the processor.

The decoder 13 decodes the operation instruction from the operation program AP prepared in advance.
For example, the decoder 13 decodes a machine language instruction read from the ROM cell 14 to generate an instruction control signal S4, an instruction signal S9 and each argument signal S10.
The command signal S9 includes a load command, an add command, a cmp command, and a jump command. For each argument signal S10, access method # 1, access method # 2, register number r
0, r1, ..., etc., flag states (flag condi
section) and jump address. The instruction control signal S4 is output to the instruction read state machine 52.

The arithmetic program AP includes arithmetic instructions for executing register-relative register addressing processing. The register-relative register addressing process is a process of selecting one register based on an operation instruction and selecting another register according to the value held by the register selected here. This process is the access method #
Executed by 1.

An instruction execution control unit 50 is connected to the decoder 13, and the register array 11 and the ALU 12 for executing the operation instruction decoded by the decoder 13.
Is controlled. The instruction execution control unit 50 includes an execution state machine 51 and an instruction read state machine 5.
2, selector 53, program counter (PC) 54,
+1 incrementer 55, first selector 56, second selector 57, input selector 59, latch circuit 5
8, 510, 511, and performs register relative register addressing processing.

The instruction read state machine 52 controls the program counter 54 and the execution state machine 51 based on the instruction control signal S4 output from the decoder 13. For example, the machine 52 outputs the instruction signal S9 and each argument signal S10 from the decoder 13 to the execution state machine 51 and the instruction execution start signal S29.
Is output.

The execution state machine 51 has an ALU1
2, selectors 56, 57 and 59, latch circuits 58 and 51
0 and 511 are connected. The output of the selector 56 is connected to the register array 11 via the read address line L14, and its input is connected to the data signal line L20 and the address signal line L33, respectively. Read address A
This is for selecting either r or the read execution address Ar. The output of the selector 57 is the write address line L1.
3 is connected to the register array 11 with its input connected to the data signal line L20 and the address signal line L34. This is to select either the write address Aw or the write execution address Aw.

In the machine 51, the instruction execution start signal S
Based on 29, execution of the instruction is started. For example, when writing data, the write control signal Sw is output to the register array 11, and the selector 59 outputs the selection control signal S24.
Is output. When reading data, the selection control signal S
32 is output to the selector 56 and the read address Ar is output.

At the time of calculation, the latch control signal S34 is output to the latch circuit 58, and the latch control signal S38 is output to the latch circuit 510. An external control signal S16 is output to the outside of the processor. When the execution of the instruction is completed, the execution state machine 51 outputs the execution end signal S26 to the instruction read state machine 52 and advances the value of the program counter 54.

A selector 53 is connected to the execution state machine 51 and the instruction read state machine 52, and either the increment output signal S7 or the branch control signal S27 is selected based on the selection control signal S28, and this is selected. The output is made to the program counter 54 as a selector output. Selection control signal S28
Is supplied from the execution state machine 51. The increment output signal S7 is output from the incrementer 55 to the selector 53.

In the program counter 54, the location where the arithmetic program AP is read from the ROM cell 14 is designated based on the count control signal S30. The +1 incrementer 55 outputs the count output signal S of the program counter 54.
5 is incremented by "+1" to be incremented.
The count control signal S30 is the instruction decoding state machine 5
Supplied from 2.

In this example, the selector 56 connected to the execution state machine 51 selects either the read execution address Ar for selecting one register or the read address Ar for selecting the register again. Done The selector 56 is adapted to select either one of the addresses according to the selection control signal S32 from the execution state machine 51. The read execution address Ar is selected from the execution state machine 51 by the selector 57.
Is output to. The read address Ar is the register array 1
It is output from 1.

A selector 57 is connected to the execution state machine 51 in addition to the selector 56, and either the write execution address Aw for selecting one register or the write address Aw for selecting the register again is selected. Will be selected. The selector 57 is adapted to select either one of the addresses by the selection control signal S31 from the execution state machine 51.
The write execution address Aw is output from the execution state machine 51 to the selector 57. The write address Aw is output from the register array 11.

The selector 59 is connected to the data bus 19A, the register array 11 and the ALU 12, and the data (DATA) fetched from the data bus 19A, the augend X value (addend Y value) output from the register array 11 or Any one of the calculation result values Z output from the ALU 12 is input-controlled based on the selection control signal S24.

The latch circuit 58 is connected between the read port of the register array 11 and the ALU 12, and latches the output value X of the register ri based on the latch control signal S34. The latch circuit 510 is ALU1
The latch control signal S
Based on 38, the coincidence detection signal S22 is latched and a flag condition signal S23 is output. The latch circuit 511 is connected between the read port of the register array 11 and the address bus 19B, and latches an external address (address) based on the latch control signal S17.

When a jump (instruction branch) occurs due to the executed instruction, a branch control signal S27 indicating the address of the jump destination is output from the execution state machine 51 to the selector 53. The selector 53 selects the branch control signal S27 based on the selection control signal S28, and outputs the branch control signal S27 to the program counter 54.
It is made to write to. Further, the control bus 19C is connected to the execution state machine 51 to output the external control signal S16 to the outside. This is for controlling external peripheral devices.

FIG. 2 is a block diagram showing an internal configuration example of the register array 11. Register array 11 shown in FIG.
According to the above, for example, 8192 32-bit registers r0 to rn (i = 0 to n; 8191) are provided, and the write port 15 is connected to the input of each register r0 to rn. 1-bit register is a D-type flip
It is composed of a flop circuit and the like.

The write port 15 is connected to the selector 59 shown in FIG. 1. Based on the write control signal Sw and the write address Aw, the data (DATA) fetched from the data bus 19A and the register array 11 output the data. Either the augend X value (addend Y value) or the operation result value Z output from the ALU 12 is written in the registers r0 to rn. The write port 15 is connected to the selector 57 shown in FIG. 1 via the write address line L13. This is for supplying the write execution address Aw or the write address Aw.

A read port 16 is connected to the outputs of the registers r0 to rn. The read port 16 is connected to the ALU 12, the latch circuits 58, 511, the selectors 56, 57, 59 shown in FIG. 1 through the data signal line L20, and the data (DATA ) Is read out.

The read port 16 has a read address line L1.
4 is connected to the selector 56 shown in FIG. This is for supplying the read execution address Ar or the read address Ar. It is connected to the selector 57 shown in FIG. 1 through the write address line L13. This is for supplying the write execution address Aw or the write address Aw.

3A to 3E are formats and the like showing an example of the structure of an instruction handled by the arithmetic processing unit 100. According to the format shown in FIG. 3A, the instructions have a fixed length of 32 bits, and are roughly classified into load instructions, add instructions, and c.
It is handled by the mp instruction and the jump instruction. l
In the oad, add, and cmp instructions, the first 2 bits represent the type of instruction. There are four types of instructions as shown in FIG. 3C.

The instruction is l with code "0" in FIG. 3C.
od is a transfer instruction, code “1” is an add instruction, and code “2” is a cmp comparison instruction.
The code “3” is a jump and indicates a branch instruction. cm
If the comparison result is the same for the p instruction,
The zero flag is set to 1 based on the flag state signal S23 of the latch circuit 510 shown in (1), and 0 is set if they are not the same.

The access method # 1 is described in the 2 bits following the instruction shown in FIG. 3A, and the access method # 2 is described in the following 2 bits. The left side of the operand is represented by access method # 1 and register number 1, and the right side is represented by access method # 2 and register number 2. That is, the access method # 1 indicates the access method of the register ri indicated by the register number 1, and the access method # 2 indicates the access method of the register ri indicated by the register number 2. The access method # 1 and the access method # 2 are register number No. respectively. 1, register number No. 2 and processing is performed between them. In each case, four types of access methods are prepared as shown in FIG. 3D.

In FIG. 3D, the code "0" indicates that "register direct" directly uses the value of the register ri indicated by the register number. The code "1" indicates that the value of the register indicated by the register number in the "register relative register" is interpreted again as the register number and the value of the register indicated by the register number is used.

The code "2" indicates that the register value indicated by the register number in "register relative outside" is treated as an external address and the outside of the arithmetic processing unit 100 is accessed. Code "3" is unused. Access method # 1 and access method # 2 correspond to register number 1 and register number 2, respectively, and processing is performed between them. For example, the register number 1 indicates the register ri holding the augend, and the register number 2 indicates the register ri holding the addend.

Further, according to the format of the jump instruction shown in FIG. 3B, the instruction is described in the first 2 bits and the flag state (flag condition) is described in the following 2 bits.
on) is described. A jump address is described in the following 28 bits. The flag state is as shown in FIG. 3E.
This is a condition for determining whether to transfer the instruction execution control. Code "0" is "unconditional" and always transfers control. Code "1" is "zero flag" and is zero fl
If ag is "1", control is transferred. Code "2"
Is "non-zero flag"
When g is "0", the control is transferred. Code "3" is unused.

FIG. 4 shows the arithmetic program A of the ROM cell 14.
It is a table figure which shows the example of the arithmetic instruction by P. FIG. 5 is an image diagram showing a state example of the registers r0 to r12. In this example, 13 registers ri of the register array 11 are
Any one of (i = 0 to 12) is used to add "1" to the value stored in the register ri,
It is assumed that the calculation result is stored in an arbitrary register indicated by the value of i. Operation instruction #I shown in FIG.
1 to # I4 are described in the arithmetic program AP of the ROM cell 14.

In each of the operation instructions # I1 to # I4, a mnemonic expression, a machine language expression, and the contents of processing are shown. The operation instruction # I1 shown in FIG. 4 is 5001400 Bh in machine language in the instruction structure shown in FIG. 3A.
Represented by add [r10], r11,
The value of the register r11 of the register number indicated by r10 of the register array 11 is added to the value of the register r11 of the register number indicated by r10, and the result is stored in the register r10 of the register number indicated by r10. .

The operation instruction # I2 is 4001400 in machine language.
Add r10, r11 represented by Bh,
The contents of the register r11 are added to the value of the register r10 and the operation result is written back to the register r10. The operation instruction # I3 is cmp r10, r12 represented by 8001400Ch in the machine language, and the register r10
Is compared with the content of the register r12, and if the values are the same, the zero flag is set to "1", and if they are different, the content is set to "0". Instruction # I4
Is a jump represented by E000000Oh in machine language
It is p nz, LOOP, and when the zero flag is “0”, the control is transferred to the label indicated by LOOP.

According to the example of 13 register states of the register array 11 shown in FIG. 5, the initial values of the registers r0 to r10 are all "0", the initial value of the register r11 is "1", and the initial value of the register r12 is "1". The initial value is "10".

When the instruction # I1 shown in FIG. 4 is executed,
Since the value of the register r10 shown in FIG. 5 is "0", the register r0 is selected. The value “0” of the register r0 is read to the read port 16, the value “1” of the register r11 is subsequently read to the read port 16, these values are added, and the operation result is obtained. A certain "1" is stored in the register r0. As a result, the value of the register r0 is increased by "1". In this example, the addition process is repeated up to 10 times, which is the value of the register r12.

When the instruction # I2 shown in FIG. 4 is executed, the value "1" which is the value of the register r11 is added to the value "0" which is the value of the register r10 which is shown in FIG. Is stored in the register r10. This allows
The processing is moved to the next register.

When the instruction # I3 shown in FIG. 4 is executed,
The value of zero flag is held by the latch circuit 510 and is referred to by the subsequent instructions. On the premise of this, the value “0” of the register r10 is compared with the value “10” of the register r12. In this example, register r
Since the value “0” of 10 and the value “10” of the register r12 are different, “0” is set in the zero flag. "1" is set to the zero flag,
The value “10” in the register r10 and the value “1” in the register r12
This is the case where "0" matches.

When the instruction # I4 shown in FIG. 4 is executed,
Since the zero flag is "0", the control is transferred to the instruction # I1 (LOOP). When the above operation is repeated 10 times, the value of the register r10 becomes "10", and the register r1
Since the value “0” of 0 and the value “10” of the register r12 match, the zero flag is set to “1” by the instruction # I3, the control does not shift to the instruction # I1 by the instruction # I4, and the arithmetic processing is performed. finish.

(2) Arithmetic Processing Method Next, an example of the operation of the arithmetic processing device 100 will be described regarding the arithmetic processing method according to the present invention. FIG. 6 is a flowchart showing an operation example of the arithmetic processing unit 100 as the embodiment according to the present invention.

In this embodiment, it is assumed that the addition processing is executed based on the arithmetic program AP forming the arithmetic instructions # I1 to # I4 shown in FIG. Of course, in the case where the arithmetic processing unit 100 is prepared in advance with the register array 11 that holds an arbitrary value based on the write address Aw and the write control signal Sw and outputs the value based on the read address Ar. Assumption.

Regarding the register state of the register array 11, as shown in FIG. 5, for example, the initial values of the 13 registers r0 to r10 are all "0", and the initial value of the register r11 is "1". The initial value of the register r12 is “10”. When writing these initial values, the write address Aw is output to the address signal line L34 in the execution state machine 51, and the selector 57 outputs the register r10 and the register r1 based on the selection control signal S31.
By selecting 1 and the register r12, the initial values "0", "1", and "10" are set.

With this as an operating condition, in step A1 of the flowchart shown in FIG.
The arithmetic program (machine language instruction) AP is received from the M cell 14, the arithmetic program AP is decoded, and the arithmetic instruction # I1 is received.
~ # I4 is detected.

At this time, in the decoder 13, add indicated by the machine language 5001400Bh described in FIG. 4 is added.
[R10], operation instruction # I1 related to r11, and add r1 represented by 4001400Bh in machine language
Operation instruction # I2 related to 0 and r11, 80014 in machine language
Operation instruction # I3 relating to cmp r10, r12 represented by 00Ch, jump nz represented by E000000Oh in machine language, arithmetic instruction relating to LOOP #
I4 is detected, and from these operation instructions # I1 to # I4,
Command control signal S4, command signal S9 and each argument signal S10
Is generated and these signals S9 and S10 are output to the execution state machine 51.

The command signal S9 includes a load command, an add command, a cmp command, and a jump command. For each argument signal S10, access method # 1, access method # 2, register numbers r0, r1, ...
condition) and jump address. The instruction control signal S4 is output from the decoder 13 to the instruction read state machine 52.

Thereafter, in step A2, the execution state machine 51 receives the operation instruction # I1 under the instruction read control of the instruction read state machine 52 and receives 50014.
Add [r10], r11 indicated by 00Bh
One register r10 is selected based on At this time,
The register number "10" is output to the address signal line L33. The selector 56 uses the selection control signal S32 to select the address signal line L33. This allows
The register number "10" is output to the read address line L14. This value “10” is used as the address Ar for reading the register r10 having the register number 10 in the register array 11. Register r1 in register array 11
0 is selected. The value of the register r10 is “0”.

Then, in step A3, the register relative register addressing process is executed with the value "0" held by the register r10. At this time, the value "0" of the register r10 is output from the read port 16 to the data signal line L20. This is for selecting another register r0. As a result, the value “0” of the register r0 output from the register array 11 to the data signal line L20 is held by the latch circuit 58.

At the same time, the execution state machine 51 selects the data signal line L20 based on the selection control signal S32. As a result, the selector 56 outputs the value “0” of the register r10 to the read address line L14. Register r in register array 11
0 is selected.

Then, the process proceeds to step A4 to select another register r11 based on the operation instruction # I1. At this time, the execution state machine 51 selects the selection control signal S32.
Is output to the selector 56 so that the read execution address Ar is selected by the selector 56. At the same time, the value "11" is output to the address signal line L33 as the read execution address Ar. This value “11” is used as an address for reading the register r11 having the register number “11” in the register array 11. The value of the register r11 is "1".

As a result, the register r11 is selected based on the read address Ar. By this selection, the register r11 is transferred from the read port 16 to the data signal line L20.
The Y value, which is the output value of, is output as "1". By these operations, the Y value of the register r11 output to the data signal line L20 = “1” and the latch circuit 58.
The X value = “0”, which is the output of, is input to the ALU 12. That is, the X value of the register r0 designated by the value “0” held by the register r10 = “0” (the value of the register r0 selected by the register relative register addressing process) and the Y value of the register r11 = “1”. Is A
Input to LU12.

Then, in step A5, the Y value held in the register r11 = “1” and the X value of the register r0 selected by the register relative register addressing process =
"0" is added by the ALU 12. At this time, the arithmetic instruction signal S35 indicating the addition instruction is input to the ALU 12. As a result, the ALU12
Then, the Y value = “1” is added to the X = “0” value, and the addition result value Z = “1” is used as the calculation result signal S21.
9 is output.

Then, in step A6, 4001 in machine language
The operation result value Z is selected by the selector 59 based on the operation instruction # I2 represented by 400Bh. At this time, the selector 59 is set to select the operation result value Z by the selection control signal S24. Calculation result value Z
Are input to the register array 11. Register array 1
In 1, the operation result value Z is stored in the register r0 designated by the register relative register addressing process based on the write address Aw and the write control signal Sw.

That is, when the operation result value Z of the ALU 12 is written back to the register r0 designated by the register r10,
First, the execution state machine 51 uses the address signal line L3.
The value "10" is output to 3 as the write execution address Aw. At this time, the selection control signal S32 is output to the read selector 56 to select the address signal line L33.

Since the value "0" of the register r10 is output to the read port 16 of the register array 11, this time, the selection control signal S31 is output to the write selector 57 to output the data signal line 20. You will be asked to choose. By this selection, the value "0" for selecting the register r0 from the read port 16 of the register array 11 through the selector 57 is input to the register array 11 as the write address Aw.

Up to this point, the write address Aw and the contents to be written are input to the register array 11. afterwards,
The execution state machine 51 uses the write signal SW to actually instruct writing of a value. In this way, add [r10], r11 of the operation instruction # I1 can be operated.

In this example, in step A7 the register r1
It is determined whether the value indicated by 2 has reached 10 times. In the determination at this time, the value of the zero flag held in the latch circuit 510 is referred to based on the operation instruction # I3.
The value of the zero flag is compared with the value of the register r10 and the value "10" of the register r12, and if both values are different, "0" is set to the zero flag.

If both values match, zero fl
“1” is set in ag. Therefore, register r12
Value is less than 10 times, zero fl
Since "0" is set in ag, the operation instruction # I4
Then, the process returns to step A5 (LOOP) and the value "1" of the register r11 is read out to the read port 16.

This value "1" is repeatedly added so that the value of the register r0 is incremented by "1", and the operation results "1", "2", "3" ...
Is stored in the register r0. Thereby, the calculation result value Z can be stored in the register r0 based on the write address Aw and the write control signal Sw.

When the value indicated by the register r12 reaches 10 times in step A7, the value "10" of the register r10 and the value "10" of the register r12 match, so the instruction # I3 causes the zero flag to be changed. Since it is set to "1" and control is not transferred to the instruction # I1 by the instruction # I4, the arithmetic processing is completed without looping to the step A5.

As described above, according to the arithmetic processing apparatus and the arithmetic processing method as the embodiment of the present invention, the arithmetic instructions # I1 to # I4 etc. decoded by the decoder 13 in step A1 of the flowchart shown in FIG. Is the command signal S9
And each argument signal S10 becomes the execution state machine 5
It is output to 1. In the execution state machine 51, one register r10 is selected based on the operation instructions # I1 to # I4 in step A2, and the register relative register addressing process is executed by the value “0” held in the register r10 in step A3. It

When another register r0 is selected in step A4, the X value and the Y value are added by the ALU 12 in step A5, and the register r0 of the register array 11 writes the write address Aw specified by the register relative register addressing process. The operation result value Z is held based on the write control signal Sw, and the operation result value Z is output as the addend X value of the next operation based on the read address Ar in step A5. ALU1
2, the X value and Y read from the register array 11
The value is added.

Therefore, since the register array 11 can be treated like a memory (RAM) in which data can be written and read at any time, the registers r0 to r12, etc. can be treated like a RAM (memory) of a normal processor. It becomes possible to access the register array 11 (register).

As a result, as compared with the conventional central processing unit (CPU), the register-relative memory addressing process for designating the storage address of the external memory can be eliminated. Since the functions of RAM and ROM can be incorporated into the conventional CPU, high-speed arithmetic processing can be executed, and the board occupying area can be increased as compared with the case where the CPU, RAM, and ROM are individually arranged on the board. Can be reduced. The application device to which the arithmetic processing device 100 is applied can be made compact.

(3) Method for Constructing Arithmetic Processing Device FIG. 7 shows an arithmetic processing device 10 as an embodiment according to the present invention.
It is a top view which shows the construction example (the 1) of 0. In this embodiment, when the arithmetic processing unit 100 shown in FIG. 1 is constructed, a plurality of memory cells and arithmetic logic operation elements are formed in advance on the same semiconductor chip, and the memory cells are combined to form the register array 11 and the ROM cell. 14 is defined, and the ALU 12, the decoder 13 and the instruction execution control unit 50 are defined by combining arithmetic logic operation elements. Then, register array 11, ROM cell 24, ALU1
2, the decoder 13 and the instruction execution control unit 50 are connected based on preset wiring information, and the ROM cell 1
The above-mentioned arithmetic program AP is written in 4.

The arithmetic processing unit 100 shown in FIG. 7 is a programmable semiconductor device (PLD; Programmable Logic Device) in which a plurality of memory cells MSE and arithmetic logic operation elements LAY are previously formed on the same semiconductor chip. In the row direction of this semiconductor device, for example, N = 7 (i = 1, 2, i ... N) wiring patterns (hereinafter referred to as row wirings CO1 to CO7) are arranged.

Similarly, in the column direction, M = 7 lines (j = 1,
2, j ... M) wiring patterns (hereinafter column wiring RO1
~ RO7) is arranged. This row wiring CO1-C
Column wirings RO1 to RO7 arranged so as to be orthogonal to O7
The PLD has a lattice structure. A memory cell / arithmetic logic operation element block (hereinafter simply referred to as a cell block) having a plurality of memory cells MSE and arithmetic logic operation element LAY as one unit in each lattice.
SEij (i = 1 to 8, j = 1 to 8) is provided.

In this example, 8 × 8 = 64 cell blocks SE11 to SE88 are formed on the same semiconductor chip. A plurality of memory cells MSE are arranged in the upper half of one cell block SEij, and a plurality of arithmetic logic operation elements LAY are arranged in the lower half thereof. The register array 11 and the ROM cell 14 are cell blocks SEi.
It is assumed that the memory cells in j are combined and defined, and that the memory cells in other cell blocks SEij are also combined to define the register array 11 and the ROM cell 14.

I / O interfaces 60 to 63 are provided at both end sides of the row wirings CO1 to CO7 and both end sides of the column wirings RO1 to RO7, and the I / O interface 6 is provided.
One end side of the row wirings CO1 to CO7 is connected to 1, and the I / O interface 63 is connected to the other end side. The I / O interface 60 has column wirings RO1 to RO
One end side of 7 is connected, and the I / O interface 62 is connected to the other end side. The row wiring CO1 closest to the cell block SE11, the column wiring RO1 and the like are used for I
I / O interface 60 or I / O interface 63
It is possible to program the wiring. Of course, the other row wirings CO2-CO7 and the column wiring RO2-
It is possible to program the wiring in another cell block SEij1 using RO8 or the like.

The four I / O interfaces 60 to 63 are, for example, of the 64 cell blocks SEij in the grid,
Cell blocks SE11, SE12 forming the outer peripheral portion
..SE18, SE11, SE21 ... SE81, S
E81, SE82 ... SE88, and SE18, SE
28 ... It is arrange | positioned so that these may be surrounded along SE88.

Wiring between memory cells in each cell block SEij, between arithmetic logic operation elements, and cell block SE1
1 to SE88 wiring, column wiring R connecting between these
A plurality of switch elements (transistors) are arranged everywhere between the O1 to RO7 and the I / O interface, and by turning on the switch elements based on the wiring information, the circuit elements can be freely connected. There is.

At this stage, the register array 11,
The ALU 12, the decoder 13, the ROM cell 14, the instruction execution control unit 50, etc. are not defined, and form a versatile programmable logic device. In this example, when a programmable logic device is incorporated in an electronic device as a CPU, cell blocks SE11 to SE88 are assigned to the respective functional circuits, and column wirings RO1 to RO7, row wirings CO1 to CO7, etc. are provided between them. CP that matches the user's wishes by connecting and using the wires and freely programming the calculation functions required by the electronic device
The U function and the like are constructed.

FIG. 8 is a plan view showing a construction example (No. 2) of the arithmetic processing unit 100. In FIG. 8, on the semiconductor chip prepared in FIG. 7, the register array 11, the ALU 12, the decoder 13, and the R, which are surrounded by the broken line shown in FIG.
OM cell 14, execution state machine 51, instruction read state machine 52, selector 53, program counter 54, incrementer 55, selector 56, selector 57, input selector 59, latch circuits 58, 51.
The processor 100 is laid out by demarcating 0 and 511.

The execution state machine 51, the instruction read state machine 52, the selector 53, the program counter 54, the incrementer 55, the selector 56, the selector 57, the input selector 59, and the latch circuit 5 are included.
Reference numerals 8, 510 and 511 denote the instruction execution control unit 50 shown in FIG.
Make up.

In this example, the register array 11 has, for example, cell blocks SE1, SE14, SE23 and SE.
43 is allocated and configured. 8192 registers r0
To rn, these cell blocks SE1, SE14, S
The memory cells MSE of E23 and SE43 are used. The register array 11 allocates a memory cell MSE so as to hold an arbitrary value based on the write address Aw and the write control signal Sw and to have a plurality of registers r0 to rn that output the value based on the read address Ar. .

The write port 15 and the read port 16 shown in FIG. 2 have, for example, cell blocks SE1 and SE1.
4, it is preferable to use the input buffer circuit or the output buffer circuit of the arithmetic logic operation element LAY of SE23 and SE43. Column wirings RO1, RO2 and row wirings CO2, CO3, CO4 are used to connect the wirings between them.

The ALU 12 is constructed by allocating cell blocks SE26 and SE36. Cell block SE2
6 and SE36 using arithmetic logic element LAY
Build LU12. Column wiring RO is used for wiring between these.
1, RO2 and row wirings CO5 and CO6 are used for connection.

The decoder 13 is configured by allocating cell blocks SE54, SE64 and the like. Cell block SE
The decoder 13 is constructed using arithmetic logic operation elements LAY such as 54 and SE64. The wiring between them is connected by using the column wiring RO5 and the row wirings CO3, CO4 and the like.

The ROM cell 14 has a cell block SE52.
, SE62, etc. are allocated and configured. Cell block S
A read-only memory is constructed using memory cells MSE such as E52 and SE62. The write / read circuit of the arithmetic program AP is configured by using the input buffer circuit of the arithmetic logic operation element LAY and the output buffer circuit. The wiring between these is connected using the column wiring RO5 and the row wirings CO1 and CO2.

The execution state machine 51 includes cell blocks SE56, SE57, SE58, SE66 and SE67.
And SE68, etc. are allocated and configured. Column wiring RO5 and row wirings CO5, CO6, CO7 are provided between the wirings.
It is designed to be connected using a cable. The execution state machine 51 selects one register ri based on the operation instructions # I1 to # I4, and executes register relative register addressing processing for selecting another register according to the value held by the register ri selected here. Is.

The instruction read state machine 52 is configured by allocating cell blocks SE85 and SE86. The wiring between these is the column wiring RO7 and the row wiring CO.
4, CO5, CO6, etc. are used for connection. A cell block SE73 or the like is assigned to the selector 53 and the program counter 54. A column wiring RO7, a row wiring CO2, and the like are used for wiring to other circuits. The incrementer 55 is configured by allocating a cell block SE83 or the like. A column wiring RO7 and a row wiring CO2 are provided for wiring to other circuits.
The connection is made using CO3 or the like.

The selector 56 is configured by allocating a cell block SE33 or the like. The wirings to other circuits are connected by using row wirings CO3 and CO4. The selector 56 selects either the read execution address Ar for selecting one register or the read address Ar for selecting the register again.

A cell block SE34 or the like is assigned to the selector 57. Rows CO2, CO3, etc. are used to connect with other circuits. The selector 57 selects either the write execution address for selecting one register ri or the write address Aw for selecting the register again.

The input selector 59 has a cell block S
It is configured by allocating E12, SE22 and the like. The column wiring RO1 and the row wiring CO1 and the like are used to connect with other circuits. The latch circuit 58 is configured by allocating a cell block SE35 or the like. A column wiring RO2, a row wiring CO5, and the like are used for wiring to other circuits.

The latch circuit 510 includes a cell block SE3.
7 etc. are allocated and configured. The column wiring RO2 and the row wirings CO6 and CO7 are used to connect with other circuits. The latch circuit 511 is configured by allocating a cell block SE41 or the like. A column wiring RO3, a row wiring CO1, and the like are used for wiring to other circuits.

FIG. 9 is an image diagram showing an example (part 3) of construction of the arithmetic processing unit 100. In FIG. 9, the register array 11, ALU 12, decoder 13, ROM cell 14, execution state machine 51, instruction read state machine 52, selector 53, program counter 54, incrementer 55, and selector 5 defined in FIG.
6, the selector 57, the input selector 59, and the latch circuits 58, 510, and 511 are connected by wiring information to construct the arithmetic processing unit 100.

In this example, a programmable logic device for constructing the arithmetic processing unit 100 is attached to a printed wiring board of an electronic device, and a flash memory 70, which is an example of a rewritable nonvolatile storage device, is attached. .

In this flash memory 70, wiring between memory cells in each cell block SEij, wiring between arithmetic logic operation elements, wiring between cell blocks SE11 to SE88,
The wiring information for turning on the switch elements arranged everywhere such as between the column wirings RO1 to RO7 connecting these and the I / O interface is stored.

FIG. 10 is a table showing an example of wiring information by the flash memory 70. In the wiring information example shown in FIG. 10, the signal lines L1 to L3 for the wiring information D1 to D38 ...
8 and the like, the signals transmitted to the signal lines L1 to L38 or the uses of DATA or the like are shown. Wiring information D1
... D38 ... Are created in a circuit technology language and are prepared as a netlist (connection information). In this example, the wiring information D1 to D38 stored in the flash memory 70 ...
Is rewritten at any time according to the function of the arithmetic processing device 100.

The arithmetic program AP is the ROM cell 1
It is made to write in 4. Calculation program A in this example
P includes arithmetic instructions # I1 to # I4 for executing register-relative register addressing processing.
This calculation program AP is used as wiring information D1 to D38 ...
You may make it output to the decoder 13 by linking with. The flash memory 70 can also function as the ROM cell 14.

FIG. 11 is an image diagram showing an example of connection in the arithmetic processing unit 100. According to the connection example shown in FIG. 11, for example, the cell block SE22 and the cell block S
When connecting E66 with the signal line L24, the switching transistor T23 arranged between the cell block SE22 and the column wiring R03, the column wiring R03, and the row wiring C.
The transistor T63 arranged between O6 and the transistor T66 arranged between the row wiring CO6 and the cell block SE66 are used. Each transistor T2
Gate control is possible for 3, T63 and T66.

On this assumption, the wiring information D24 of the table shown in FIG. 11 is read from the flash memory 70 when the power is turned on. The wiring information D24 is set to the gates of the transistors T23, T63, and T66. As a result, each of the transistors T23, T63,
T66 turns on. These transistors T23 and T6
By turning on T3 and T66, the cell block SE22 and the column wiring R03, the column wiring R03 and the row wiring CO6, and the row wiring CO6 and the cell block SE66 are electrically connected, and the signal line L24 is connected. Can be built.

In this example, the cell block SE22 is assigned to the selector 59, the cell block SE66 is assigned to the execution state machine 51, and the signal line L24.
Is used when transmitting the selection control signal S24 of the selector 59.

In this way, the wiring information D1 to D38 ... Is set in the switching transistors arranged everywhere between the memory cells in each cell block SEij, and the wiring information D1 to D38 ... -Based on the above, the circuit elements are freely connected by the transistor. As a result, the register array 11, ALU 12, decoder 1
3, the ROM cell 14, the instruction execution control unit 50, etc. are connected. With this setting, the size of the arithmetic program AP stored in the ROM cell 14 can be reduced.

FIG. 12 is a circuit connection diagram showing a construction example (part 4) of the arithmetic processing unit 100. FIG. 12 shows a circuit diagram of the arithmetic processing unit 100 connected when the power is turned on. A plurality of signal lines and the like are described in the configuration diagram of the arithmetic processing unit 100 shown in FIG. The signal line described here is the wiring information D recorded in the flash memory 70.
1 to D38 and the like. Wiring information D1 to D3
8 and the like are prepared for each signal line.

In this example, the wiring information D3 shown in FIG.
By turning on the switching transistor as shown in FIG. 3, the signal line L3 is connected to the decoder 13 and the ROM cell 14
Connect. The arithmetic program AP is transmitted to the signal line L3. Similarly, the signal line L4 connects the decoder 13 and the instruction read state machine 52 based on the wiring information D4. The command control signal S4 is transmitted to the signal line L4.

The signal line L5 is RO based on the wiring information D5.
The M cell 14, the instruction read state machine 52 and the program counter 54 are connected. The count output signal S5 is transmitted to the signal line L5. Signal line L6 is wiring information D
6, the selector 53 and the program counter 54 are connected. Either the branch control signal S27 or the increment output signal S7 is transmitted to the signal line L6 as a selector output.

The signal line L7 connects the incrementer 55 and the selector 53 based on the wiring information D7. Signal line L
Increment output signal S7 is transmitted to 7. The signal line L9 and the signal line L10 connect the decoder 13 and the execution state machine 51 based on the wiring information D10. The command signal S9 is transmitted to the signal line L9, and each argument signal S10 is transmitted to the signal line L10.

The signal line L11 connects the data bus 19A to the input selector 59 based on the wiring information D11. Data (DATA) is transmitted to the signal line L11. The signal line L12 connects the register array 11 and the execution state machine 51 based on the wiring information D12.
The write control signal Sw is transmitted to the signal line L12.

The write address line L13 is the wiring information D13.
The register array 11 and the selector 57 are connected based on The write address Aw is assigned to the write address line L13.
Is transmitted. The read address line L14 is the wiring information D1.
4 to connect the register array 11 and the selector 56. The read address A is connected to the read address line L14.
r is transmitted.

The signal line L15 connects the latch circuit 511 and the address bus 19B based on the wiring information D15.
An external address is transmitted to the signal line L15. Signal line L
Reference numeral 16 connects the execution state machine 51 and the control bus 19C based on the wiring information D16. Signal line L
An external control signal S16 is transmitted to 16. Signal line L1
Reference numeral 7 connects the latch circuit 511 and the execution state machine 51 based on the wiring information D17. The latch control signal S17 is transmitted to the signal line L17.

The data signal line L20 is based on the wiring information D20, the register array 11, the ALU 12, the data bus 19A, the selector 57, the selectors 56 and 58.
And the selector 59 for input are connected. Data (DATA), X value, Y value and the like are transmitted to the data signal line L20.

The signal line L21 connects the ALU 12 and the input selector 59 based on the wiring information D21. The calculation result value Z is transmitted to the signal line L21. Signal line L22
Represents the ALU 12 and the latch circuit 5 based on the wiring information D22.
Connect with 10. The coincidence detection signal S2 is provided on the signal line L22.
2 is transmitted.

The signal line L23 connects the execution state machine 51 and the latch circuit 510 based on the wiring information D23. The flag state signal S23 is transmitted to the signal line L23. The signal line L24 connects the selector 59 for input and the execution state machine 51 based on the wiring information D24. The selection control signal S24 is transmitted to the signal line L24.

The signal line L25 connects the selector 59 for input and the register array 11 based on the wiring information D25. Data, the operation result value Z, the augend X value, and the like are transmitted to the signal line L25. The signal line L26 connects the execution state machine 51 and the instruction read state machine 52 based on the wiring information D26. The execution end signal S26 is transmitted to the signal line L26.

The signal line L27 connects the execution state machine 51 and the selector 53 based on the wiring information D27. The branch control signal S27 is transmitted to the signal line L27. The signal line L28 connects the execution state machine 51 and the selector 53 based on the wiring information D28. The selection control signal S28 is transmitted to the signal line L28.

The signal line L29 connects the instruction read state machine 52 and the execution state machine 51 based on the wiring information D29. The command execution start signal S29 is transmitted to the signal line L29. The signal line L30 is the wiring information D30.
The instruction read state machine 52 and the program counter 54 are connected based on the above. The count control signal S30 is transmitted to the signal line L30.

The signal line L31 connects the selector 57 and the execution state machine 51 based on the wiring information D31. The selection control signal S31 is transmitted to the signal line L31. The signal line L32 connects the selector 56 and the execution state machine 51 based on the wiring information D32. The selection control signal S32 is transmitted to the signal line L32.

The address signal line L33 connects the selector 56 and the execution state machine 51 based on the wiring information D33. The read address A is provided on the address signal line L33.
r is transmitted. The signal line L34 connects the latch circuit 58 and the execution state machine 51 based on the wiring information D34. The latch control signal S58 is transmitted to the signal line L34.

The signal line L35 connects the ALU 12 and the execution state machine 51 based on the wiring information D35.
The ALU control signal S35 is transmitted to the signal line L35.
The signal line L36 is connected to the latch circuit 5 based on the wiring information D36.
8 and the ALU 12 are connected. The X value "0" or the like is transmitted as a latch output to the signal line L36.

The address signal line L37 connects the selector 57 and the execution state machine 51 based on the wiring information D37. A write address A is supplied to the address signal line L37.
w is transmitted. The signal line L38 connects the execution state machine 51 and the latch circuit 510 based on the wiring information D38. The latch control signal S38 is transmitted to the signal line L38.

As described above, according to the method of constructing the arithmetic processing unit 100 as the embodiment according to the present invention, the wiring information D read from the flash memory 70 when the power is turned on.
1 to D38 ... and the like based on the register array 11, A
LU 12, decoder 13, ROM cell 14, execution state machine 51, instruction read state machine 52, selector 53, program counter 54, incrementer 55, selector 56, selector 57, input selector 59 and latch circuits 58, 510, 511. Is to be connected.

Therefore, in the execution state machine 51, one register r10 is selected based on the operation instructions # I1 to # I4, and another register r0 is selected by the value "0" held by the register r10. A programmable processor 100 for performing processing can be built with power on. It is possible to efficiently construct a processor including memory cells with one chip.

In the decoder 13 after construction, the operation instruction # I1 is sent from the operation program AP for operating the ALU 12.
~ # I4 is decoded, and the instruction execution control unit 50 controls the register array 11 and the ALU 12 to execute the operation commands # I1 to # I4 decoded by the decoder 13. In the ALU 12, the X value and Y value read from the register array 11 are calculated. The operation result value Z can be stored in the register r0 having the value "0" indicated by the register r10.

Further, since the instruction execution control unit 50 can handle all the portions having the memory function inside the PLD as registers, the operation speed is higher than that of the processor of the type in which the memory cells and the registers are distinguished and accessed. It will be possible. Moreover, the area occupied by the substrate can be reduced as compared with the case where the CPU, RAM, ROM, etc. are individually arranged on the substrate. An electronic device such as a mobile terminal device to which the arithmetic processing device 100 is applied can be made compact.

[0137]

As described above, according to the arithmetic processing unit of the present invention, the instruction execution control unit for controlling the register array and the arithmetic unit for executing the arithmetic instruction is provided. A register-relative register addressing process is performed in which one register is selected based on an arithmetic instruction, and another register is selected according to the value held in this register.

With this configuration, the register array can be treated like a memory in which data can be written and read at any time, and therefore register relative memory addressing for designating the storage address of the external memory as compared with the conventional central processing unit. It becomes independent of processing.

Since the functions of RAM and ROM can be incorporated in the CPU of the conventional system, high-speed arithmetic processing can be performed, and compared to the case where the CPU, RAM, ROM, etc. are individually arranged on the substrate. The area occupied by the substrate can be reduced. The application device to which the arithmetic processing device is applied can be made compact.

Moreover, a register array and a read-only memory are formed by memory cells on the same semiconductor chip,
By configuring the arithmetic unit, the instruction decoding unit, and the instruction execution control unit with arithmetic logic operation elements, the arithmetic processing device can be configured with a programmable logic device.

According to the method of constructing an arithmetic processing device according to the present invention, when constructing a device that performs arithmetic processing based on an arbitrary arithmetic program, a plurality of memory cells and arithmetic logic operation elements are previously formed on the same semiconductor chip. To form a register array and a read-only memory by combining these memory cells, and to define an arithmetic unit, an instruction decoding unit, and an instruction execution control unit by combining arithmetic logic operation elements, and then to form a register array and a read-only memory. The memory, arithmetic unit, instruction decoding unit and instruction execution control unit are connected based on preset wiring information, and an arbitrary arithmetic program is written in the read-only memory.

With this configuration, the instruction execution control unit is programmable such that one register is selected based on the operation instruction and the other register is selected according to the value held by this register. An arithmetic processing unit can be constructed.

Moreover, it is possible to construct an arithmetic processing unit in which the functions of RAM and ROM are incorporated in the CPU of the conventional system, and to execute high-speed arithmetic processing.
Alternatively, the area occupied by the substrate can be reduced as compared with the case where the RAM, the ROM and the like are individually arranged on the substrate. The application device to which the arithmetic processing device is applied can be made compact.

According to the arithmetic processing method of the present invention, when arbitrary arithmetic processing is performed based on the arithmetic program, an arbitrary value is held based on the write address and the write control signal, and based on the read address. Prepare a plurality of registers to output the value in advance, then decode the operation instruction from the operation program, select one register based on this operation instruction, and select another register according to the value held by the register selected here. Performs register-relative register addressing to select a register, selects another register based on an arithmetic instruction, and holds the value held by the other register selected here and the register selected by the register-relative register addressing process. The values and are calculated.

With this configuration, a plurality of registers can be treated like a memory in which data can be written and read at any time, so that the register relative to the conventional central processing unit and the external memory can be compared. It becomes independent of the memory addressing process. As a result, it becomes possible to execute high-speed arithmetic processing as compared with the conventional method.

The present invention is extremely suitable when applied to a programmable one-chip microcomputer or the like that can be incorporated in various electronic devices.

[Brief description of drawings]

FIG. 1 is an arithmetic processing device 1 as an embodiment according to the present invention.
It is a block diagram which shows the structural example of 00.

FIG. 2 is a block diagram showing an internal configuration example of a register array 11.

3A to 3E are formats and the like showing a structural example of an instruction handled by the arithmetic processing unit 100. FIG.

FIG. 4 is a table showing an example of operation instructions by an operation program of a ROM cell 14.

FIG. 5 is an image diagram showing a state example of registers r0 to r12 and the like.

FIG. 6 is an arithmetic processing device 1 as an embodiment according to the present invention.
It is a flowchart which shows the operation example of 00.

FIG. 7 is an arithmetic processing device 1 as an embodiment according to the present invention.
It is a top view which shows the construction example (the 1) of 00.

FIG. 8 is a plan view showing a construction example (No. 2) of the arithmetic processing device 100.

9 is an image diagram showing a construction example (part 3) of the arithmetic processing apparatus 100. FIG.

10 is a table showing an example of wiring information by the flash memory 70. FIG.

11 is an image diagram showing a connection example in the arithmetic processing device 100. FIG.

FIG. 12 is a circuit connection diagram showing a construction example (part 4) of the arithmetic processing device 100.

[Explanation of symbols]

11 ... Register array, 12 ... ALU (arithmetic unit), 13 ... Decoder (instruction decoding unit), 14 ...
ROM cell (read-only memory cell), 50 ... Instruction execution control section, 51 ... Execution state machine (instruction execution control section), 52 ... Instruction decoding state machine (instruction execution control section), 53, 59 ... Selectors, 54 ...
・ Program counter, 55 ... Incrementer, 5
8, 510, 511 ... Latch circuit, 56 ... First
No. selector (instruction execution control unit), 57 ... Second selector (instruction execution control unit), 70 ... Flash memory (storage device), 100 ... Arithmetic processing device, r0 to rn
···register

Claims (16)

[Claims] 1. A device for performing arithmetic processing based on an arbitrary arithmetic program, the register holding an arbitrary value based on a write address and a write control signal, and outputting the value based on a read address. A register array having a plurality of units, an arithmetic unit for arithmetically operating a value read from the register array, an instruction decoding unit for decoding an arithmetic instruction from an arithmetic program for operating the arithmetic unit, and the instruction decoding unit. An instruction execution control unit that controls the register array and the arithmetic unit to execute the decoded arithmetic instruction, wherein the instruction execution control unit selects one of the registers based on the arithmetic instruction and is selected. Register relative register addressing processing for selecting another register according to the value held by the register That processing unit. 2. The arithmetic processing device according to claim 1, further comprising a read-only memory cell storing the arithmetic program. 3. The arithmetic processing device according to claim 1, wherein the arithmetic program includes an arithmetic instruction for executing the register relative register addressing processing. 4. The register array and the read-only memory are composed of a plurality of memory cells, the arithmetic unit, the instruction decoding unit and the instruction execution control unit are composed of a plurality of arithmetic logic operation elements, and the memory cell and arithmetic logic. The arithmetic processing device according to claim 1, wherein the arithmetic processing device is constituted by a programmable logic device provided on the same semiconductor chip. 5. The instruction execution control section includes a first selector that selects either a read execution address for selecting the one register or a read address for reselecting the register. The arithmetic processing unit according to claim 1, further comprising a second selector that selects either a write execution address for selecting one register or a write address for selecting the register again. . 6. A method of constructing an apparatus for performing arithmetic processing based on an arbitrary arithmetic program, comprising forming a plurality of memory cells and arithmetic logic operation elements in advance on the same semiconductor chip, and combining the memory cells. A register array and a read-only memory are defined, and an arithmetic unit, an instruction decoding unit, and an instruction execution control unit are defined by combining the arithmetic logic operation elements, and then the register array, the read-only memory, an arithmetic unit, and an instruction decoding unit. And a method for constructing an arithmetic processing device, characterized in that the instruction execution control unit is connected based on preset wiring information and an arbitrary arithmetic program is written in the read-only memory. 7. The method for constructing an arithmetic processing device according to claim 6, wherein the arithmetic program includes an arithmetic instruction for executing the register relative register addressing processing. 8. A rewritable non-volatile storage device for storing the wiring information is provided, the wiring information is read from the storage device when the power is turned on and set, and the register array is set based on the set wiring information. The method for constructing an arithmetic processing device according to claim 6, wherein the read-only memory, the arithmetic unit, the instruction decoding unit, and the instruction execution control unit are connected to each other. 9. The method for constructing an arithmetic processing device according to claim 6, wherein the wiring information stored in the storage device is rewritten at any time according to the function of the arithmetic processing device. 10. The register array has a plurality of registers for holding an arbitrary value based on a write address and a write control signal, and outputting the value based on a read address. 6. The method for constructing an arithmetic processing unit according to 6. 11. The instruction execution control unit executes a register relative register addressing process of selecting one of the registers based on the operation instruction and selecting another register according to a value held by the selected register. 7. The method for constructing an arithmetic processing device according to claim 6, wherein: 12. The instruction execution control unit includes a first selector that selects either a read execution address for selecting the one register or a read address for selecting the register again, The arithmetic processing according to claim 6, further comprising: a second selector that selects either a write execution address for selecting one register or a write address for selecting the register again. How to build a device. 13. The arithmetic unit operates the value read from the register array, the instruction decoding unit decodes an arithmetic instruction from an arithmetic program for operating the arithmetic unit, and the instruction execution control unit 7. The method according to claim 6, wherein the register array and the arithmetic unit are controlled to execute the arithmetic instruction decoded by the instruction decoding unit. 14. A method for performing an arbitrary arithmetic process based on an arithmetic program, which holds an arbitrary value based on a write address and a write control signal and outputs the value based on a read address. A plurality of registers are prepared in advance, then an arithmetic instruction is decoded from the arithmetic program, one of the registers is selected based on the arithmetic instruction, and another register is selected according to the value held by the selected register. The register addressing process is executed, the other register is selected based on the operation instruction, and the value held by the other selected register and the value of the register selected by the register relative register addressing process are calculated. An arithmetic processing method characterized by: 15. The operation processing method according to claim 14, wherein the result of the operation is stored in a register selected by a value held by the register. 16. The arithmetic processing method according to claim 14, wherein the arithmetic program includes an arithmetic instruction for executing the register relative register addressing processing.