JP2003283329A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the leak current in MOS transistors used for a logic evaluator in a logic circuit and suppress the rise of a noise voltage to expand the operation margin. <P>SOLUTION: A synchronous logic circuit comprises: a pMOS transistor M1 connected between a power source terminal Vdd and a first node N1 with a clock signal CLK inputted to its gate; an nMOS transistor M2 connected between a ground terminal Vss and a second node N2 with the clock signal CLK inputted to its gate; and a logic evaluator 10 composed of nMOS transistors M31, 32 connected in parallel between the nodes N1, N2 with input signals IN1, IN2 fed to the gates of both transistors. A pMOS transistor M4 is inserted between the bodies of the nMOS transistors M31, 32 with the Vss connected to its gate. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a logic circuit using a plurality of MOS transistors, and more particularly to a semiconductor integrated circuit having a synchronous logic circuit and a pass gate logic circuit.

[0002]

2. Description of the Related Art In recent years, a semiconductor layer (Silicon On Insulator: SOI) formed on a substrate via an insulating film has been used,
Attention has been paid to semiconductor integrated circuits in which various logic circuits are formed by forming MOS transistors in this SOI. SO
In the SOI-MOS transistor, which is a typical I element, the element formation region is separated from the substrate through an insulating film, so that the parasitic capacitance between the source and drain diffusion layers and the substrate is extremely small. As a result, the SOI-MOS transistor can perform high-speed switching operation.

In a semiconductor device using an SOI-MOS transistor, a neutral region (hereinafter referred to as a body) forming an element is separated for each element. Therefore, the body becomes electrically floating. In a semiconductor integrated circuit using such an element in which the body is in a floating state, the body voltage has various values depending on the operating state of the circuit.

For example, in the accumulation state in which the MOS transistor is cut off, there is a gate capacitance between the gate and the body via a gate insulating film, and therefore the body voltage changes due to capacitive coupling as the gate signal changes. . Further, since there is a junction capacitance due to a pn junction between the source and the body and between the drain and the body, the body voltage changes due to capacitive coupling as the source and drain signals change.

When the pn junction is reverse biased, a reverse leakage current flows, and when it is forward biased, a forward current flows, and these currents change the number of majority carriers stored in the body. The voltage changes. Furthermore, in a fine element, the majority carriers accumulated in the body increase due to the impact ionization current generated near the drain due to the majority carriers flowing from the source to the drain, and the body voltage changes. Further, in the fine element, the tunnel current flowing from the gate to the body through the thin gate insulating film increases the majority carriers accumulated in the body and changes the body voltage. In this way, SO
Since the floating body of the I-MOS transistor has various voltages, the pn junction between the body and the source may be in a strong forward bias state.

The SOI-MOS transistor has a source,
In addition to a field effect transistor composed of a gate and a drain, it has a parasitic bipolar transistor composed of a source, a body and a drain. It is known that when the pn junction between the body and the source is in a forward bias state as described above, the body effect of the field effect transistor lowers the threshold voltage. When the threshold voltage decreases, a leakage current called subthreshold leakage flows from the drain to the source in the MOS transistor in the cutoff state. In addition, when the pn junction between the body and the source is in a strong forward bias state exceeding 0.8 V, the parasitic bipolar transistor operates, and in this case as well, the leakage current flows from the drain to the source of the MOS transistor in the cutoff state. It comes to flow.

FIG. 7 shows a conventional example of a 2-input OR logic circuit composed of SOI-MOS transistors. M1 has a source connected to the first power supply (power supply potential) Vdd, a drain connected to the node N1, and a gate connected to the clock signal CLK.
PMOS transistor for precharge to which is input,
M2 is an nMOS transistor for preventing a through current at the time of precharge in which the source is connected to the second power supply (ground potential) Vss, the drain is connected to the node N2, and the clock signal CLK is input to the gate. M31 and M32 are nMOS transistors for evaluation, the drains of which are connected to the node N1 and the sources of which are connected to the node N2.
The input signal IN1 is input to the gate of 1, and the input signal IN2 is input to the gate of M32. INV1 is a CMOS inverter circuit for signal amplification whose input end is connected to the node N1 and whose output end is connected to the node OUT.

The operation of this circuit will be described with reference to the timing chart of FIG. In FIG. 8, the input signal IN2 is at the low level “L”, and the input signal IN is input during the precharge period.
FIG. 3 is a diagram schematically showing each node voltage when 1 changes from high level “H” to “L”, body voltages of nMOS transistors M31 and M32, and a current flowing through M32.

From time t0 to t2, the clock signal CL
K is "L" and the circuit is in the precharged state. That is, the pMOS transistor M1 is conductive, the nMOS transistor M2 is nonconductive, and the node N1 is at the power supply potential Vdd.
Will be precharged. As a result, the output node OUT becomes "L" by the inverter circuit INV1.

From time t0 to t1, the input signal IN1 is "H", the input signal IN2 is "L", the nMOS transistor M31 is conducting, and the M32 is non-conducting. Therefore, the node N2 is Vdd-Vth ( Vth is nMOS
The threshold voltage of the transistor). Therefore,
The drain voltage of the nMOS transistor M31 is Vdd, the gate voltage is Vdd, and the source voltage is Vdd-Vth. M3
The body voltage Vb1 of 1 is mainly Vd at the gate and drain.
It rises due to capacitive coupling when changing to d, and becomes almost Vdd. The drain voltage of the nMOS transistor M32 is Vdd, the gate voltage is the ground potential Vss, and the source voltage is Vdd.
It becomes dd-Vth. The body voltage Vb2 of M32 rises mainly due to capacitive coupling when the drain changes to Vdd, but is lower than Vb1 because there is no capacitive coupling with the gate.

Next, at time t1, the input signal IN1 is "H".
From "L" to "L", Vb2 does not change, but Vb1 becomes lower than Vb2 due to capacitive coupling between the gate and the body. Further, the voltage of the node N2 drops slightly due to capacitive coupling between the gate and the source.

Next, at time t2, the clock signal CLK changes to "H" and the circuit enters the logic evaluation state. At this time, since the input signals IN1 and IN2 are both "L", the nMOS transistors M31 and M32 remain non-conductive, and in the evaluation state, the pMOS transistor M1.
Becomes non-conductive, the node N1 becomes electrically floating. On the other hand, since the nMOS transistor M2 becomes conductive, the voltage of the node N2 drops to Vss. This node N
2, that is, Vb1 and Vb2 become higher than the source voltage due to the voltage change of the sources of the nMOS transistors M31 and 31, respectively, and the pn junction between the body and the source is in the forward bias state. From time t1 to t2, Vb2 is Vb1
Therefore, the forward bias of the pn junction in M32 is stronger than the forward bias of the pn junction in M31.
Over 0.8V.

In such a state, n
Parasitic bipolar current Ibip and subthreshold current Imo from drain to source of the MOS transistor M32.
A leakage current due to s occurs, and as a result, the voltage of the node N1 drops below Vdd. That is, the leakage current becomes a noise source, and the noise voltage ΔVN is generated at the node N1. ΔVN is an output node OU of the inverter circuit INV1
A noise voltage is generated in T. Also, ΔVN is Vdd-Vth_
When it becomes larger than logic (Vth_logic is the logical threshold voltage of the inverter circuit), the inverter circuit INV1 malfunctions and the output node OUT becomes “H” completely. That is,
Even though the input signals IN1 and IN2 are "L", the output becomes "H", and the circuit does not operate as OR logic and malfunctions.

[0014]

As described above, the conventional SO
The body of the I-MOS transistor is in an electrically floating state, and the logic circuit using the I-MOS transistor may have a body voltage higher than the source voltage by 0.8 V or more depending on the operating state. As a result, the leakage current increases due to the subthreshold leakage of the MOS transistor and the leakage current increases due to the operation of the parasitic bipolar transistor.
Noise voltage is generated inside the circuit and at the output of the circuit, and the operating margin is reduced. Further, when the noise voltage inside the circuit is large, the circuit malfunctions. Furthermore, the noise voltage of the output becomes a noise source of other circuits to which this output is input,
There is a problem that the operating margin of other circuits is reduced or malfunction occurs.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to reduce leakage current in a MOS transistor used in a logic evaluation section of a logic circuit and to prevent generation of noise voltage. An object of the present invention is to provide a semiconductor integrated circuit that can suppress the expansion of the operation margin.

[0016]

(Structure) In order to solve the above problems, the present invention adopts the following structure.

That is, the present invention is a semiconductor integrated circuit in which a synchronous logic circuit is composed of a plurality of MOS transistors,
Connected between a first power supply and a first node, a first conductivity type first MOS transistor having a gate to which a clock signal is input, and a second power supply and a second node And a second MOS transistor of the second conductivity type whose gate receives the clock signal, and the second node, which is connected between the first node and the second node and receives at least one input signal. A logic evaluation section, wherein the logic evaluation section is connected between the first node and the third node, and at least one of which receives the input signal at its gate.
Three second MOS transistors of the second conductivity type, a first conductivity type connected between the body of the third MOS transistor and the third node, and the gate of which is connected to the second power supply. A fourth MOS transistor, wherein the third node is directly connected to the second node or the fifth MOS transistor of the second conductivity type whose gate receives the input signal. It is characterized in that it is connected to two nodes.

Here, the following are preferred embodiments of the present invention. (1) Each MOS transistor is formed in a semiconductor layer on an insulating layer. The semiconductor layer should be Si.

(2) A plurality of third MOS transistors are connected in parallel, one fourth MOS transistor is provided, and each body of the third MOS transistor has a fourth MO transistor.
Must be commonly connected to one end of the S-transistor. (3) A plurality of third MOS transistors are connected in parallel,
A plurality of fourth MOS transistors are provided corresponding to the third MOS transistor, and a fourth MO transistor is provided between each body of the third MOS transistor and the third node.
The S transistor is connected.

(4) An inverter circuit having an input terminal connected to the first node and an output terminal connected to the fourth node. (5) A sixth MO of the first conductivity type, which is connected between the first power supply and the first node and whose gate is connected to the fourth node.
Including S transistor. (6) The first conductivity type is a p-channel, the second conductivity type is an n-channel, the first power supply is the power supply potential Vdd, and the second power supply is the ground potential Vss.

Further, the present invention is a semiconductor integrated circuit in which a pass gate logic circuit is composed of a plurality of MOS transistors, which is inserted between a first node and a second node which are input terminals of a first signal. And a latch circuit inserted between the second node and a third node serving as a signal output terminal, wherein the logic evaluation unit includes the first node and the second node. One or a plurality of evaluation MOSs, each of which is arranged between
A transistor and the evaluation MOS transistor,
A leakage current preventing MOS transistor connected between the body of the MOS transistor whose source is connected to the first node and the first node and having a constant voltage input to its gate. And

The following are preferred embodiments of the present invention. (1) Each MOS transistor is formed in a semiconductor layer on an insulating layer. The semiconductor layer should be Si. (2) The first power source has a power source potential Vdd, and the second power source has a ground potential Vss. (3) The evaluation MOS transistor is an n-channel, the leakage current prevention MOS transistor is a p-channel,
The voltage input to the gate of the leakage current prevention MOS transistor must be the ground potential Vss.

(Operation) According to the present invention, in the synchronous logic circuit using the MOS transistor controlled by the clock signal, the drain is provided at the first node which is in an electrically floating state in the logic evaluation state. A fourth MOS transistor of the first conductivity type whose gate is connected to the second power supply is inserted between the body and the source of the third MOS transistor of the second conductivity type which is connected to form the logic evaluation section. As a result, the body potential of the third MOS transistor can be lowered to near the second power supply voltage, and thus the leakage current in the third MOS transistor can be reduced.

Further, in a logic circuit using a pass gate logic using a MOS transistor and a latch circuit, a constant voltage is input to the gate between the body and the source of the evaluation MOS transistor forming the logic evaluation section. By inserting the current prevention MOS transistor, the body potential of the evaluation MOS transistor can be lowered to near a constant voltage (for example, Vss), and thus the leakage current in the evaluation MOS transistor can be reduced.

Therefore, M used in the logic evaluation section of the logic circuit
It is possible to reduce the leakage current in the OS transistor, suppress the generation of noise voltage, and increase the operation margin.

[0026]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a circuit configuration diagram showing a 2-input OR logic synchronous logic circuit according to the embodiment of FIG.

As the element forming substrate, an SOI substrate having a semiconductor layer formed on a semiconductor substrate with an insulating film interposed was used.
Specifically, a Si layer is formed on a Si substrate via a SiO ₂ film.

In the figure, M1 has its source connected to a first power supply (power supply potential) Vdd, its drain connected to a first node N1, and its gate connected to a clock signal CLK for inputting a precharge pMOS transistor ( The sources of the first MOS transistor) and M2 are the second power source (ground potential) V
An nMOS transistor (second transistor) for preventing a through current at the time of precharge in which the drain is connected to the second node N2 and the gate is supplied with the clock signal CLK.
MOS transistor).

The drains of M31 and M32 are the nodes N1.
Is an nMOS transistor (third MOS transistor) for logic evaluation, whose source is connected to the node N2, the input signal IN1 is input to the gate of M31, and the input signal IN2 is input to the gate of M32. Has been done. In addition, INV1 has an input end connected to the node N1 and an output end connected to the node OUT, and is a C for signal amplification.
It is a MOS inverter circuit.

The basic structure up to this point is the same as the conventional example shown in FIG. 7, but in the present embodiment, in addition to this, M
OS transistors M4 and M6 are provided.

M4 is a leakage current preventing pMOS transistor (fourth MOS transistor) having a drain connected to B1, a source connected to the node N2, and a gate to which the ground potential Vss is input. Where B1 is nMOS
This is a node in which the bodies of the transistors M31 and M32 are commonly connected.

M6 is a noise preventing pMOS transistor (sixth MOS transistor) having a source connected to the power supply Vdd, a gate connected to the output node OUT, and a drain connected to the node N1. The pMOS transistor M6 can be omitted if the noise at the node N1 is small, and even if the noise cannot be omitted, the pMOS transistor M1 should not reduce the operating speed of the circuit.
The driving capacity of M6 is set to 1/10 or less, and the driving capacity of M6 is set to be extremely small.

In the circuit of FIG. 1, when the evaluation state is entered from the precharge state, the node N1 is in an electrically floating state. At this time, noise on the node N1 causes a malfunction. Noise sources include crosstalk noise between wires, noise due to capacitive coupling when connected transistors operate, noise generated by off-leakage current of connected transistors, and charge distribution through connected transistors. Noise, etc. caused by the Of these, the noise generated by the off-leakage current corresponds to the problem in the present invention. The noise prevention pMOS transistor M6 prevents the potential of the node N1 from dropping due to these noises to some extent.

Next, a noise prevention pMOS transistor M
The operation of the logic circuit shown in FIG. 1 when 6 is omitted will be described with reference to the timing chart of FIG. In FIG. 2, the input signal IN2 is at the low level "L", each node voltage when the input signal IN1 changes from the high level "H" to "L" during the precharge period, the nMOS transistor M
It is the figure which represented typically the body voltage of 31 and M32, and the electric current which flows into these nMOS transistors M31 and 32.

From time t0 to t2, the clock signal CL
K is "L" and the circuit is in the precharged state. That is, the pMOS transistor M1 is conductive, the nMOS transistor M2 is nonconductive, and the node N1 is at the power supply potential Vdd.
Will be precharged. As a result, the output node OUT becomes "L" by the inverter circuit INV1.

From time t0 to t1, the input signal IN1 is "H", the input signal IN2 is "L", the nMOS transistor M31 is conductive, and the M32 is non-conductive, so that the node N2 becomes Vdd-Vth by M31. Be charged. Therefore, the drain voltage of M31 is Vdd and the gate voltage is Vd.
d, the source voltage is Vdd-Vth, the drain voltage of the nMOS transistor M32 is Vdd-Vth, the gate voltage is the ground potential Vss, and the source voltage is Vdd-Vth. Also, p
Since the MOS transistor M4 becomes conductive, the body voltage Vb of the nMOS transistors M31 and M32 becomes equal to the node N.
It becomes Vdd-Vth same as 2.

Next, at time t1, the input signal IN1 is "H".
Changes from "L" to "L", the voltage of the node N2 is nMOS.
The capacitance coupling between the gate and the source of the transistor M31 causes a slight decrease, and Vb also decreases accordingly.

Next, at time t2, the clock signal CLK changes to "H" and the circuit enters the logic evaluation state. At this time, since the input signals IN1 and IN2 are both "L", the nMOS transistors M31 and M32 remain non-conductive. Further, in the evaluation state, the pMOS transistor M1 becomes non-conductive, so that the node N1 becomes electrically floating.

On the other hand, since the nMOS transistor M2 becomes conductive, the voltage of the node N2 drops to the ground potential Vss.
At this time, the body voltage Vb of the nMOS transistors M31 and M32 starts to drop with the voltage change of the node N2. When the voltage of the node N2 becomes | Vthp | (Vthp is the threshold voltage of the pMOS transistor M4), M4 becomes non-conductive, so that Vb is kept at | Vthp |. | Vthp | is normally set to about 1/5 of the power supply potential Vdd. It can be seen from the comparison with FIG. 8 that Vb is much lower than Vb3.

That is, when Vdd is 1.5V, | Vthp | is about 0.3V, and when Vdd is 1V, | Vthp | is about 0.2V. Therefore, the nMOS transistor M
The pn junction between the body and the source of M31 and M32 is in a weak forward bias state, and the subthreshold current Imos.
And as a result of the parasitic bipolar current Ibip becoming smaller, the leakage current from the drain to the source hardly flows. As described above, since the noise voltage is not generated at the node N1, malfunction of the circuit can be prevented.

FIG. 3 is a diagram showing the power supply potential Vdd dependency of the leakage current in the nMOS transistors M31 and M32 and the noise voltage generated at the node N1 obtained by the numerical analysis. A broken line shows a conventional example, and a solid line shows this embodiment. From this figure, it can be seen that in the present embodiment, the leakage current is reduced by about one digit and the noise voltage is also significantly reduced.

(Second Embodiment) In the first embodiment, 2
Although the input OR logic circuit is used, the present invention is not limited to this and can be applied to various logic circuits. FIG. 4 shows an example of an n-input logic circuit as the second embodiment. Instead of the logic evaluation nMOS transistors M31 and M32, the logic evaluation unit 1
0 is connected between the nodes N1 and N2.

FIG. 5 shows an example of the configuration of the logic evaluation section 10.
In FIG. 5A, the drain is connected to the node N1, the source is connected to the node N2, the body is connected to B1,
A one-input logic evaluation section including an nMOS transistor M3 whose gate receives the input signal IN1 and a pMOS transistor M4 whose source is connected to B1 and whose drain is connected to the node N2 and whose ground potential Vss is applied. is there.

In FIG. 5B, an nMOS transistor M3 having a drain connected to the node N1, a source connected to a third node N3, a body connected to B1, and an input signal IN1 input to the gate, The source is connected to B1, the drain is connected to the node N3, the gate is applied with the ground potential Vss, and the pMOS transistor M4 is connected to the drain to the node N3. The source is connected to the node N2. The gate is connected to the input signal IN2. NMOS to which is input
This is a 2-input logic evaluation unit composed of a transistor (fifth MOS transistor) M5.

In FIG. 5C, the drain is connected to the node N1, the source is connected to the node N2, and the body is B1.
Connected to the gate and the input signal IN1 is input to the gate
The OS transistor M31 and the source are connected to B1,
The drain is connected to the node N2 and the gate is at the ground potential V
The pMOS transistor M41 to which ss is applied, the drain is connected to the node N1, the source is connected to the node N2, the body is connected to B2, and the input signal IN is input to the gate.
An nMOS transistor M32 to which 2 is input, a source connected to B2, a drain connected to a node N2,
This is a 2-input logic evaluation section composed of a pMOS transistor M42 to which the ground potential Vss is applied to the gate.

In FIG. 5D, the drain is connected to the node N1, the source is connected to the node N3, and the body is B1.
Connected to the gate and the input signal IN1 is input to the gate
The OS transistor M31, the drain is connected to the node N1, the source is connected to the node N3, and the body is B1.
Connected to the nM and the input signal IN2 is input to the gate
The OS transistor M32 and the source are connected to B1,
The drain is connected to the node N3 and the gate is at the ground potential V
The three-input logic evaluation section is composed of a pMOS transistor M4 to which ss is applied, an nMOS transistor M5 whose drain is connected to the node N3, whose source is connected to the node N2, and whose gate receives the input signal IN3.

In FIG. 5E, the drain is connected to the node N1, the source is connected to the node N3, and the body is B1.
Connected to the gate and the input signal IN1 is input to the gate
The OS transistor M31 and the source are connected to B3,
The drain is connected to the node N1 and the gate is at the ground potential V
The pMOS transistor M41 to which ss is applied, the drain is connected to the node N1, the source is connected to the node N3, the body is connected to B2, and the input signal IN is input to the gate.
An nMOS transistor M32 to which 2 is input, a source connected to B2, a drain connected to a node N3,
A three-input logic evaluation section including a pMOS transistor M42 having a gate applied with the ground potential Vss, an nMOS transistor M5 having a drain connected to the node N3, a source connected to the node N2, and an input signal IN3 input to the gate. Is.

The configuration of the logic evaluation section 10 is not limited to the example shown in FIG. 5, but may be any configuration in which at least one or more evaluation MOS transistors are connected in series and parallel. The evaluation MOS transistor forming the logic evaluation unit 10 is an nMOS.
Not only transistors but also pMOS transistors may be used, or nMOS transistors and pMOS transistors may be mixed. In the case of the evaluation pMOS transistor, a leakage current preventing nMOS transistor is used.
The leakage current prevention MOS transistor may be common to two or more evaluation MOS transistors, or may be separate for each evaluation transistor. MOS for leakage current prevention
A constant voltage other than the ground potential Vss may be used as the gate voltage of the transistor. Although the pMOS transistor is used as the precharge transistor in this embodiment, the present invention is not limited to this, and an nMOS transistor may be used as the precharge transistor.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
2 is a circuit configuration diagram showing a semiconductor integrated circuit including a pass gate logic and a latch circuit according to the embodiment of FIG.

The source of M71 is connected to the first node N11, and the drain is connected to the second node N12.
This is an nMOS transistor whose body is connected to B1 and whose gate receives the input signal INA, and this transistor constitutes pass gate logic. Here, the node N11
The input signal INB is input to the source connected to. M72 has a source connected to B1, a drain connected to a node N11, and a gate connected to the ground potential Vss.
Is a leakage current preventing pMOS transistor to which is applied. The input of INV2 is connected to the node N12,
C, whose output is connected to OUT which is the third node N13
The input terminal of the MOS inverter circuit, INV3 is the node OU
CM connected to T and the output end connected to node N12
This is an OS inverter circuit, and a latch circuit is formed by INV2 and INV3.

In this circuit, the node N12 is "H".
At Vdd, the output node OUT is at "L" and latched at Vss. When the input signal INA is "L", the input signal I
The body voltage of the nMOS transistor M71 when NB is "H" is Vb. At this time, since the pMOS transistor M72 becomes conductive, the body voltage Vb becomes the same potential as the source voltage. After that, when the input signal INB changes from “H” to “L”, Vb starts to drop together with the voltage change of INB. When INB becomes | Vthp |, M72 becomes non-conductive, so that Vb is kept at | Vthp |. Therefore, M
The pn junction between the body and the source of 71 is weakly forward-biased, and the subthreshold current and the parasitic bipolar current are reduced. As a result, almost no leakage current flows from the drain to the source.

As described above, in this embodiment, the node N12
Since no noise voltage is generated in the circuit, malfunction of the circuit can be prevented. On the other hand, when there is no M72, a strong forward bias state is established between the body and the source of M71, and M7
There is a risk that a leakage current due to a subthreshold current and a parasitic bipolar current will flow through the node 1, a noise voltage will be generated at the node N12, and the latch circuit will be inverted. That is, the present invention is effective even in a logic circuit including a pass gate logic and a latch circuit, and it is possible to prevent malfunction of the circuit.

The configuration of the pass gate logic is not limited to the example shown in FIG. 6, but at least one evaluation MOS is used.
Any configuration may be used as long as the transistors are connected in series and parallel. This MOS transistor may be a pMOS transistor as well as an nMOS transistor, or an nMOS transistor and a pMOS transistor may be mixed.
In case of pMOS transistor for evaluation, leakage current prevention n
Use MOS transistors. MOS for leakage current prevention
The transistors may be common to two or more evaluation MOS transistors, or may be separate for each evaluation transistor. A constant voltage other than the ground voltage Vss may be used as the gate voltage of the leakage current preventing MOS transistor.

In each of the above-mentioned embodiments, each M
Although the OS transistor is formed in the SOI layer, the present invention is not necessarily limited to the one formed in the SOI layer, and it is sufficient that the element formation region of each MOS transistor is electrically isolated. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0056]

As described above in detail, according to the present invention, the forward bias between the body and the source of the MOS transistor forming the logic evaluation section is reduced, the leakage current is reduced, and the generation of noise voltage is suppressed. To be As a result, in the synchronous logic circuit, the noise voltage generated at the output node is reduced, malfunction is prevented, and the operational margin of other circuits to which the output voltage of this circuit is input is greatly improved. Further, in the logic circuit in which the pass gate transistor and the latch circuit are combined, malfunction of the latch circuit can be prevented. Therefore, a high-performance semiconductor integrated circuit including a plurality of logic circuits can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a 2-input OR logic synchronous logic circuit according to a first embodiment.

FIG. 2 is a timing chart for explaining the operation of the synchronous logic circuit of FIG.

FIG. 3 is a diagram for explaining the effect of the first embodiment, showing the dependence of leakage current and noise voltage on a power supply voltage in a MOS transistor.

FIG. 4 is a circuit configuration diagram showing a synchronous logic circuit having an n-input logic evaluation section according to the second embodiment.

5 is a diagram showing a configuration example of a logic evaluation unit in FIG.

FIG. 6 is a circuit configuration diagram showing a logic circuit including a pass gate logic and a latch circuit according to a third embodiment.

FIG. 7 is a circuit configuration diagram showing a conventional synchronous logic circuit.

FIG. 8 is a timing chart for explaining the operation of the conventional synchronous logic circuit.

[Description of Codes] Vdd ... First power supply (power supply potential) Vss ... Second power supply (ground potential) CLK ... Clock signals Vb, Vb1, Vb2 ... Body voltage Vth, Vthp ... Threshold voltage ΔVN ... Noise voltage Ibip ... parasitic bipolar current Imos ... subthreshold currents IN1 to INn, INA, INB ... input signal OUT ... output nodes N1 to N3, N11 to N13 ... nodes B1 and B2 ... body node M1 ... precharge pMOS transistor (first M
OS transistor) M2 ... Through-current prevention nMOS transistor (second M
OS transistor) M3, M31, M32 ... Evaluation nMOS transistor (third MOS transistor) M4, M41, M42 ... Leakage current prevention pMOS transistor (fourth MOS transistor) M5 ... Evaluation nMOS transistor (fifth MOS) Transistor) M6 ... pMOS transistor for noise prevention (sixth MOS)
Transistor) M71 ... Pass gate logic nMOS transistor M72 ... Leakage current prevention pMOS transistors INV1 to INV3 ... Inverter circuit 10 ... Logic evaluation unit

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Claims (10)

[Claims] 1. A first conductivity type first MOS transistor connected between a first power supply and a first node and having a gate to which a clock signal is input, a second power supply and a second node. A second MOS transistor of a second conductivity type connected between the first node and the second node and having a gate to which the clock signal is input, and at least one input A logic evaluation section to which a signal is input, the logic evaluation section being connected between the first node and a third node, and having at least one second input terminal to which the input signal is input. A conductive type third MOS transistor, a body of the third MOS transistor, and the third
A fourth MOS transistor of the first conductivity type having a gate connected to the second power source, the third node being directly connected to the second node, Alternatively, the fifth MO of the second conductivity type whose gate receives the input signal is input.
A semiconductor integrated circuit connected to the second node via an S transistor. 2. The semiconductor integrated circuit according to claim 1, wherein each of the MOS transistors is formed in a semiconductor layer on an insulating layer. 3. A plurality of the third MOS transistors are connected in parallel, one fourth MOS transistor is provided, and each body of the third MOS transistor is common to one end of the fourth MOS transistor. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuits are connected. 4. A plurality of the third MOS transistors are connected in parallel, and the fourth MOS transistor is the third MOS transistor.
A plurality of MOS transistors are provided corresponding to each of the MOS transistors, and the fourth MOS transistor is connected between each body of the third MOS transistor and the third node. 1. The semiconductor integrated circuit according to 1 or 2. 5. The semiconductor integrated device according to claim 1, further comprising an inverter circuit having an input terminal connected to the first node and an output terminal connected to a fourth node. circuit. 6. A sixth conductivity type sixth MOS transistor connected between the first power supply and the first node and having a gate connected to the fourth node. The semiconductor integrated circuit according to claim 5. 7. A semiconductor integrated circuit in which a plurality of MOS transistors are formed on a Si layer formed on a substrate via an insulating layer to form a synchronous logic circuit, the source of which is connected to a power supply terminal Vdd. A drain is connected to the first node, a p-channel first MOS transistor whose gate receives a clock signal, a source is connected to the ground terminal Vss, and a drain is connected to the second node,
An n-channel second MOS transistor whose gate receives the clock signal, and a logic evaluation unit which is connected between the first node and the second node and receives two input signals are provided. The drain of the logic evaluation unit is commonly connected to the first node, and the source of the logic evaluation unit is commonly connected to the second node.
Two n-channel third MOS transistors whose bodies are commonly connected and whose gates receive the two input signals respectively, and whose gate is connected to the ground terminal Vss and whose source is each of the third MOS transistors. A semiconductor integrated circuit comprising a p-channel fourth MOS transistor connected to the body and having a drain connected to the second node. 8. A semiconductor integrated circuit comprising a pass gate logic circuit composed of a plurality of MOS transistors, the logic evaluation being inserted between a first node and a second node which are input terminals of a first signal. And a latch circuit inserted between the second node and a third node serving as a signal output terminal, wherein the logic evaluation section includes the first node and the second node. And one or more evaluation MOS transistors each having a gate to which a second input signal is input, and a body of the evaluation MOS transistors whose source is connected to the first node. And the first
A semiconductor integrated circuit, which is connected to the node of the MOS transistor and has a leakage current preventing MOS transistor having a gate to which a constant voltage is input. 9. A first conductivity type having a source connected to a first node serving as an input terminal of a first signal, a drain connected to a second node, and a gate receiving a second input signal. A first MOS transistor, a second conductivity type second MOS transistor having a source connected to the first node, a drain connected to the body of the first MOS transistor, and a constant voltage input to a gate. And a latch circuit connected between the second node and a third node serving as a signal output terminal. 10. The semiconductor integrated circuit according to claim 8, wherein each of the MOS transistors is formed in a semiconductor layer on an insulating layer.