JP2003283254A - Frequency conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce conversion gain suppression by increasing a bias current only when a disturbing wave signal is inputted in the strong electric field. <P>SOLUTION: When a high frequency signal in a weak electric field is inputted, almost no current flows between the drain and source of a second FET 2, and current flows only through a self-bias resistor 14 connected to the source of a dual gate FET 1. When the high frequency in a strong electric field is inputted, the capacitance of a fourth DC-cut capacitor 28, the resistance of a third gate resistor 13, and a gate width of the second FET 2 are set so that the sum of the current flowing between the drain and source of the second FET 2 and the current flowing through the self-bias resistor 14 becomes a prescribed value. The bias current is increased only when the high frequency signal in the strong electric field is inputted, and the increase in the conversion gain suppression is suppressed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit, and more particularly to a frequency conversion circuit which is used in a radio receiver or the like which handles high frequency signals and which is suitable for semiconductor integrated circuits.

[0002]

2. Description of the Related Art Conventionally, in a frequency conversion circuit for a high frequency signal such as a quasi-microwave band, for example, an integrated circuit using a field effect transistor (FET-Field Effect Transistor) having a dual gate structure made of a gallium arsenide compound semiconductor is used. For example, a frequency conversion semiconductor circuit having a configuration as shown in FIG. 4 is publicly known and well known. The conventional circuit will be described below with reference to FIG. In this circuit, the dual gate FET 51 is used for frequency conversion. First, the first impedance matching circuit 52 and the first DC cutting capacitor 55 are provided in the first gate G1.
A local oscillation signal from the outside via the second impedance matching circuit 53 and the second impedance matching circuit 53 to the second gate G2.
A high-frequency signal is externally applied via the DC-cutting capacitor 56.

The source of the dual gate FET 51 is set to the ground potential via the self-biasing resistor 59, and the bypass capacitor 58 is provided between the source and the ground potential. . Here, the bypass capacitor 58 is provided to reduce the impedance between the source of the dual gate FET 51 and the ground potential at a required frequency from the viewpoint of ensuring the gain of this circuit at the time of frequency conversion, that is, the conversion gain. is there. The power supply voltage is applied to the drain of the dual gate FET 51 through the high frequency cutoff inductor 62, and the second gate G is also applied.
The high frequency signal having the sum and difference frequency components of the high frequency signal applied to 2 and the local oscillation signal applied to the first gate G1 is the third impedance matching circuit 54 and the third DC cutting capacitor 57. It can be obtained through.

[0004]

By the way, for example, in a frequency conversion circuit used for a receiver of a portable radio terminal or the like, a high frequency signal inputted to the frequency conversion circuit is usually weak, but there is a special problem. Assuming use under conditions, reception sensitivity suppression may be defined when a strong electric field interference signal is input to the frequency conversion circuit. However, in a frequency conversion circuit premised on frequency conversion of a weak electric field high frequency signal, when such a strong electric field interference signal is input, the circuit operation exceeds the linear operation region, and the conversion gain is suppressed. As a result, there is a problem that reception sensitivity is significantly deteriorated. In such a case, for example, by increasing the bias current of the frequency conversion circuit to increase the output, it is possible to reduce the conversion gain suppression due to the input of the interference wave signal of the strong electric field. In a portable wireless terminal to be used, the amount of power consumption of the battery power source increases with an increase in bias current during normal operation, which causes a problem that the operable time becomes short. In order to improve the deterioration of output characteristics when a strong electric field disturbance signal is input, for example, as disclosed in Japanese Patent Laid-Open No. 2000-91938, a buffer amplifier or the like is provided in an input stage of a frequency conversion circuit. There has been proposed a technique of providing a level detection circuit having the above and controlling the bias current of the frequency conversion circuit according to the level of the high frequency signal detected by the level detection circuit. However, in such a conventional technique, there is a problem that the scale of the level detection circuit becomes large, and especially in the case of an integrated circuit, the manufacturing cost increases due to the increase of the chip area.

The present invention has been made in view of the above situation, and provides a frequency conversion circuit capable of reducing the conversion gain suppression by increasing the bias current only when a strong electric field disturbing wave signal is input. To do. Another object of the present invention is to perform frequency conversion with less conversion gain suppression when an interference signal of a strong electric field is input, without increasing the circuit scale and area in the integrated circuit as much as possible compared with the conventional art. To provide a circuit.

[0006]

In order to achieve the above object, the frequency conversion circuit according to the present invention has a strong electric field gain that suppresses an increase in conversion gain suppression when a high frequency high frequency signal is input. In a frequency conversion circuit using a field effect transistor provided with an adjusting means, the field effect transistor has a dual gate structure, and the source of the dual gate field effect transistor and a ground potential are connected in parallel. The connected self-bias resistor and the bypass capacitor are connected in series, and the strong electric field gain adjusting means includes an enhancement type field effect transistor, and a gate of the enhancement type field effect transistor has a high frequency The enhancement type electric field is configured such that a part of the signal is applied. Fruit transistor is made connected in parallel to the self-bias resistor and a bypass capacitor.

In such a configuration, when the input level of the high frequency signal becomes high, the increase in the conversion gain suppression is suppressed by the strong electric field gain adjusting means. Therefore, unlike the conventional case, for example, when it is used in the receiving circuit, When a high-frequency signal of a strong electric field is input, it is prevented that the conversion gain suppression is increased and the reception sensitivity is significantly deteriorated, and a frequency conversion circuit having stable operation characteristics is provided.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, the circuit configuration in the first configuration example will be described with reference to FIG. In this first configuration example, a field effect transistor (hereinafter referred to as "dual gate FET") 1 having a dual gate structure is used for frequency conversion. That is, first, the second gate of the dual gate FET 1 (denoted as “G2” in FIG. 1) is connected to the ground potential via the first gate resistor 11, and the first DC cut capacitor is also connected. It is connected to the high frequency signal input terminal 35 via the first impedance matching circuit 25 and the first impedance matching circuit 21. A high frequency signal from the outside is applied to the high frequency signal input terminal 35. The first gate of the dual-gate FET 1 (denoted as “G1” in FIG. 1) is connected to the ground potential via the second gate resistor 12, and the second DC cut capacitor 26 and Second impedance matching circuit 2
It is connected to the local signal input terminal 36 via 2. A local oscillation signal from the outside is applied to this local signal input terminal 36.

On the other hand, the drain of the dual gate FET1 (denoted as "D1" in FIG. 1) is connected to the output terminal 39 via the third impedance matching circuit 23 and the third DC cutting capacitor 27. Has become. The third impedance matching circuit 23 and the third impedance matching circuit 23
The mutual connection point with the DC cut capacitor 27 of
One end of the high frequency blocking inductor 31 is connected.
The other end of the high frequency cutoff inductor 31 is connected to a power supply terminal 37 to which a power supply voltage is applied from the outside, and the high frequency cutoff inductor 31 and the third impedance matching circuit 23 are connected to the drain of the dual gate FET 1. The power supply voltage is applied via the.
Further, the source of the dual gate FET 1 (denoted as “S1” in FIG. 1) is connected to one ends of the self-bias resistor 14 and the bypass capacitor 29, respectively.
The other end of 9 is connected to the ground potential.

The frequency conversion circuit also includes a second field effect transistor (hereinafter referred to as "second FET") 2
As a main component, the strong electric field gain adjusting means is configured as described below. That is, first,
The second FET 2 is preferably an enhancement type, and its gate (indicated as “G3” in FIG. 1) is
Via the fourth DC-cutting capacitor 28, the first
It is connected to the connection point between the impedance matching circuit 21 and the first DC cutting capacitor 25, and is also connected to the ground potential via the third gate resistor 13. Further, the drain of the second FET 2 (denoted as “D3” in FIG. 1) is the dual gate FE described above.
The source (noted as "S3" in FIG. 1) is connected to the source of T1 while being connected to the ground potential. Therefore, the second FET 2 is provided in a state of being connected in parallel to the self-bias resistor 14 and the bypass capacitor 29.

In the above structure, a part of the high frequency signal applied to the high frequency signal input terminal 35 is applied to the gate of the second FET 2 via the fourth DC cutting capacitor 28. The magnitude of the signal is the fourth DC
It is determined by the capacitance value of the cut capacitor 28, the resistance value of the third gate resistor 13, and the gate width of the second FET 2. Then, more specifically, these circuit constants are set from the following viewpoints. That is, first, the high-frequency signal input terminal 35
When a high-frequency signal of a weak electric field is applied to the second FET 2, the drain-source current of the second FET 2 becomes substantially zero as compared with the current flowing in the self-bias resistor 14,
When a high-frequency signal of a strong electric field is applied to the high-frequency signal input terminal 35, the sum of the drain-source current of the second FET 2 and the current flowing through the self-bias resistor 14 should be a desired current value. , The capacitance value of the fourth DC cutting capacitor 28, the resistance value of the third gate resistor 13, and the gate width of the second FET 2 are set. The circuit in the above configuration is preferably a semiconductor integrated circuit, but of course, a so-called discrete circuit may be used.

Next, the operation of the above configuration will be described. First, when a high-frequency signal of a weak electric field is applied to the high-frequency signal input terminal 35, almost no current (drain-source current) flows through the second FET 2 due to the operating conditions of the circuit described above. Therefore, the bias current in this frequency conversion circuit is only the current flowing in the self-bias resistor 14 connected between the source of the dual gate FET 1 and the ground potential, and its value is the desired frequency conversion. A low current value is set in consideration of the circuit characteristics. On the other hand, when the high frequency signal of the strong electric field is applied to the high frequency signal input terminal 35,
A current also flows between the drain and the source of the FET 2 of, and the sum of this current and the current flowing in the self-bias resistor 14 becomes a predetermined value by setting the circuit constant as described above. That is, more specifically, the current value is such that the linear operation region of this frequency conversion circuit becomes high. As a result, when a strong electric field disturbance signal is input,
Unlike the conventional case, the conversion gain suppression characteristic is significantly improved.

Next, referring to FIGS. 3 and 5, the operation characteristics of the above-described configuration example will be described in comparison with those of the conventional circuit. First, FIG. 3 shows the test results by the simulation of the conversion gain and the power supply current characteristic with respect to the interference wave signal input power in the above configuration example, and FIG. 5 shows the similar characteristic example in the conventional circuit. Has been done. In both figures, the horizontal axis represents the interference wave input power,
The vertical axis shows the conversion gain and the power supply current. In each of the figures, the alternate long and short dash line is a characteristic line showing the change in the power supply current with respect to the change in the interfering wave input power, and the solid line is the characteristic line showing the change in the conversion gain with respect to the change in the interfering wave input power. Comparing the interfering wave input power, in the case of the conventional circuit, the interfering wave input power when the conversion gain is compressed by 1 dB is -11.5 dBm (see FIG. 5). In the first configuration example of the configuration, the interference wave input power is −7.3 dBm (see FIG.
It is understood that the conversion gain suppression characteristic at the time of an interference wave input signal is improved by about 4.2 dB as compared with the related art. The operation characteristics in the weak electric field are almost the same in both the circuit according to the embodiment of the present invention and the conventional circuit (see FIGS. 3 and 5).

Next, a second structural example will be described with reference to FIG. The same components as those shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. In this second configuration example, the circuit portion configured around the second FET 2 in the first configuration example above is configured around the second to fourth field effect transistors 2 to 4 connected in cascade. It has been replaced with the circuit.
That is, specifically described below, first, second to fourth field effect transistors (hereinafter referred to as “second FET”, “third FET”, and “fourth FET”) 2 For 4 to 4, it is preferable to use the enhancement type field effect transistor. The gate of the second FET 2 is connected to the connection point between the first impedance matching circuit 21 and the first DC cutting capacitor 25 via the fourth DC cutting capacitor 28, and
It is the same as the first configuration example shown in FIG. 1 above in that the source is directly connected to the ground potential while being connected to the ground potential via the third gate resistor 13. Is. The drain of the second FET 2 is connected to the gate of the third FET 3 (denoted as “G4” in FIG. 2), and the drain of the second FET 2 and the gate of the third FET 3 are Both are connected to the second power supply applying terminal 38 through the fourth resistor 15 as the first voltage applying resistor, and the power supply voltage is applied.

The third FET 3 has its drain (denoted as "D4" in FIG. 2) and the gate of the fourth FET 4 (denoted as "G5" in FIG. 2) as the second voltage application terminal. Each of them is connected to the second power supply applying terminal 38 via the resistor 16 of No. 5, and the power supply voltage is applied to each of them. And this third
Source of FET3 (indicated as “S4” in FIG. 2)
Is connected to the ground potential together with the source of the fourth FET 4 (described as “S5” in FIG. 2) described below. The drain of the fourth FET 4 (denoted as "D5" in FIG. 2) is the dual gate FET1.
It has been connected to the source of.

Next, the operation of the above configuration will be described. First, a case where a high-frequency signal of a weak electric field is applied to the high-frequency signal input terminal 35 will be described. Part of the high-frequency signal applied to the high-frequency signal input terminal 35 is the fourth signal.
The second FET 2 via the DC cut capacitor 28 of
The voltage amplitude applied to the gate of
The circuit constants are determined as described in the first configuration example shown in FIG. 1 so that the magnitude is equal to or lower than the voltage (pinch-off voltage) that can make the second FET 2 conductive. Therefore, the second FET 2 is turned off. Since the second FET 2 is non-conductive, a power supply voltage equal to or higher than the pinch-off voltage is externally applied to the gate of the third FET 3 via the fourth resistor 15.
The third FET 3 becomes conductive. Since the potential difference between the drain and the source of the third FET 3 becomes approximately 0 V due to conduction, the gate of the fourth FET 4 has a pinch-off voltage equal to or higher than the pinch-off voltage sufficient to bring the fourth FET 4 into the conductive state. The DC bias voltage is applied to the fourth FET 4 and the fourth FET 4 is turned off. That is, when a high-frequency signal with a weak electric field is applied to the high-frequency signal input terminal 35, the current flowing between the drain and source of the fourth FET 4 becomes substantially zero as compared with the current flowing through the self-bias resistor 14. It has become. Therefore, in this case, the bias current flows only through the self-bias resistor 14, and its value is a low current value set in consideration of the desired characteristics of the frequency conversion circuit.

On the other hand, when a high-frequency signal of a strong electric field is applied to the high-frequency signal input terminal 35, the second FET 2 becomes conductive due to the high-frequency signal applied via the fourth DC cutting capacitor 28, Thereby, the third
FET3 becomes non-conductive. Therefore, the fourth FE
As a result of the power supply voltage being applied to the gate of T4 via the fifth resistor 16, the fourth FET 4 becomes conductive.
In this case, the sum of the current flowing between the drain and source of the fourth FET 4 and the current flowing through the self-bias resistor 14 becomes the desired current value. That is, as in the case of the first configuration example shown in FIG. 1, when the high-frequency signal of the strong electric field is applied to the high-frequency signal input terminal 35 and the fourth FET 4 becomes conductive, the fourth FET 4 becomes conductive. The capacitance value of the DC cut capacitor 28, the resistance value of the third gate resistor 13, the second
To the gate widths of the fourth FETs 2 to 4 and the resistance values of the fourth and fifth resistors 15 and 16 between the current flowing between the drain and source of the fourth FET 4 and the current flowing in the self-bias resistor 14. The sum is set to a suitable value that gives a desired current value.

Although a field effect transistor having a dual gate structure is used in order to obtain a frequency conversion operation in the above configuration example, the field effect transistor is not limited to this, and for example, a field effect transistor having a so-called single gate structure is used. Of course, they may be connected in a stack structure.

[0019]

As described above, according to the present invention,
Since the configuration is such that the increase in conversion gain suppression is prevented only when a high-frequency signal with a strong electric field is input, the increase in circuit scale and area when integrated circuits are minimized compared to conventional circuits. Moreover, by adjusting the bias current only when a high-frequency signal of a strong electric field is input,
When a high-frequency signal with a weak electric field is input, the bias current can be reduced and power consumption can be suppressed as in the conventional circuit. Furthermore, when a high-frequency signal of a strong electric field is input, it is possible to efficiently increase the bias current to provide a frequency conversion circuit that suppresses conversion gain suppression.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first configuration example of a frequency conversion circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second configuration example of the frequency conversion circuit according to the embodiment of the present invention.

FIG. 3 is a characteristic diagram showing conversion gain and power supply current change characteristics with respect to change in interfering wave input power according to the first configuration example of the embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional circuit.

FIG. 5 is a characteristic diagram showing a change characteristic of a conversion gain and a power supply current with respect to a change of an interference wave input power of a conventional circuit.

[Explanation of symbols]

1 ... Dual gate FET 2 ... Enhancement type second FET 3 ... Enhancement type third FET 4 ... Enhancement type fourth FET 14 ... Self-biasing resistor 35 ... High frequency signal input terminal 36 ... Local signal input terminal 39 ... Output terminal

Claims (3)

[Claims] 1. A frequency conversion circuit using a field effect transistor comprising a strong electric field gain adjusting means for suppressing an increase in conversion gain suppression when a high frequency electric field signal of a strong electric field is inputted. A dual gate structure, and a self-bias resistor and a bypass capacitor connected in parallel are provided in series between the source of the dual gate field effect transistor and the ground potential, while the strong electric field is provided. The gain adjusting means includes an enhancement-type field effect transistor, and a gate of the enhancement-type field effect transistor is configured so that a part of a high frequency signal is applied to the enhancement-type field effect transistor. , Parallel to the self-biasing resistor and bypass capacitor Frequency conversion circuit characterized by comprising been continued. 2. A frequency conversion circuit using a field effect transistor having a strong electric field gain adjusting means for suppressing an increase in conversion gain suppression when a high frequency signal of a strong electric field is inputted, wherein the field effect transistor is A dual gate structure, and a self-bias resistor and a bypass capacitor connected in parallel are provided in series between the source of the dual gate field effect transistor and the ground potential, while the strong electric field is provided. The gain adjusting means includes enhancement type first to third field effect transistors, and the enhancement type first field effect transistor is provided so that a part of a high frequency signal is applied to its gate. , Its drain is connected to the gate of said enhancement type second field effect transistor At the same time, a power supply voltage can be applied to the drain of the enhancement-type first field-effect transistor and the gate of the enhancement-type second field-effect transistor via the first voltage-applying resistor. The drain of the second field effect transistor is connected to the gate of the enhancement type third field effect transistor, and the drain of the enhancement type second field effect transistor and the gate of the enhancement type third field effect transistor are connected to each other. , A power supply voltage can be applied via a second voltage applying resistor, the enhancement-type first to third field effect transistors have sources connected to a ground potential, and the enhancement-type third field effect transistor. The transistor is the self-biasing resistor and Frequency conversion circuit characterized by comprising connected in parallel to bypass capacitor. 3. The frequency conversion circuit according to claim 1, wherein, instead of the dual gate field effect transistor, two field effect transistors having a single gate structure are connected in a stack structure.