JP2003282868A - Method for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device having a field effect transistor in which a desired impurity region can be formed. <P>SOLUTION: The method for fabricating a semiconductor device 100 comprises step (a) for forming a gate insulation layer 12 and a gate electrode 14 sequentially on a first conductivity type semiconductor substrate 10, step (b) for forming first impurity regions 32 and 42 by introducing second conductivity type impurities into the semiconductor substrate 10 using the gate insulation layer 12 as a mask and then performing heat treatment, step (c) for forming second impurity regions 34 and 44 by introducing first conductivity type impurities at least beneath the first impurity regions 32 and 42, step (e) for forming a sidewall insulation layer 16 on the side face of the gate insulation layer 12, and step (f) for forming third impurity regions 30 and 40 for the source/drain region by introducing second conductivity type impurities. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a MOS transistor characterized by a method for forming an extension region.

[0002]

BACKGROUND ART In recent years, miniaturization and high integration of semiconductor devices have been rapidly advanced. Along with this, the channel length is shortened in the MOS transistor, so that a phenomenon called so-called punch-through easily occurs. Punch-through is a phenomenon in which a depletion layer in a source region and a depletion layer in a drain region are in contact with each other, so that a current always flows between a source and a drain and a leak current increases. The occurrence of punch through affects the transistor characteristics such as the threshold voltage of the transistor and the amount of off leak current.

As a countermeasure, there is a method of forming a punch-through stopper region below the source / drain region. The punch through stopper region is a region made of an impurity having a conductivity type opposite to that of the source / drain region. A method of forming a MOS transistor having such a structure will be described. In the following description, a MOS transistor having an LDD structure will be described.

First, on the first conductive type semiconductor substrate,
A gate insulating layer and a gate electrode are sequentially formed. Then, in the semiconductor substrate, using the gate electrode as a mask, impurities of the first conductivity type are introduced to form a first impurity region serving as a punch-through stopper region. An impurity of the second conductivity type is introduced at a position shallower than the first impurity region, and L
A second impurity region to be a DD region is formed. Then,
Perform heat treatment. Then, a sidewall is formed on the side surface of the gate electrode, the second conductivity type impurity is introduced using the gate electrode and the sidewall as a mask, and the source / source
A drain region is formed.

[0005]

In forming an NMOS transistor, the LDD region is formed by ion implantation of phosphorus or arsenic. For example, when arsenic is ion-implanted, a crystal defect layer may be formed in a region deeper than the LDD region. When the NMOS transistor is formed by applying the above-described technique, the punch-through stopper region and the boron forming the channel region are formed in the crystal defect layer because the punch-through stopper region is formed deeper than the LDD region. May be selectively diffused in the direction. Due to such a phenomenon, L
It is difficult to control the impurity concentration distribution in the DD region and the punch through stopper region.

It is an object of the present invention to provide a method of manufacturing a semiconductor device including a MOS transistor, which can form a desired impurity region.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, (a) a gate insulating layer and a gate electrode are sequentially formed on a first conductivity type semiconductor substrate, and (b) the semiconductor substrate is formed. Using the gate electrode as a mask, impurities of the second conductivity type are introduced to form a first impurity region, and then heat treatment is performed. (C) At least below the first impurity region, a first impurity region is formed. Introducing impurities of conductivity type,
A second impurity region is formed, (d) a sidewall insulating layer is formed on the side surface of the gate electrode, and (e) a second conductivity type impurity is introduced to form a third region for the source / drain regions. Forming an impurity region of.

According to the present invention, in the step (b), heat treatment is performed after forming the first impurity region. Therefore, even if a crystal defect or the like occurs due to ion implantation at the time of forming the first impurity region, the crystal defect can be repaired. As a result, an impurity region having a desired concentration distribution can be formed. The source / drain region means a source region or a drain region.

The present invention can take the following modes, for example.

In the present invention, in the step (c), the second impurity region can be formed so as to function at least as a punch through stopper region. According to this aspect, since the punch-through stopper region can be formed, punch-through can be prevented, and a highly reliable transistor can be formed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, a semiconductor device 100 formed by the manufacturing method according to this embodiment will be described with reference to FIG. The semiconductor device 100 includes a P-type semiconductor substrate 10 having an element region defined by a trench element isolation region 20. A gate insulating layer 12 is formed on the semiconductor substrate 10. A gate electrode 14 is formed on the gate insulating layer 12. A source region 30 is formed in the semiconductor substrate 10 on one side of the gate insulating layer 12. A drain region 40 is formed in the semiconductor substrate 10 on the other side of the gate insulating layer 12.
A first low concentration impurity region 32 is formed in the semiconductor substrate 10 between the gate insulating layer 12 and the source region 30. In addition, the gate insulating layer 12 and the drain region 40
And the second low concentration impurity region 42 is formed in the semiconductor substrate 10.

First and second low-concentration impurity regions 32,
Below the 42, first and second punch-through stopper regions 34 and 44 are formed. Above the first and second low concentration impurity regions 32 and 42, the gate electrode 1 is formed.
The side wall insulating layer 16 is formed on the side wall of No. 4.

Next, a method of manufacturing the semiconductor device 100 will be described with reference to the drawings. In this embodiment, N
A method of forming a MOS transistor will be described.

(1) First, as shown in FIG. 2, a P well (not shown) is formed in a P type semiconductor substrate (hereinafter referred to as "semiconductor substrate") 10 by a known method. next,
The trench element isolation region 20 is formed by a known method.

Next, P-type impurities are introduced into the semiconductor substrate 10 for adjusting the threshold value to form impurity regions.
For example, boron can be ion-implanted as an impurity, and the ion implantation dose is, for example, 1 × 10 5.
It can be ¹² to 1 × 10 ¹³ cm ⁻² . The impurity region below the gate insulating layer 12 can function as the channel region 50.

(2) Next, an insulating layer (not shown) for the gate insulating layer 12 is formed on the semiconductor substrate 10.
Next, a polysilicon layer (not shown) is formed on the gate insulating layer. The polysilicon layer is formed by, for example, the CVD method.

The thickness of the polysilicon layer is set, for example, under the gate insulating layer 12 by blocking impurities during the implantation of impurities for forming first and second low-concentration impurity regions which will be described later. The thickness is such that impurities are not implanted into the semiconductor substrate 10. Specifically, the thickness of the polysilicon layer is, for example, 200 to 350 nm, preferably 250.
~ 300 nm.

Next, as shown in FIG. 2, the polysilicon layer and the gate insulating layer are patterned by photolithography and etching to form the gate insulating layer 12 and the gate electrode 14. Then, if necessary, the semiconductor substrate 10 and the gate electrode 14 are sacrificial-oxidized.

(3) Next, as shown in FIG. 3, N type impurities 60 are introduced into the semiconductor substrate 10 by ion implantation to form first and second low concentration impurity regions 32 and 42.

In this ion implantation, phosphorus or arsenic is ion-implanted. The ion implantation conditions are not particularly limited as long as the first and second low concentration impurity regions 32 and 42 are formed. Taking arsenic as an N-type impurity, the dose amount of ion implantation is, for example, 1 × 10 5.
^{14 to} 5 × 10 ¹⁵ cm ^-2 , preferably 5 × 10 ¹⁴ to 1 × 1
It is 0 ¹⁵ cm ^-2 . Further, as a method of controlling the impurities ion-implanted into the semiconductor substrate 10 below the gate insulating layer 12, for example, the film thickness of the gate electrode 14 can be controlled.

Then, a heat treatment is performed, and the first and second heat treatments are performed.
The crystal defects generated when the low-concentration impurity regions 32 and 42 are formed are recovered. This heat treatment is preferably performed at about 1000 ° C.

(4) Next, as shown in FIG. 4, first and second punch-through stopper regions 34, 44 are formed in regions deeper than the first and second low-concentration impurity regions 32, 42. The punch through stopper regions 34 and 44 include
Impurities of opposite conductivity type are introduced into the first and second low concentration impurity regions 32 and 42. In this ion implantation, for example, boron can be implanted, and the ion implantation conditions are not particularly limited as long as the first and second punch-through stopper regions 34 and 44 can be formed. Taking boron as an example of impurities, the ion implantation dose is, for example, 1 × 10 ^{12 to} 5 × 10 5.
^{It is 13} cm ⁻² , preferably 5 × 10 ¹² to 1 × 10 ¹³ cm ⁻² .

Next, as shown in FIG.
The sidewall insulating layer 16 is formed on both sides by a known method. For example,
The sidewall insulating layer 16 can be formed. C
A silicon oxide film (not shown) is formed on the entire surface by the VD method or the like. Then, the sidewall insulating layer 16 can be formed by anisotropically etching the silicon oxide film by reactive ion etching or the like.

(5) Next, as shown in FIG. 4, impurities such as arsenic are ion-implanted into the semiconductor substrate 10 using the gate electrode 14 and the sidewall insulating layer 16 as a mask. The dose of ion implantation is, for example, 5
× 10 ¹⁴ to 1 × 10 ¹⁶ cm ^-2 , preferably 1 × 10 ¹⁵ to
It is 5 × 10 ¹⁵ cm ^-2 . In this ion implantation of impurities, the gate electrode 14 and the sidewall insulating layer 16
Plays a role of blocking impurities. As a result, no impurities are implanted into the semiconductor substrate 10 below the gate insulating layer 12 and the sidewall insulating layer 16 in this ion implantation step. Thus, the sidewall insulating layer 1
The source region 30 and the drain region 40 in the semiconductor substrate 10 on the sides of 6 are formed, and the semiconductor device 100 according to the present embodiment is completed.

According to the present embodiment, first, first and second low concentration impurity regions 32 and 42 are formed, and a heat treatment is further performed. By this step, the first and second
The crystal defects generated when the low-concentration impurity regions 32 and 42 are formed are repaired. As a result, an impurity region having a desired concentration distribution can be formed.

Since the first and second punch-through stopper regions 34 and 44 are formed in a state where the crystal defects are repaired, impurities forming the first and second punch-through stopper regions 34 and 44 are It is possible to prevent the problem of selective diffusion in the direction of crystal defects. Moreover, although the impurities forming the channel region 50 may cause the same phenomenon, such a problem can be prevented.

The present invention is not limited to the above-mentioned embodiments, but can be modified within the scope of the gist of the present invention. For example, it can be applied when the conductivity types are opposite. Further, the impurity concentrations of the first and second low-concentration impurity regions 32 and 42 may be similar to those of the source region 30 and the drain region 40.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device obtained by a manufacturing method according to an embodiment.

FIG. 2 is a sectional view schematically showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 3 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 4 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

[Explanation of symbols]

10 semiconductor substrate 12 gate insulating layer 14 gate electrode 16 sidewall insulating layer 20 element isolation regions 30, 40 source / drain regions 32, 42 first and second low-concentration impurity regions 34, 44 first and second punch through Stopper region 50 Channel region 60 Impurity 100 Semiconductor device

Claims (2)

[Claims] 1. A gate insulating layer and a gate electrode are sequentially formed on a semiconductor substrate of a first conductivity type, and a second conductivity type impurity is formed on the semiconductor substrate by using the gate electrode as a mask. Is formed to form a first impurity region, and then heat treatment is performed. (C) At least a first conductivity type impurity is introduced below the first impurity region, and a second impurity region is formed. And (d) forming a sidewall insulating layer on the side surface of the gate electrode, and (e) introducing a second conductivity type impurity to form a third impurity region for the source / drain region. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the second impurity region is formed so as to function at least as a punch-through stopper region.