JP2003282657A - Pattern inspection device for semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem with prior art that the size of a wafer 22 becomes larger is an increasing step 4, 5, 6 and 8 in., and at the same time a design rule becomes finer and hence a pattern becomes finer to result in an increase of amount of pattern data, so that a pattern inspection time per the wafer 22 is prolonged. <P>SOLUTION: In a pattern inspection device 10 for a semiconductor chip, a plurality of chips 11 are inspected simultaneously using a plurality of cameras 14 and a plurality of data processing devices 15. Provided that N sets of cameras 14 and N pieces of PCs 15 are simultaneously operated to simultaneously inspect the N pieces of chips 11, inspection time for the wafer 12 is reduced to 1/N times when compared with the prior art. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state of being regularly formed on a semiconductor wafer (that is, before dicing).
The present invention relates to an automatic pattern inspection device for semiconductor chips.

[0002]

2. Description of the Related Art In a semiconductor chip (hereinafter abbreviated as a chip), the original pattern may be destroyed due to the influence of dust in a PR process or a film forming process. Therefore, the chip pattern must be inspected in a completed state or an unfinished state. Since it is a difficult task for humans, an automatic pattern inspection device is used. If the wafer is diced, the position and direction of each chip will be disturbed, so it cannot be handled by an automatic pattern inspection device. Therefore, the chips in the state of the wafer before dicing (chip-on-wafer) are applied to the automatic pattern inspection device.

FIG. 5 is a front view and a plan view of a main part of a conventional semiconductor chip automatic pattern inspection apparatus 20. A large number of chips 21 on the wafer 22 in the X direction (horizontal direction),
They are regularly arranged in the Y direction (front-back direction). The wafer 22 is fixed to the stage 23 by suction. The stage 23 is X, according to the arrangement pitch of the chips 21 to be inspected,
The pitch is fed in the Y direction. C just above the wafer 22
A CD camera 24 is attached. CCD camera 2
The magnification of 4 is adjusted so that one chip 21 fits in the field of view.

The pattern of the chip 21 is a CCD camera 24.
And is sent to a PC (personal computer) 25 as pattern data. As a reference for comparison, the PC 25 stores the pattern of the chip 21 photographed immediately before and compares it with the pattern of the chip 21. PC25
In the inside, the difference between the pattern data of the chip 21 photographed immediately before and the pattern data of the chip 21 is calculated. If the patterns of both chips 21 are exactly the same, the pattern data of both chips 21 are the same, so the difference is zero. Actually, there is a difference in the patterns of both chips 21, so there is a difference in that part. If the difference is within the limit, it is automatically determined that there is no pattern collapse, and if it exceeds the limit, it is automatically determined that there is pattern collapse. The pattern inspection time for one row from the edge of the wafer 22 is about 60 seconds on average for a small chip and 1 on average for a large chip.
It is about 80 seconds.

FIG. 6 shows a CC when an automatic pattern inspection is performed on a single wafer 22 by a conventional automatic pattern inspection apparatus 20.
This is the trajectory 26 of the D camera 24. Actually CCD camera 2
4 is fixed and the wafer 22 moves, but the relative trajectory 26 is as shown in FIG. In the wafer 22 shown in FIG. 6, 52 chips 21 are arranged. As can be seen from FIG. 6, in the case of the arrangement of the chips 21, the CCD camera 24 has to make four reciprocations to inspect an entire wafer 22.

In FIG. 6, the number of chips 21 is 52 for the sake of explanation.
Although the number is as small as 100, hundreds to tens of thousands of chips 21 are arranged on the actual wafer 22. Therefore C
The CD camera 24 has to make several tens to several hundreds of rounds to inspect the pattern of one wafer 22. Dozens of round trips are when the chip 21 is large, so the inspection time for one chip 21 is long, and hundreds of round trips are for the chip 2.
Since 1 is small, the inspection time for one chip 21 is short. Therefore, even if the number of reciprocations is small, the inspection time per wafer 22 is not necessarily short. After all, the required inspection time is almost determined by the size of the wafer 22.

[0007]

The size of the wafer 22 has been increasing in the order of 4 inches → 5 inches → 6 inches → 8 inches. At the same time, the design rule becomes finer and the pattern becomes finer, and the amount of pattern data is increasing. Since the calculation speed of the PC 25 is dramatically increased, the inspection time per unit pattern data amount is very short. However, since the size of the wafer 22 and the increase in the amount of data due to the finer pattern cannot be kept up, the inspection time per wafer 22 is becoming longer.

On the other hand, even if the size of the wafer 22 is increased, the time for the main steps such as diffusion, film formation and etching is not so long. Therefore, the ratio of the pattern inspection time becomes high in the total manufacturing time of the chip 21. Since the pattern inspection work has a low added value, it is not good that the ratio of the pattern inspection time is high. If the pattern inspection takes time, the wafer 22
Can easily become stagnant and cause delivery problems.

In order to solve the above problems, the present invention is a semiconductor chip pattern inspection apparatus capable of performing a pattern inspection in a short time even on a large-sized wafer.

[0010]

The invention according to claim 1 is
A semiconductor chip pattern inspection apparatus for automatically inspecting a pattern of a chip formed on a semiconductor wafer, characterized by simultaneously inspecting a plurality of chips by simultaneously using a plurality of cameras and a plurality of data processing devices. This is a chip pattern inspection device.

In the conventional pattern inspection apparatus, one camera and one data processing apparatus (PC: personal computer) inspect chips one by one. Therefore, when the wafer becomes large and the number of chips in one wafer increases, the time for inspecting one wafer becomes very long. In the pattern inspection apparatus of the present invention, for example, 5 cameras and 5 PCs are simultaneously operated to inspect 5 chips at the same time. By doing so, the inspection time for one wafer is ⅕ of the conventional one.

According to a second aspect of the present invention, in the semiconductor chip pattern inspection apparatus according to the first aspect, a plurality of cameras are arranged at intervals of an integral multiple of a chip arrangement pitch. It is a pattern inspection device.

When shooting a plurality of chips at the same time with a plurality of cameras, if the cameras are arranged at intervals of an integer multiple of the chip arrangement pitch, the positions of the camera and the chips are always the same when the stage is pitch-fed at the chip arrangement pitch. It is convenient because it fits.

According to a third aspect of the present invention, there is provided the semiconductor chip pattern inspection apparatus according to the second aspect, wherein the plurality of cameras are arranged in a staggered pattern.

Since the size of the camera is considerably larger than the chip size, when the cameras are arranged in a line, the interval between the cameras is significantly larger than the chip arrangement pitch, which may be unsatisfactory. In that case, it is convenient to arrange the cameras in a staggered manner because the distance between the cameras approaches the arrangement pitch of the chips.

According to a fourth aspect of the present invention, in the semiconductor chip pattern inspection apparatus according to the second aspect, the arrangement of the plurality of cameras can be adjusted according to the chip arrangement. .

Since the arrangement pitch of the chips is various, it is convenient that the position of each camera can be freely adjusted in order to arrange a plurality of cameras at intervals of an integral multiple of the arrangement pitch of the chips.

According to a fifth aspect of the present invention, in the semiconductor chip pattern inspection apparatus according to the first aspect, an optical fiber is attached to the tip of the camera, and the arrangement interval of the tip of the optical fiber is made smaller than the arrangement interval of the camera. The semiconductor chip pattern inspection apparatus is characterized in that the arrangement interval of the tips is set to an integer multiple of the chip arrangement pitch.

If the chip size becomes very small, the chip arrangement pitch becomes very small, and it becomes impossible to match the chip arrangement pitch even if the cameras are arranged in a staggered manner. In that case, the optical fiber is attached to the tip of the camera in this way, and the tip of the optical fiber is densely arranged. The diameter of the optical fiber is much smaller than that of the camera, so it can accommodate a small chip.

According to a sixth aspect of the present invention, in the semiconductor chip pattern inspection apparatus according to the first aspect, a plurality of chips are placed in the field of view of each camera, and each camera inspects the patterns of the plurality of chips at once. It is a characteristic semiconductor chip pattern inspection apparatus.

When the chip size is small, it is more efficient to collectively take a plurality of chips in a rectangular shape and inspect it, rather than to inspect the cameras one by one. The reason is that the inspection time for one field of view is long, but the number of stage feeds is smaller than that for inspecting chips one by one and sending the stage, and the stage feed time can be shortened accordingly.

[0022]

1 is a front view and a plan view of a main portion of an example 10 of a semiconductor chip automatic pattern inspection apparatus according to the present invention. A large number of chips 11 are regularly arranged on the wafer 12 in the X direction (left-right direction) and the Y direction (front-back direction). Actually, hundreds to tens of thousands of chips 11 are arranged on one wafer 12, but for convenience of explanation, FIG.
52 chips 11 are drawn. Wafer 12
Are fixed to the stage 13 by suction. The stage 13 is pitch-fed in the X and Y directions according to the arrangement pitch of the chips 11 to be inspected. Directly above the wafer 12, a plurality of (four in FIG. 1) CCD cameras 14 are mounted. The magnification of each CCD camera 14 is one chip 1 in the field of view.
It has been adjusted so that 1 fits in exactly. The distance between the CCD cameras 14 in the X direction is equal to the chip 11 on the wafer 12.
The pitch is adjusted to be an integral multiple of the X-direction pitch.

The pattern of the chip 11 is photographed by the CCD camera 14 immediately above each and sent to each PC (personal computer) 15 as pattern data. As a reference for comparison, the PC 15 stores the pattern of the chip 11 taken immediately before and compares it with the pattern of the chip 11. The previous chip 11 in the PC 15
And the difference between the pattern data of the chip 11 is calculated. If the patterns of both chips 11 are exactly the same, both chips 11
Since the data of is the same, the difference is zero. Actually, there is always a difference in the patterns of both chips 11, so there is a difference in that part. If the difference is within the limit, it is determined that there is no pattern collapse, and if it exceeds the limit, it is determined that there is pattern collapse.

In the case of FIG. 1, the comparison calculation of the pattern data of the four chips 11 is simultaneously performed by the four PCs 15. Therefore, the pattern inspection of four chips 11 can be performed in the time required for the pattern inspection of one chip 11 conventionally. Therefore, the pattern inspection time is substantially 1 /
4.

FIG. 2 shows an automatic pattern inspection apparatus 10 according to the present invention.
C for automatic pattern inspection of one wafer 12 with
This is the locus 16 of the CD camera 14. Actually, the CCD camera 14 is fixed and the wafer 12 moves, but the relative locus 16 is as shown in FIG. As can be seen from FIG. 2, in the case of the arrangement of the chips 11, the CCD camera 14 needs only one round trip to inspect the entire wafer 12. With the conventional automatic pattern inspection device, it takes 4 to inspect the entire wafer 12.
Since it has to reciprocate, the number of reciprocations in the automatic pattern inspection apparatus of the present invention becomes 1/4. As a result, the automatic pattern inspection apparatus of the present invention reduces the pattern inspection time to 1/4 of the conventional time.

In FIG. 2, the number of chips 11 is drawn small for the sake of explanation, and therefore the number of reciprocations is only one. However, hundreds to tens of thousands of chips 11 are arranged on the actual wafer 12. Therefore, the number of round trips of the CCD camera 14 is much larger than that in the case of FIG. 2 and becomes several tens to several hundreds. However, it is the same as in the case of FIG.

The distance between the CCD cameras 14 in the X direction is adjusted to be an integral multiple of the X direction pitch between the chips 11 on the wafer 12. However, since the size of the chip 11 is small, it may not be possible when the pitch in the X direction is small. In that case, if the CCD cameras 14 are staggered in a staggered manner as shown in FIG. 3, the time can be shortened as compared with the case where they are arranged in a line. At this time, the distance between the CCD cameras 14 in the Y direction is adjusted to be an integral multiple of the Y direction pitch between the chips 11.

If the size of the chip 11 is smaller and the pitch in the X direction is small and it is not possible to stagger the CCD cameras 14 in a staggered manner, the optical fiber 17 is attached to the tip of the CCD camera 14 as shown in FIG. Optical fiber 1
Since 7 is much smaller than the CCD camera 14, the arrangement pitch can be greatly reduced. Although not shown, the optical fibers 17 may be staggered.

When the size of the chip 11 is small, the plurality of chips 11 can be placed in the field of view of the CCD camera 14 instead of forcing the interval between the CCD cameras 14 to be reduced. The plurality of chips 11 are, for example, four (9,
16 chips 11). In this case, the PC 15 compares and calculates the patterns of four (9, 16, ...) Chips 11 at a time. This is Stage 13
Since it requires less time to mechanically move the CCD camera, it is more efficient than operating the CCD camera 14 with a narrow interval.

[0030]

According to the conventional pattern inspection apparatus, one camera and one data processing apparatus (PC: personal computer) inspect chips one by one. In this case, when the wafer becomes large and the number of chips in one wafer increases, the time for inspecting one wafer becomes very long. In the semiconductor chip pattern inspection device of the present invention, a plurality of cameras and a plurality of data processing devices are simultaneously used to inspect a plurality of chips at the same time.
The pattern inspection apparatus of the present invention includes N cameras and N PCs.
When N chips are inspected at the same time by operating simultaneously, the inspection time for one wafer becomes 1 / N of the conventional one.

[Brief description of drawings]

FIG. 1 is a front view and a plan view of a main part of an automatic pattern inspection device 10 according to the present invention.

FIG. 2 shows a CC in the automatic pattern inspection device 10 of the present invention.
Track of D camera 14

FIG. 3 is a schematic view showing a CCD in the automatic pattern inspection device 10 of the present invention.
Front and plan views with cameras 14 arranged in a staggered manner

FIG. 4 is a schematic view showing a CCD in the automatic pattern inspection device 10 of the present invention.
Front view and plan view of the optical fiber 17 attached to the tip of the camera 14.

FIG. 5 is a front view and a plan view of a main part of a conventional automatic pattern inspection device 20.

FIG. 6 is a CCD in a conventional automatic pattern inspection device 20.
Locus of camera 24

[Explanation of symbols]

10 Automatic pattern inspection apparatus of the present invention 11 chips 12 wafers 13 stages 14 CCD camera 15 PC (personal computer) 16 CCD camera trajectory 17 optical fiber 20 Conventional automatic pattern inspection system 21 chips 22 wafers 23 stages 24 CCD camera 25 PC (personal computer) 26 CCD camera trajectory

Claims (6)

[Claims] 1. A semiconductor chip pattern inspection apparatus for automatically inspecting a pattern of a chip formed on a semiconductor wafer, wherein a plurality of cameras and a plurality of data processing devices are simultaneously used to inspect a plurality of the chips at the same time. A semiconductor chip pattern inspection device characterized by the above. 2. The semiconductor chip pattern inspection apparatus according to claim 1, wherein the plurality of cameras are arranged at intervals of an integral multiple of an arrangement pitch of the chips. 3. The pattern inspection apparatus for a semiconductor chip according to claim 2, wherein the plurality of cameras are arranged in a staggered pattern. 4. The semiconductor chip pattern inspection apparatus according to claim 2, wherein the arrangement of the plurality of cameras can be adjusted according to the arrangement of the chips. 5. The semiconductor chip pattern inspection apparatus according to claim 1, wherein an optical fiber is attached to a tip of the camera, an arrangement interval of the tip of the optical fiber is set smaller than an arrangement interval of the camera, and A pattern inspection device for a semiconductor chip, wherein an arrangement interval is an integer multiple of an arrangement pitch of the chips. 6. The semiconductor chip pattern inspection apparatus according to claim 1, wherein a plurality of said chips are placed in the field of view of each said camera, and each camera inspects the patterns of said plurality of chips at one time. Semiconductor chip pattern inspection device.