JP2003280984A5 - - Google Patents
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- Publication number
- JP2003280984A5 JP2003280984A5 JP2003043570A JP2003043570A JP2003280984A5 JP 2003280984 A5 JP2003280984 A5 JP 2003280984A5 JP 2003043570 A JP2003043570 A JP 2003043570A JP 2003043570 A JP2003043570 A JP 2003043570A JP 2003280984 A5 JP2003280984 A5 JP 2003280984A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/080,739 | 2002-02-22 | ||
| US10/080,739 US6807603B2 (en) | 2002-02-22 | 2002-02-22 | System and method for input/output module virtualization and memory interleaving using cell map |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003280984A JP2003280984A (ja) | 2003-10-03 |
| JP2003280984A5 true JP2003280984A5 (ja) | 2006-04-06 |
| JP4445708B2 JP4445708B2 (ja) | 2010-04-07 |
Family
ID=27752849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003043570A Expired - Fee Related JP4445708B2 (ja) | 2002-02-22 | 2003-02-21 | マップテーブルを使用して入出力モジュールにアクセスする方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6807603B2 (ja) |
| JP (1) | JP4445708B2 (ja) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060015589A1 (en) * | 2004-07-16 | 2006-01-19 | Ang Boon S | Generating a service configuration |
| US20060015772A1 (en) * | 2004-07-16 | 2006-01-19 | Ang Boon S | Reconfigurable memory system |
| EP1825433A4 (en) * | 2004-11-23 | 2010-01-06 | Efficient Memory Technology | METHOD AND APPARATUS FOR MULTIPLE INTERLAYING ADDRESSING INTERLACES OF PAGINATED MEMORIES AND INTELLIGENT MEMORY BANKS |
| US8190809B2 (en) * | 2004-11-23 | 2012-05-29 | Efficient Memory Technology | Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines |
| US20130232304A1 (en) * | 2012-03-05 | 2013-09-05 | Qualcomm Incorporated | Accelerated interleaved memory data transfers in microprocessor-based systems, and related devices, methods, and computer-readable media |
| US10140223B2 (en) * | 2016-06-27 | 2018-11-27 | Qualcomm Incorporated | System and method for odd modulus memory channel interleaving |
| US11562101B2 (en) * | 2017-11-13 | 2023-01-24 | Intel Corporation | On-device bitstream validation |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293607A (en) | 1991-04-03 | 1994-03-08 | Hewlett-Packard Company | Flexible N-way memory interleaving |
| US5530837A (en) | 1994-03-28 | 1996-06-25 | Hewlett-Packard Co. | Methods and apparatus for interleaving memory transactions into an arbitrary number of banks |
| US5655113A (en) * | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
| EP0931290A1 (en) | 1997-03-21 | 1999-07-28 | International Business Machines Corporation | Address mapping for system memory |
| EP1050819A1 (en) | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Computer memory access |
| US6526459B1 (en) * | 1999-11-10 | 2003-02-25 | Ati International Srl | Allocation of input/output bus address space to native input/output devices |
| US6480943B1 (en) | 2000-04-29 | 2002-11-12 | Hewlett-Packard Company | Memory address interleaving and offset bits for cell interleaving of memory |
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2002
- 2002-02-22 US US10/080,739 patent/US6807603B2/en not_active Expired - Fee Related
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2003
- 2003-02-21 JP JP2003043570A patent/JP4445708B2/ja not_active Expired - Fee Related