JP2003273847A - Digital signal processing circuit, semiconductor device using digital signal processing circuit, and design method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and the like, which can avoid malfunctions at the time of operating in synchronization using a plurality of clock signals of different frequencies. <P>SOLUTION: A semiconductor device 1 is provided with a first core 2 for receiving a first clock signal, for operating, in synchronization with the first clock signal, and for outputting a data signal which changes in synchronization with the first clock signal, a second core 3 for receiving a second clock signal, whose frequency is different from the first clock signal, for operating in synchronization with the second clock signal, and for receiving the data signal in synchronization with the second clock signal, and a digital signal processing circuit 4 for latching the data signal outputted by the first core 2, and for outputting the latched signal to the second core 3. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit which latches an input signal and outputs the latched signal. Furthermore, the present invention relates to a semiconductor device using such a digital signal processing circuit, and a designing method for such a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, a plurality of cores (functional blocks) that operate in synchronization with a plurality of clock signals having different frequencies may be used. Figure 9
It is a figure which shows such a conventional semiconductor device. As shown in FIG. 9, the semiconductor device 21 includes a first core 2 and a second core 2.
2, 23 and a D-type flip-flop 24.

The first and second cores 22 and 23 are circuit blocks that realize predetermined functions, for example, CP.
U (Central Processing Unit), DSP (Digital Sig)
nalProcessor) etc. The first core 22 receives the first clock signal, performs a predetermined operation in synchronization with the first clock signal, and outputs the signal at the falling edge of the first clock signal. The output signal of the first core 22 is input to the data input terminal D of the flip-flop 24.

The flip-flop 24 receives the first clock signal at the clock input terminal C, latches the output signal of the first core 22 at the rising edge of the first clock signal, and outputs the latched signal at the output terminal Q. Output from. The output signal of the flip-flop 24 is the second core 2
Input to 3. The second core 23 receives the second clock signal, samples the output signal of the flip-flop 24 in synchronization with the second clock signal, and performs a predetermined operation in synchronization with the second clock signal.

FIG. 10 is a timing chart showing the operation timing of the flip-flop 24. The operation of the flip-flop 24 will be described below with reference to FIG. As shown in FIG. 10, the first clock signal rises at times t ₂₁ , t ₂₃ , t ₂₅ , and t ₂₇ , and at time t
_It falls at ₂₂ , t ₂₄ , t ₂₆ , and t ₂₈ .

Here, at time t ₂₂ , the core 22
When a high level signal is output, the flip-flop 24
Latches this signal at time t ₂₃ . Then, the flip-flop 24 outputs a high level signal at time t ₂₃ . The core 23 outputs this signal to the second
Sampling is performed in synchronization with the clock signal of.

However, the first clock signal and the second clock signal
Since the frequency of the clock signal is different, the timing at which the core 23 samples the output signal of the flip-flop 24 is asynchronous with the output timing of the flip-flop 24. Therefore, the semiconductor device 21 may malfunction. Further, it is necessary to design the semiconductor device 21 so as to satisfy the conditions of the setup time and the hold time of the flip-flop 24, which imposes a heavy load on the designer who designs the timing of the semiconductor device.

Incidentally, Japanese Patent Application Publication (JP-A) No. 6-45880 (hereinafter also referred to as "reference 1") discloses a data edge for detecting a change in a data input signal and outputting a data detection signal. A detection circuit, a clock edge detection circuit that detects a trigger edge of a clock input signal and outputs a clock detection signal, a first AND gate that inputs the data detection signal and the clock detection signal, and the AND A second logical product gate that outputs a logical product signal of the output signal of the gate and the clock detection signal, and a delayed data signal of the data input signal and the logical product signal are input respectively and output a logical sum signal. A signal control circuit having a logical sum gate, the logical sum signal being input to the data end, and the delayed clock signal of the clock signal being input to the clock end. Delay-type flip-flop circuit which comprises a flip-flop for outputting the delayed data output signal to the data output terminal can be found. However, the delay-type flip-flop circuit described in Reference 1 is a delay-type flip-flop circuit that operates by receiving a single clock signal. It does not output a synchronizing signal.

[0009]

In view of the above problems, the present invention is designed to prevent malfunction of a semiconductor device that operates in synchronization with a plurality of clock signals having different frequencies and to design the timing of the semiconductor device. To provide a digital signal processing circuit capable of reducing the load on a person
The purpose of. A second object of the present invention is to provide a semiconductor device using such a digital signal processing circuit. A third object of the present invention is to provide a method for designing such a semiconductor device.

[0010]

In order to solve the above problems, a digital signal processing circuit according to the present invention receives first and second clock signals having different frequencies and synchronizes with the first clock signal. It is characterized in that the data signal that changes with time is latched in synchronization with the first clock signal, and the latched signal is output in synchronization with the second clock signal.

Here, the latched signal may be output in synchronization with the second clock signal and may be output in synchronization with the first clock signal.

Further, the semiconductor device according to the present invention receives the first clock signal, operates in synchronization with the first clock signal, and outputs a data signal which changes in synchronization with the first clock signal. A first functional block, a digital signal processing circuit according to the present invention for latching a data signal output by the first functional block, and outputting the latched signal, and a second clock signal for receiving a second clock signal. A second functional block that operates in synchronization with the signal and receives the output signal of the digital signal processing circuit in synchronization with the second clock signal.

Here, the first functional block and the digital signal processing circuit may be included in one macroblock, or the second functional block and the digital signal processing circuit may be included in one macroblock. It may be included.

A semiconductor device designing method according to a first aspect of the present invention receives a first clock signal, operates in synchronization with the first clock signal, and synchronizes with the first clock signal. The step (a) of arranging a first functional block that outputs a data signal that changes according to
And a digital signal which receives the second clock signal, latches the data signal output from the first functional block in synchronization with the first clock signal, and outputs the latched signal in synchronization with the second clock signal. A step (b) of arranging the processing circuit, and receiving a second clock signal, operating in synchronization with the second clock signal, and receiving an output signal of the digital signal processing circuit in synchronization with the second clock signal Second
Step (c) of arranging the functional block of the above, and a first wiring connecting the output of the first functional block and the data input of the digital signal processing circuit, the data output of the digital signal processing circuit and the data of the second functional block The second wiring for connecting the input, the third wiring for supplying the first clock signal to the first functional block, the first wiring for the digital signal processing circuit
A fourth wiring for supplying a clock signal to the digital signal processing circuit, a fifth wiring for supplying a second clock signal to the digital signal processing circuit,
And arranging a sixth wiring for supplying the second clock signal to the second functional block (d).

A semiconductor device designing method according to a second aspect of the present invention receives a first clock signal, operates in synchronization with the first clock signal, and synchronizes with the first clock signal. A first functional block that outputs a data signal that changes according to the first and second clock signals having different frequencies, and synchronizes the data signal output by the first functional block with the first clock signal. A step (a) of arranging a macroblock including a digital signal processing circuit for latching and outputting the latched signal in synchronization with the second clock signal; and receiving the second clock signal and converting it into the second clock signal. Step (b) of arranging a second functional block that operates in synchronization and receives the output signal of the digital signal processing circuit in synchronization with the second clock signal, and the data output of the macroblock A first wiring connecting a data input of the second functional block, a second wiring supplying a first clock signal to the macroblock, a third wiring supplying a second clock signal to the macroblock, and Arranging a fourth wiring for supplying a second clock signal to the second functional block (c).

A semiconductor device designing method according to a third aspect of the present invention receives a first clock signal, operates in synchronization with the first clock signal, and synchronizes with the first clock signal. The step (a) of arranging a first functional block that outputs a data signal that changes according to
And a digital signal which receives the second clock signal, latches the data signal output from the first functional block in synchronization with the first clock signal, and outputs the latched signal in synchronization with the second clock signal. A processing circuit and a second functional block that receives the second clock signal, operates in synchronization with the second clock signal, and receives the output signal of the digital signal processing circuit in synchronization with the second clock signal. Arranging the containing macroblock (b), a first wiring connecting the output of the first functional block and the data input of the macroblock, and a second wiring for supplying the first clock signal to the first functional block. Arranging a wiring, a third wiring for supplying the first clock signal to the macroblock, and a fourth wiring for supplying the second clock signal to the macroblock (c) Comprising.

Here, the digital signal processing circuit may output the latched signal in synchronization with the second clock signal and also in synchronization with the first clock signal.

According to the above configuration, the digital signal processing circuit latches the signal that changes in synchronization with the first clock signal in synchronization with the first clock signal and the latched signal in the second clock signal. Since the output is performed in synchronization with, it is possible to prevent malfunction of the semiconductor device and reduce the load on the designer who designs the timing of the semiconductor device.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals. In Figure 1,
1 shows a semiconductor device according to a first embodiment of the present invention. Figure 1
In the semiconductor device 1, the first and second cores 2, 3
And a digital signal processing circuit 4.

The first and second cores 2 and 3 are circuit blocks that realize predetermined functions, for example, a CPU.
(Central Processing Unit), DSP (Digital Signa)
l Processor) etc. The first core 2 receives the first clock signal, performs a predetermined operation in synchronization with the first clock signal, and outputs the signal at the timing of the falling edge of the first clock signal. The output signal of the first core 2 is input to the data input terminal D of the digital signal processing circuit 4.

The digital signal processing circuit 4 receives the first clock signal at the first clock input terminal C1 and at the second clock input terminal C2 the second clock signal having a frequency higher than that of the first clock signal. To receive. Then, the digital signal processing circuit 4 samples and latches the output signal of the first core 2 at the timing of the rising edge of the first clock signal, and latches the latched signal at the timing of the rising edge of the second clock signal. Output from the output terminal Q. The output signal of the digital signal processing circuit 4 is input to the second core 3.

The second core 3 receives the second clock signal, samples the output signal of the digital signal processing circuit 4 at the timing of the falling edge of the second clock signal, and synchronizes with the second clock signal. Then, a predetermined operation is performed.

FIG. 2 is a timing chart showing the operation timing of the digital signal processing circuit 4. The operation of the digital signal processing circuit 4 will be described below with reference to FIG.

As shown in FIG. 2, the first clock signal rises at times t ₁ , t ₅ , t ₉ , and t ₁₃ , and at time t ₃ ,
t _7, t _11, t falls at _15. The second clock signal rises at time _{t 2, t 6, t 10} , t 14, falls at time _{t 4, t 8, t 12} , t 16. Where core 2
However, when a high level signal is output at time t ₃ , the digital signal processing circuit 4 at time t ₅
This signal is sampled. Then, the digital signal processing circuit 4 outputs a high level signal at time t ₆ . At time t ₈ , the output signal of the digital signal processing circuit 4 is stable at a high level, and the core 3
This signal can be sampled reliably.

Next, when the core 2 outputs a low level signal at time t ₇ , the digital signal processing circuit 4
Samples this signal at time t ₉ .
Then, the digital signal processing circuit 4 outputs a low level signal at time t ₁₀ . At time t ₁₂ ,
The output signal of the digital signal processing circuit 4 is stable at a high level, and the core 3 can reliably sample this signal.

As described above, according to the semiconductor device 1, the digital signal processing circuit 4 outputs the output signal of the core 2 which changes at the timing of the falling edge of the first clock signal to the rising edge of the first clock signal. The latched signal is output at the timing of the rising edge of the second clock signal. for that reason,
The core 3 can reliably sample the output signal of the digital signal processing circuit 4, and can prevent malfunction of the semiconductor device 1.

FIG. 3 is a flowchart showing the method for designing a semiconductor device according to this embodiment. Hereinafter, a method for designing the semiconductor device 1 will be described with reference to FIG. First, the core 2 is arranged (step S11), then the digital signal processing circuit 4 is arranged (step S12), and the core 3 is further arranged (step S13). Then, a wiring that connects the core 2 and the digital signal processing circuit 4, a wiring that connects the digital signal processing circuit 4 and the core 3, a wiring that supplies a clock signal to the cores 2, 3 and the digital signal processing circuit 4 are arranged ( Step S14).

In this way, the load on the designer who designs the timing of the semiconductor device can be reduced. further,
Since the signal used by the core 3 can be generated by the single digital signal processing circuit 4, the load on the designer who designs the layout of the semiconductor device can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a semiconductor device according to the second embodiment of the present invention. In FIG. 4, the semiconductor device 5 includes a core 3
And a macro block 6. Macro block 6
Includes a core 2 and a digital signal processing circuit 4. In this way, the core 2 and the digital signal processing circuit 4 may be included in one macro block 6.

FIG. 5 is a flow chart showing a method for designing a semiconductor device according to this embodiment. Hereinafter, a method for designing the semiconductor device 5 will be described with reference to FIG. First, the macro block 6 is arranged (step S21), and then the core 3 is arranged (step S22). Then, the wiring that connects the macroblock 6 and the core 3 and the wiring that supplies the clock signal to the macroblock 6 and the core 3 are arranged (step S23).

As described above, if the core 2 and the digital signal processing circuit 4 are included in one macro block 6, the load on the designer who designs the layout of the semiconductor device can be further reduced.

Next, a third embodiment of the present invention will be described. FIG. 6 shows a semiconductor device according to the third embodiment of the present invention. In FIG. 6, the semiconductor device 7 has a core 2
And a macroblock 8. Macro block 8
Includes a core 3 and a digital signal processing circuit 4. Thus, the core 3 and the digital signal processing circuit 4 may be included in one macro block 8.

FIG. 7 is a flowchart showing the method for designing a semiconductor device according to this embodiment. Hereinafter, a method for designing the semiconductor device 7 will be described with reference to FIG. First, the core 2 is arranged (step S31), and then the macro block 8 is arranged (step S32). And
Wiring for connecting the core 2 and the macro block 8 and wiring for supplying a clock signal to the core 2 and the macro block 8 are arranged (step S33).

As described above, if the core 3 and the digital signal processing circuit 4 are included in one macro block 8, the load on the designer who designs the layout of the semiconductor device can be further reduced.

Next, a fourth embodiment of the present invention will be described. FIG. 8 shows a semiconductor device according to the fourth embodiment of the present invention. In FIG. 8, a semiconductor device 9 includes a first core 10, a second core 3 and a digital signal processing circuit 1.
1 and.

The first core 10 is a circuit block that realizes a predetermined function, and is, for example, a CPU, a DSP, or the like.
The first core 10 receives the first clock signal and outputs the first clock signal.
A predetermined operation is performed in synchronization with the clock signal, and the signal is output at the timing of the falling edge of the first clock signal. Further, the first core 10 receives the first data output (Q1 output) of the digital signal processing circuit 11 in synchronization with the first clock signal. The output signal of the first core 10 is input to the data input terminal D of the digital signal processing circuit 11.

The digital signal processing circuit 11 receives the first clock signal at the first clock input terminal C1 and the first clock signal at the second clock input terminal C2.
The second clock signal having a frequency higher than that of the first clock signal is received, and the output signal of the first core 10 is sampled and latched at the timing of the rising edge of the first clock signal. Then, the digital signal processing circuit 11
The latched signal is output as the first data output (Q1 output) from the first output terminal Q1 to the core 10 at the timing of the rising edge of the first clock signal. Further, the digital signal processing circuit 11 outputs the latched signal as the second data output (Q2 output) from the second output terminal Q2 to the core 3 at the timing of the rising edge of the second clock signal.

As described above, according to the semiconductor device 9, the digital signal processing circuit 11 outputs the latched signal to the core 1 at the timing of the rising edge of the first clock signal.
In addition to outputting to 0, it is output to the core 3 at the timing of the rising edge of the second clock signal. Therefore, since the signal used by the core 3 and the signal used internally by the core 10 can be generated by one digital signal processing circuit 11, the load on the designer who designs the layout of the semiconductor device 1 is reduced. can do.

[0039]

As described above, according to the present invention, a signal that changes in synchronization with the first clock signal is latched in synchronization with the first clock signal, and the latched signal is used in the second clock signal. Since the signal is output in synchronization with the signal, malfunction of the semiconductor device can be prevented, and the load on the designer who designs the timing of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation timing of the digital signal processing circuit 4 of FIG.

FIG. 3 is a flowchart showing a method for designing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a method for designing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing a method for designing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a conventional semiconductor device.

10 is a timing chart showing the operation timing of the D-type flip-flop 14 of FIG.

[Explanation of symbols]

1, 5, 7, 9, 21 Semiconductor device 2,3,10,22,23 core 4, 11 Digital signal processing circuit 6,8 macroblocks 24 D-type flip-flop

Claims (9)

[Claims] 1. A first data signal and a second data signal having different frequencies are received, and a data signal that changes in synchronization with the first clock signal is latched and latched in synchronization with the first clock signal. A digital signal processing circuit, which outputs a signal in synchronization with the second clock signal. 2. The digital signal processing circuit according to claim 1, wherein the latched signal is output in synchronization with the second clock signal and is output in synchronization with the first clock signal. . 3. A first signal receiving the first clock signal, operating in synchronization with the first clock signal, and outputting a data signal that changes in synchronization with the first clock signal.
3. The digital signal processing circuit according to claim 1 or 2, which latches the data signal output by the first functional block, and outputs the latched signal, and the second clock signal, A second functional block which operates in synchronization with a second clock signal and receives an output signal of the digital signal processing circuit in synchronization with the second clock signal. 4. The semiconductor device according to claim 3, wherein the first functional block and the digital signal processing circuit are included in one macro block. 5. The semiconductor device according to claim 3, wherein the second functional block and the digital signal processing circuit are included in one macro block. 6. A first clock signal is received and the first clock signal is received.
(A) arranging a first functional block that operates in synchronization with the clock signal and outputs a data signal that changes in synchronization with the first clock signal; Receive a clock signal,
Arranging a digital signal processing circuit for latching a data signal output from the first functional block in synchronization with the first clock signal and outputting the latched signal in synchronization with the second clock signal ( b) and a second signal receiving the second clock signal, operating in synchronization with the second clock signal, and receiving an output signal of the digital signal processing circuit in synchronization with the second clock signal. (C) arranging the functional block of the first functional block, first wiring connecting the output of the first functional block and the data input of the digital signal processing circuit, the data output of the digital signal processing circuit and the second wiring. Second wiring for connecting the data input of the functional block, third wiring for supplying the first clock signal to the first functional block, digital signal processing A fourth wiring for supplying the first clock signal to the circuit, a fifth wiring for supplying the second clock signal to the digital signal processing circuit, and the second clock for the second functional block. And a step (d) of arranging a sixth wiring for supplying a signal. 7. A first clock signal is received and the first clock signal is received.
A first functional block that operates in synchronization with the first clock signal and outputs a data signal that changes in synchronization with the first clock signal, and receives first and second clock signals having different frequencies, A macro block including a digital signal processing circuit for latching a data signal output from a first functional block in synchronization with the first clock signal and outputting the latched signal in synchronization with the second clock signal is arranged. And (a) to receive the second clock signal, operate in synchronization with the second clock signal, and receive the output signal of the digital signal processing circuit in synchronization with the second clock signal. (B) arranging a second functional block to perform, and a first wiring for connecting the data output of the macroblock and the data input of the second functional block, A second wiring for supplying the first clock signal to the macroblock, a third wiring for supplying the second clock signal to the macroblock, and the second clock signal for the second functional block And (c) arranging a fourth wiring for supplying the semiconductor device. 8. A first clock signal is received and the first clock signal is received.
(A) arranging a first functional block that operates in synchronization with the clock signal and outputs a data signal that changes in synchronization with the first clock signal; Receive a clock signal,
A digital signal processing circuit for latching a data signal output from the first functional block in synchronization with the first clock signal, and outputting the latched signal in synchronization with the second clock signal, and the second signal processing circuit. , A macro block including a second functional block that operates in synchronization with the second clock signal and receives an output signal of the digital signal processing circuit in synchronization with the second clock signal. Arranging step (b), a first wiring for connecting the output of the first functional block and the data input of the macroblock, and a second wiring for supplying the first clock signal to the first functional block Wiring of
A step (c) of arranging a third wiring for supplying the first clock signal to the macroblock and a fourth wiring for supplying the second clock signal to the macroblock. Equipment design method. 9. The digital signal processing circuit outputs the latched signal in synchronization with the second clock signal, and outputs the latched signal in synchronization with the first clock signal. 9. The method for designing a semiconductor device according to any one of 6 to 8.