JP2003273348A - Method for forming diffuse barrier layer in semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for preventing dopant boron from being diffused from a gate electrode to a channel area and a semiconductor device. <P>SOLUTION: A silicon nitride barrier layer for preventing the diffusion of in-gate electrode layer impurity is formed by the chemical reaction of tetrachlorosilane and ammonia between a gate electrode layer and a gate dielectric layer with a high dielectric coefficient. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of MOS field effect transistor (MOSFET) devices.
A method of forming a diffusion barrier layer in a CMOS device having a boron-doped gate in the MOS section.

[0002]

2. Description of the Related Art CMOS circuits are commonly known as integrated circuits using nMOS and pMOS devices. Conventional CM
In the OS device, the n ⁺ gate electrode is formed for each of the nMOS portion and the pMOS portion by phosphorus doping. When the channel is short, that is, 0.25 μm or less, it is necessary to use a p ⁺ -doped polycrystalline silicon gate electrode by boron doping in the pMOS portion in order to minimize the short channel effect. Therefore, a p-channel MOS having a p-type gate electrode and an n-channel MOS having an n-type gate electrode
A CMOS device consisting of and is called a two-gate CMOS.

In the past, there has been a proposal to use a good gate electrode dielectric material to solve the problem of shrinkage in thermal oxide gate dielectrics below 70 nm level. A good gate electrode dielectric material here is a high dielectric constant (high-k,
Dielectric material (high dielectric constant), eg ZrO ₂ , HfO ₂ , Al ₂ O
₃ are listed. Boron diffusion has been a bottleneck in the formation of two-gate CMOS devices using high dielectric constant gate electrodes.

That is, in the pMOS portion, boron may diffuse from the gate electrode to the channel region through the dielectric material having a high dielectric constant during the heat treatment. When boron infiltrates into the channel region, low field hole mobility (low field ho
Le mobility) may become low and initial voltage (Vt) may drop. Therefore, how to form a two-gate CMOS device using a high-dielectric-constant dielectric material and preventing infiltration of boron is an issue to be solved.

[0005]

SUMMARY OF THE INVENTION To solve the above problems, a first object of the present invention is to provide a method of forming a diffusion barrier layer for preventing the infiltration of boron in a semiconductor device. Especially.

A second object of the present invention is to provide a semiconductor device in which a diffusion barrier layer is formed in a gate structure to prevent impurity diffusion from the gate electrode.

[0007]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a silicon nitride (tetrachlorosilane-) by a chemical reaction using tetrachlorosilane as a reactant between a gate electrode layer and a gate dielectric layer having a high dielectric constant. based
It is characterized by forming a silicon nitride (TCS-SiN) layer.

Such a TCS-SiN layer prevents impurities such as boron from diffusing (penetrating) from the gate electrode into the substrate. The TCS-SiN layer is a silicon nitride (dichlorosi) produced by chemical reaction using conventional dichlorosilane as a reactant.
Unlike a lane-based silicon nitride (DCS-SiN) layer, that is, it does not decompose and generate hydrogen during the high temperature manufacturing stage.

Specifically, a method of forming a diffusion barrier layer in a semiconductor device according to the present invention for achieving the first object comprises a step of forming a gate dielectric layer having a high dielectric constant on a substrate, and the gate dielectric layer. And a step of forming a silicon nitride barrier layer for preventing diffusion of impurities in a gate electrode layer to be subsequently formed by a chemical reaction between tetrachlorosilane and ammonia by using a CVD method.

The semiconductor device of the present invention for achieving the second object is located between a gate electrode layer and a gate dielectric layer having a high dielectric constant and prevents diffusion of impurities in the gate electrode layer. A semiconductor device having a silicon nitride barrier layer, wherein the silicon nitride barrier layer is formed by utilizing a CVD method and by a chemical reaction between tetrachlorosilane and ammonia.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The structure and operation of an embodiment of the present invention which achieves the above-mentioned object and solves the problems of the prior art will be described in detail with reference to the accompanying drawings.

1 to 5 are views showing manufacturing steps of a pMOS transistor manufacturing method according to an embodiment of the present invention.

For simplification of the description, in this embodiment, only the structure of the pMOS portion of the two-gate CMOS device will be described, but those skilled in the art can easily think of the structure of the nMOS from the structure of this pMOS device. be able to. For example, the pMOS can be easily formed from the nMOS by exchanging the impurities having different conductivity types.

FIG. 1 shows a partial cross section of the semiconductor substrate 10. The substrate 10 is made of shallow-doped n-type single crystal silicon. First, the substrate 10 is annealed, for example, in an environment of NH ₃ or NO to form a thin nitride layer 12 of 3-10 Å on the substrate 10. The nitride layer 12 is usually composed of silicon nitride or silicon oxide.

Next, a dielectric material having a high dielectric constant (k) is deposited on the nitride layer 12 to form a gate dielectric layer 1 having a thickness of 20-200Å.
4 is formed. The gate dielectric layer 14 has ak value of 8-100.
It is 0 and is composed of a metal oxide and a silicate. Here, as the metal oxide, ZrO ₂ , HfO ₂ , AL ₂ O ₃ , T
Examples include iO ₂ and Ta ₂ O ₃ . On the other hand, examples of the silicate include ZrSiO ₄ and HfSiO ₄ . In addition, as a method of forming the gate dielectric layer 14, a low pressure CVD (chemical vapor deposition) method, a metal organic chemical vapor deposition method, a jet type vapor deposition (jet vap depos
ition) method, sputter deposition method and the like. In this embodiment, the gate dielectric layer 14 is formed by depositing a metal film and then annealing in an environment having oxygen gas.

Next, as shown in FIG. 2, the gate dielectric layer 1
4 is formed, a thin silicon nitride layer 16 having a thickness of 5-20Å is formed as a barrier layer. The thin silicon nitride layer 16 can significantly prevent impurities (for example, B, P, As) from seeping into the substrate 10. The silicon nitride layer 16 is formed by using the CVD method and tetrachlorosilane (t
It is formed by a chemical reaction between etrachlorosilane) and ammonia (NH ₃ ) (hereinafter, the silicon nitride layer is referred to as a TCS-SiN layer). The TCS-SiN layer 16 formed in this way has good thermal stability as compared with a conventional one obtained by a chemical reaction between dichlorosilane and NH ₃ (hereinafter referred to as a DCS-SiN layer). This can be seen from Figures 6 and 7.

FIG. 6 shows the SiH bond concentration in the DCS-SiN layer (c
is a curve showing the relationship between ontent) and anneal (RTA) temperature. Figure 7 shows the NH bond concentration in the TCS-SiN layer and
2 is a curve showing the relationship with the temperature of the base.

As can be seen from FIG. 6, the Si—H bond in the DCS-SiN layer decomposes at a high temperature to release hydrogen, which promotes diffusion (or seepage) of boron.

On the other hand, as seen from FIG. 7, the NH bond in the TCS-SiN layer is stable even when the temperature rises to 1050 ° C.
Therefore, the TCS-SiN layer is not decomposed and hydrogen is not generated in the subsequent high temperature manufacturing stage.

In this embodiment, the TCS-SiN layer 16 is 725 ° C.-8
It is formed by a low pressure CVD (LPCVD) method at a temperature of 25 ° C.

Next, as shown in FIG. 3, the gate electrode layer 18 is used as the gate electrode of the MOS transistor to form the TCS-SiN layer 1.
6 to form. The material of the gate electrode layer 18 may be various conductive materials, but polycrystalline silicon is most suitable. When the gate electrode layer 18 is made of polycrystalline silicon,
It is formed by a known method such as a CVD method. In this embodiment, the gate electrode layer 18 has a thickness of 7 at a temperature of 625 ° C. or higher.
It is formed by forming polycrystalline silicon having a thickness of 50-1800Å, and becomes a conductive layer after a subsequent ion implantation step (step for forming source / drain regions).

Next, as shown in FIG. 4, the gate electrode layer 18, the TCS-SiN layer 16 and the gate dielectric layer 14 are etched by an etching method.
And defining the gate structure 20 by patterning the nitride layer 12. Here, as an etching method,
Active ion etching method, chemical plasma etching method,
Alternatively, another anisotropic etching method may be used.

Next, as shown in FIG. 5 (arrow 21), ion implantation is performed to form the source / drain regions 22.
And the gate electrode layer 18 is changed to a conductive layer. In this example, p-type impurities (eg B or BF ₂ )
To form a pMOS transistor.

When forming an nMOS transistor, the implanted impurities are n-type impurities (such as As or
P) is used.

In the case of the above-mentioned ion implantation, the gate structure 2
Since 0 is used as a mask, the source / drain regions 22 formed on the substrate 10 are located on both sides of the gate structure 20, and the channel region 24 is formed below the gate structure 20, that is, between the source / drain regions 22. It Note that such ion implantation is performed, for example, with a dose amount of 5 × 10 ¹⁴ −5 ×
It is performed with 10 ¹⁵ atoms / cm ² and an implantation energy of 2-80 keV.

The activation of the source / drain regions 22 is performed at the same time as one or more other high temperature manufacturing steps. Usually, this activation is done with the metallization manufacturing stage. Further, here, if necessary, the source / drain regions 22 may be annealed. For example, temperature
Perform RTA (rapid annealing) at 900 ° C-1075 ° C for 30-60 seconds and in an environment of an inert gas such as argon gas, helium gas or nitrogen gas.

During the high temperature manufacturing step described above, there is a tendency for impurities (eg, B or other) in the gate electrode layer 18 to diffuse into the channel region 14 through the gate dielectric layer 14. Since the TCS-SiN layer 16 located between the dielectric layers 14 almost blocks the diffusion path, that is, serves as a diffusion barrier, the impurities are prevented from penetrating into the channel region 24.

Through the manufacturing steps of the above-described embodiment of the present invention, a pMOS transistor having a gate dielectric layer having a high dielectric constant and capable of preventing the infiltration of impurities is formed. Therefore, the present invention is most suitable for manufacturing a two-gate CMOS device that requires a boron-doped gate electrode in the pMOS section.

FIG. 8 is a diagram showing the structure of a two-gate CMOS device having a TCS-SiN barrier layer according to an embodiment of the present invention. Here, the same parts as those in the embodiment shown in FIGS. 1 to 5 are represented by the same reference numerals, and the description thereof will be omitted.

In FIG. 8, the CMOS device 2 has well regions 4 and 6 which are active regions of an nMOS transistor and a pMOS transistor. In this embodiment, the surface of the semiconductor substrate 10 has a two-tub active region having different conductivity.
That is, the p well region 4 and the n well region 6 are formed.
The structure of the well region is not limited to that shown in this embodiment.

The two transistor regions are separated by a trench 8 formed at the interface between the two transistors.
In such a two-gate CMOS device 2, since the conductivity type of the gate electrode of the MOS transistor is the same as that of the channel, the gate electrode 18 in the pMOS portion is doped with boron or other p-type impurities.
The gate electrode 18 in the nMOS portion is doped with P, As or other n-type impurities. The TCS-SiN layer 16 in the gate structure 20 can prevent impurities, particularly boron, from seeping into the channel.

Although the present invention has been presented as the above embodiment, this is not intended to limit the present invention, and those skilled in the art can make variations and modifications within the spirit and scope of the present invention.

[0033]

According to the present invention, the formation of the TCS-SiN layer between the gate electrode layer and the gate dielectric layer having a high dielectric constant prevents impurities from diffusing from the gate electrode to the channel region. It Therefore, it is possible to suppress a decrease in initial voltage and low electric field hole mobility.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a pMOS transistor manufacturing method according to an embodiment of the present invention.

2 is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 3 is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 4 is a cross-sectional view showing a step subsequent to the step shown in FIG.

5 is a cross-sectional view showing a step subsequent to the step shown in FIG.

FIG. 6 is a curve showing the relationship between the SiH bond concentration and the annealing temperature in the DCS-SiN layer.

FIG. 7 is a curve showing the relationship between the NH bond concentration in the TCS-SiN layer and the annealing temperature.

FIG. 8 is a diagram showing a configuration of a two-gate CMOS device having a gate structure provided with a TCS-SiN barrier layer according to an embodiment of the present invention.

[Explanation of symbols]

2 CMOS device 4 p-well 6 n-well 8 trench 10 Semiconductor substrate 12 Nitride layer 14 High dielectric constant gate dielectric layer 16 TCS-SiN layer 18 Gate electrode layer 20 gate structure 21 ion implantation 22 Source / drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/49 (72) Inventor Shi Chun Sung Taiwan, Taipei, Wusin Street, Lane 600, No. 32 F term (reference) 4M104 AA01 BB01 BB40 EE03 EE16 EE17 GG09 HH20 5F048 AC03 BA01 BB06 BB07 BB11 BB12 BB14 BE03 BG14 5F058 BA05 BD02 BD10 BF04 BJ04 5F140 AA28 AB03 AC01 BA01 BD02 BD07 BD09 BD11 BD12 BD13 BE07 BE09 BE10 BF01 BF04 BG28 BG38 BG43 BG44 BG56 BK13 BK21 CB08 CF07

Claims (14)

[Claims] 1. Forming a gate dielectric layer having a high dielectric constant on a substrate, and forming a gate electrode layer on the gate dielectric layer by a CVD method and a chemical reaction of tetrachlorosilane and ammonia. Forming a diffusion barrier layer in a semiconductor device, which comprises forming a silicon nitride barrier layer for preventing diffusion of impurities therein. 2. The dielectric constant of the gate dielectric layer is 8-1000.
The method for forming a diffusion barrier layer in a semiconductor device according to claim 1, wherein 3. The method of forming a diffusion barrier layer in a semiconductor device according to claim 1, wherein the gate dielectric layer is formed of metal oxide or silicate. 4. The silicon nitride barrier layer has a thickness of 5-20.
4. The method for forming a diffusion barrier layer in a semiconductor device according to claim 1, wherein the diffusion barrier layer is Å. 5. The diffusion in a semiconductor device according to claim 1, wherein the silicon nitride barrier layer is formed by using a LPCVD method and at 725 ° C.-825 ° C. Method of forming barrier layer. 6. The semiconductor device as claimed in claim 1, wherein a step of forming a nitride layer on the substrate is performed before the step of forming the gate dielectric layer. Method of forming diffusion barrier layer. 7. A semiconductor device comprising a silicon nitride barrier layer which is located between a gate electrode layer and a gate dielectric layer having a high dielectric constant and which blocks diffusion of impurities in the gate electrode layer. Is a semiconductor device characterized by being formed by a chemical reaction between tetrachlorosilane and ammonia using the CVD method. 8. The dielectric constant of the gate dielectric layer is 8-1000.
The semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 7, wherein the gate dielectric layer is formed of metal oxide or silicate. 10. The silicon nitride barrier layer has a thickness of 5-
The semiconductor device according to any one of claims 7 to 9, wherein the semiconductor device has a length of 20Å. 11. The semiconductor device according to claim 7, wherein the silicon nitride barrier layer is formed by using a LPCVD method and at 725 ° C. to 825 ° C. 12. The semiconductor device according to claim 7, wherein the semiconductor device is a pMOS transistor having a p-type gate electrode. 13. The semiconductor device according to claim 7, wherein the semiconductor device is an nMOS transistor having an n-type gate electrode. 14. The semiconductor device according to claim 7, wherein the semiconductor device is a CMOS including a pMOS transistor having a p-type gate electrode and an nMOS transistor having an n-type gate electrode. The semiconductor device according to.