JP2003270371A - Clock device in computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a systematically well-matched clock device in a computer system, not generating inverted phenomenon or jump of a time. <P>SOLUTION: A first clock 12a counts the output of a first frequency dividing circuit 14a wherein an originated frequency of a clock of an oscillator 13 is divided by a prescribed frequency dividing ratio, and ticks for external processing. A second clock 12b counts the output of a second frequency dividing circuit 14b wherein the originated frequency of the clock of the oscillator 13 is divided by a prescribed frequency dividing ratio, and ticks for internal processing. A time correction processing part 15 corrects times of the first clock 12a and the second clock 12b to the reference time of a reference clock 17. Thereby, time correction of the first clock 12a is performed so as to be fit for the external processing, and time correction of the second clock 12b is performed so as to be fit for the internal processing. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timepiece device of a computer system that keeps a processing time of each device constituting the computer system.

[0002]

2. Description of the Related Art A plurality of clocks are provided in a computer system to manage the processing time of each device or the entire system. A plurality of clocks may be provided for each station across the LAN, or a plurality of clocks may be provided in one device regardless of the LAN. For example, multiple arithmetic processing units (CPU) in one device
In many cases, a clock is also provided for each CPU. Further, the management device of one CPU may also have an IC for exclusive use of a clock and a clock created (managed) by processing of a fixed period.

As a matter of course, if the stations are different, a plurality of clocks in the same device often have different clock sources (for example, crystal oscillators) for each clock. Since there is always a difference in precision between these clocks, there is a difference in precision between these clocks, but there is always a time difference. The time difference causes various inconveniences in the system. Therefore, in a device that operates continuously (or operates for a long period of time), this time difference is managed so as to be within a range that does not cause a problem. That is, the time is adjusted between these clocks.

As a method of keeping the time difference between clocks within a certain range, when a certain time interval or a time difference becomes a certain value or more, time adjustment (correction) is performed with reference to the time of any one of the clocks. There is. In this case, when the time is adjusted, the reference value is written in the timepiece to be corrected.

For example, the value of the reference clock (reference clock) is "September 22, 2001 11: 28: 28: 10", and the value of the corrected clock (process clock) is "200".
In the case of 11: 28: 28: 15 on September 22, 1st, the second is rewritten to "10 seconds". In this way, the time is corrected and the processed clock is adjusted to the time of the reference clock.

[0006]

However, when the processing clock is ahead of the reference clock, the time is set back.
If the processing clock is behind the reference clock, a time jump occurs.

For example, when the time is corrected while the processing clock is ahead of the reference clock by 5 seconds, the time is returned by 5 seconds. Time correction from "15 seconds" to "10
If it is corrected to "second", only the second value of the processing clock is set to 1
It looks like the following every second.

[0008] That is, the underlined portion in the first half, which is the time before correction, and the underlined portion in the latter half, which is the time after correction, overlap with each other, which causes a problem. For example, when the data collection processing is performed at a certain time, the same time is passed twice, so the data is collected again by the time correction, and the previously stored storage area is overwritten. If the information to be stored in the storage area is the data (instantaneous value) of the collection time such as analog signal or digital signal, it will not cause any problem, but when storing the increment value from the last collection time to the current collection time, A situation will occur in which an incorrect increment value is stored (overwritten).

Further, if the correction is applied in a state where the processing clock is delayed by 5 seconds from the reference clock, a jump of 5 seconds occurs. Assuming that the time correction is corrected from "5 seconds" to "10 seconds", the following is the case where only the seconds value of the processing clock is seen every 1 second.

[0010] In particular, in the case of a system having a function of collecting data with time, if a time jump occurs, if there is data to be collected at the jumped time, the data at that time will be lost.

Therefore, for the time return (time reversal phenomenon), the time width associated with the time adjustment is calculated. If the time width is large, the already stored (first time) data is invalidated, and the The second data is validated.
That is, when passing the second collection time, even if the data is already collected, the data is collected again and overwritten in the already stored area. On the other hand, when the time width is small, a method is often used in which the already stored (first collected) data is valid and no processing is performed at the second collection time. Also, if you are jumping in time,
It means that the processing of the time to jump over is processed collectively.

As described above, the program processing associated with the time inversion phenomenon and the jump is complicated. Further, when the operation at that time is recorded (history) with time, the time difference between the two operations with the time correction interposed cannot be known only by looking at the operation record. If the time is corrected frequently, the above inconvenience can be prevented, but the processing amount for that purpose is increased, and other truly necessary processing is stressed.

An object of the present invention is to provide a timepiece device for a computer system that is systematically harmless without causing a time reversal phenomenon or a jump.

[0014]

According to another aspect of the present invention, there is provided a timepiece device for a computer system, wherein an oscillator for oscillating a clock at a predetermined oscillation frequency and an oscillation frequency of the clock of the oscillator are divided by a predetermined division ratio. A first frequency dividing circuit for dividing the frequency, a first clock for counting the output of the first frequency dividing circuit and marking a time for external processing, and a frequency of oscillation of the clock of the oscillator divided by a predetermined frequency division ratio. A second frequency divider circuit that performs a frequency division, a second clock that counts the output of the second frequency divider circuit and marks the time for internal processing, and the times of the first clock and the second clock are corrected. And a time correction processing unit.

In the timepiece device of the computer system according to the first aspect of the present invention, the first timepiece counts the output of the first frequency dividing circuit obtained by dividing the oscillation frequency of the clock of the oscillator by a predetermined frequency division ratio. The second clock counts the output of the second frequency divider circuit, which is obtained by dividing the oscillation frequency of the clock of the oscillator by a predetermined dividing ratio, and sets the time for internal processing. Carve. Then, the time correction processing unit corrects the times of the first clock and the second clock to the reference time of the reference clock. This makes it possible to adjust the time independently of the first clock and the second clock, the first clock corrects the time to be suitable for external processing, and the second clock adjusts for internal processing. Adjust the time suitable for.

According to a second aspect of the present invention, there is provided a timepiece device for a computer system according to the first aspect of the invention, wherein the time adjustment processing unit sets a frequency division ratio for the first timepiece when the time adjustment start time comes. Immediately adjust the reference time at the time of the time adjustment start, while keeping it fixed, and operate the second clock at a division ratio that takes into account the time deviation from the reference clock at the time adjustment start time and gradually When the time of the second clock is corrected and the time of the second clock matches the time of the first clock, the division ratio of the second clock is made the same as the division ratio of the first clock. To do.

In a timepiece device of a computer system according to a second aspect of the invention, in addition to the operation of the first aspect of the invention, the time correction processing section has a frequency division ratio of the first frequency dividing circuit for the first timepiece. The time of the first clock is immediately corrected to the reference time at the time of starting the time correction while keeping the fixed. on the other hand,
The second timepiece is operated at a frequency division ratio in consideration of the time difference from the reference timepiece at the time of starting the time adjustment, and the time of the second timepiece is gradually adjusted at a constant ratio. Then, when the time of the second clock matches the time of the first clock, the frequency division ratio of the second clock is made the same as the frequency division ratio of the first clock. This allows
The second clock for internal processing adjusts the time gradually at a constant rate, so that the time inversion phenomenon and the jump are prevented.

According to a third aspect of the present invention, there is provided a timepiece device for a computer system according to the second aspect, wherein the time adjustment processing unit periodically specifies when the second timepiece is adjusting the time. The second timepiece is operated by returning the frequency division ratio during the normal operation to the time zone in which the program for performing the process of (1) operates.

In the timepiece device of the computer system according to the third aspect of the invention, in addition to the operation of the second aspect of the invention, the time adjustment processing section is normally operated when a program for periodically performing a specific operation operates. Since the time is divided by the frequency division ratio during operation, the arithmetic processing of the processing program is not hindered.

According to a fourth aspect of the present invention, there is provided a timepiece device for a computer system according to the second aspect, wherein the time adjustment processing section is the first time adjustment start point preset in the time adjustment processing section. If the time of the clock is corrected and the time adjustment start time point is the operating time zone of the program that periodically executes the specific processing, the time of the second clock is corrected after the time zone has elapsed. Characterize.

In the timepiece device of the computer system according to the fourth aspect of the invention, in addition to the operation of the second aspect of the invention, the time adjustment processing section causes the time adjustment operation to be performed when a predetermined time adjustment start time is reached. To start. in this case,
When the time adjustment start time point is the operation time zone of the program that periodically executes the specific process, the time of the second clock is adjusted after the time zone has elapsed. As a result, the operation of the processing program is prevented from being used.

According to a fifth aspect of the present invention, there is provided a timepiece device for a computer system according to the second aspect, wherein the time adjustment processing section adjusts the time of the second timepiece to the time of the next time adjustment or It is characterized in that the second timepiece is operated at a frequency division ratio such that the time adjustment is completed at a time near that time.

In the timepiece device of the computer system according to the invention of claim 5, in addition to the operation of the invention of claim 2, the time adjustment processing section completes the time adjustment at the time of the next time adjustment or a time in the vicinity thereof. Second with a division ratio that
Operate the clock. As a result, the error in time increments between the time of the time adjustment period and the time of the reference clock becomes small.

According to a sixth aspect of the present invention, there is provided a timepiece device of a computer system according to the first aspect of the invention, wherein the reference timepiece is each device constituting the computer system,
Alternatively, it is provided in the host of the system.

In the timepiece device of the computer system according to the invention of claim 6, in addition to the operation of the invention of claim 1, when the host of the system has a reference clock, the reference time is adjusted by the transmission means. When each device has a reference clock, the reference time is input from each reference clock to the time adjustment processing unit.

According to a seventh aspect of the present invention, there is provided a timepiece device for a computer system according to the first aspect, wherein the first timepiece is provided with a battery that supplies power even during a power outage. However, it is characterized in that the second clock is stopped at the time of power failure and the time at the time of power failure is saved.

In the timepiece device of the computer system according to the invention of claim 7, in addition to the operation of the invention of claim 1, at the time of a power failure, the time is ticked by the power source from the first clock battery and the second clock is stopped. Save the time when the power failure occurred.

According to an eighth aspect of the present invention, in the timepiece device of the computer system according to the seventh aspect, the time correction processing unit sets the time of the first clock to the time of the reference clock when the power is restored from a power failure. It is characterized by matching with.

In the timepiece device of the computer system according to an eighth aspect of the present invention, in addition to the operation of the seventh aspect of the invention, the time correction processing unit sets the time of the first timepiece as the reference time when the power is restored from a power failure. Set to the time. As a result, when power is restored, the time is always adjusted to the reference time.

According to a ninth aspect of the present invention, there is provided a timepiece device of a computer system according to the first aspect, wherein the time adjustment processing unit sets the time of the first clock and the time of the second clock at the time of power-on. If there is a time lag in the clock, the second clock is operated at a division ratio that takes the time lag between the first clock and the second clock into consideration, and the time of the second clock is gradually corrected at a constant rate. When the time of the second clock matches the time of the first clock, the frequency division ratio of the second clock is set to be the same as the frequency division ratio of the first clock.

In the timepiece device of the computer system according to the ninth aspect of the invention, in addition to the operation of the first aspect of the invention, there is a time lag between the time of the first clock and the time of the second clock when the power is turned on. In this case, the time adjustment processing unit determines the second frequency division ratio based on the time division between the first clock and the second clock.
Operate the clock. As a result, the time of the second clock is gradually corrected at a constant rate. Then, when the time of the second clock matches the time of the first clock, the frequency division ratio of the second clock is made the same as the frequency division ratio of the first clock. As a result, the time of the first clock and the time of the second clock are always set when the power is turned on.

According to a tenth aspect of the present invention, there is provided a timepiece device for a computer system according to the ninth aspect, wherein the time adjustment processing unit sets the time of the first clock and the time of the second clock at the time of power-on. When the time shift of is larger than a predetermined value, the time of the second clock is immediately adjusted to the time of the first clock.

In the timepiece device of the computer system according to the invention of claim 10, in addition to the operation of the invention of claim 9, the time difference between the time of the first clock and the time of the second clock is predetermined when the power is turned on. When the value is larger than the value, the reliability of the calculation result by the processing program cannot be ensured even if the time is corrected so that the time is not interrupted. Therefore, the time correction processing unit sets the time of the second clock to that of the first clock. Set the time instantly.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a block configuration diagram of a clock device of a computer according to an embodiment of the present invention. The clock device 11 is installed for each device constituting the computer.

The clock device 11 has two processing clocks, a first clock 12a that keeps time for external processing with respect to the outside of the device and a second clock 12b that keeps time for internal processing with respect to the inside of the device. ing. This processing clock includes a hardware clock and a software clock using an interrupt of a fixed cycle.

The oscillator 13 oscillates a clock at a predetermined oscillation frequency, and for example, a crystal oscillator is used. The oscillation frequency of the crystal oscillator, which is the clock source, is quite large. For example, the frequency used for a clock device is usually 327.
It is 68 Hz, and when it is also used as the clock of the arithmetic processing unit (CPU), one having an oscillation frequency of several MHz or higher is used. In the embodiment of the present invention, a case where an oscillation frequency of 10 MHz is used will be described. The output of the oscillator 12 is the first frequency divider circuit 14a and the second frequency divider circuit 14a.
Is input to the frequency dividing circuit 14b.

The first frequency dividing circuit 14a divides the oscillation frequency of the clock from the oscillator 13 by a predetermined frequency dividing ratio and inputs it to the first clock 12a. The first clock 12a counts the output of the first frequency dividing circuit 14a and ticks the time for external processing. Similarly, the second frequency dividing circuit 14b is connected to the oscillator 13
The transmission frequency of the clock from is divided by a predetermined division ratio and input to the second clock 12b. The second clock 12b is the second
The output of the frequency dividing circuit 14b is counted to mark the time for internal processing.

Here, the first frequency dividing circuit 14a and the second frequency dividing circuit 14a
The frequency division ratio of the frequency division circuit 14b is set by the time correction processing unit 15, and the frequency division ratio of a fixed value (for example, the frequency division ratio at which the output is 1 Hz) is set in the first frequency division circuit 14a. A variable frequency division ratio is set in the second frequency divider circuit 14b each time the time is adjusted.

The first clock 12a has a first frequency dividing circuit 14a.
The second clock 12b counts the output from the second frequency dividing circuit 14b to obtain the year / month / day / hour / minute / second. It is like this. First clock 12a and second clock 1
The year / month / day / hour / minute / second obtained in 2b can be read from the time correction processing unit 15 and the time can be set. In this case, in addition to the year, month, day, hour, minute, second, it may have a unit of ms.

A reference clock 17 is connected to the time adjustment processing unit 15 via a reference signal receiving unit 16. The reference clock 17 is a system representative, for example, from a host station to each device via a transmission line. Connected. The reference clock 17 may be provided in each device.

Next, the processing contents of the time adjustment in the time adjustment processing section 15 will be described. The time adjustment processing unit 15 adjusts the time at midnight when a processing program for data collection or the like is rarely activated or at every hour (XX: 00 minutes, once / hour). In this case, when the time at which the time adjustment is performed is in the operation time zone of the processing program, the time adjustment of the second clock is started after the time zone has elapsed. The time adjustment disclosure time point is preset in the time adjustment processing unit 15.

With respect to the first clock 12a for external processing, the second clock 12 for internal processing is immediately corrected to the reference time when the time adjustment is started with the frequency division ratio fixed.
As for b, the time of the second clock 12b is gradually adjusted at a constant ratio by operating at a frequency division ratio in consideration of the time difference from the reference clock 17 at the time of starting the time adjustment.

FIG. 2 is an explanatory diagram of the time correction of the first clock 12a for external processing, and FIG. 2A shows the first clock 12a.
2B is an explanatory view of how to adjust the time when the clock is ahead of the reference clock 17, FIG. 2B shows that the first clock 12b is the reference clock 17
It is explanatory drawing of the method of time adjustment when it is late.

In FIG. 2 (a), it is assumed that the reference clock 17 engraves the reference time Tr and the first clock 12a engraves the first processing time T1. Further, the reference time ticked by the reference clock 17 at the time adjustment start time T0 is Tr1,
It is assumed that the first clock 12a is ticking a time T11 which is ahead of that. In this case, the time correction processing unit 15 immediately corrects the time of the first clock 12a from T11 to Tr1.
In this case, since the first clock 12a is immediately corrected, the time is returned.

In FIG. 2 (b), it is assumed that the reference clock 17 engraves the reference time Tr and the first clock 12a engraves the first processing time T1. Further, the reference time ticked by the reference clock 17 at the time adjustment start time T0 is Tr1,
It is assumed that the first clock 12a is ticking a time T12 later than that. In this case, the time correction processing unit 15 immediately corrects the time of the first clock 12a from T12 to Tr1.
In this case, since the first clock 12a is immediately corrected, a time jump occurs.

As described above, since the first clock 12a is immediately corrected to the reference time, the time is returned or the time is skipped. However, the first clock 12a is used for external processing. Since it is a processing clock, and it is a preferable state that the corrected reference time of the entire system is obtained after the time correction request, there is no problem. As a result, when another device (host or device) reads the time of the device, the corrected time of the entire system is read.

Next, FIG. 3 shows a second clock 12 for internal processing.
3B is an explanatory diagram of the time adjustment of FIG. 3B, and FIG. 3A is an explanatory diagram of the time adjustment method when the second clock 12b is ahead of the first clock 12a (reference clock 17). ) Is the second
12 is an explanatory diagram of how to adjust the time when the clock 12b of FIG. 11 is behind the reference clock 17 of the first clock 12a.

In FIG. 3 (a), it is assumed that the reference clock 17 engraves the reference time Tr and the second clock 12b engraves the second processing time T2. Further, the reference time ticked by the reference clock 17 at the time adjustment start time T0 is Tr1,
It is assumed that the second clock 12b is ticking a time T21 that is ahead of that. In this case, the time adjustment processing unit 15 temporarily inputs a large frequency division ratio to the second frequency dividing circuit 14b,
The ticks of the second clock 12b are reduced (the advance of the clock is delayed). Then, a time T01 when the time of the second clock 12b matches the time of the reference clock 17 (first clock 12a).
Then, the frequency division ratio of the second frequency dividing circuit 14b is set to the first frequency dividing circuit 1
Match the frequency division ratio of 4a. Therefore, the second timepiece 12b does not cause time return or time skipping.

In FIG. 3 (b), it is assumed that the reference clock 17 engraves the reference time Tr and the second clock 12b engraves the second processing time T2. Further, the reference time ticked by the reference clock 17 at the time adjustment start time T0 is Tr1,
It is assumed that the second clock 12b is ticking a time T22 later than that. In this case, the time adjustment processing unit 15 temporarily inputs a small frequency division ratio to the second frequency dividing circuit 14b,
Increase the ticks of the second clock 12b (advance the advance of the clock). The time of the second clock 12b is the reference clock 1
Time T02 when the time coincides with time 7 (first clock 12a)
Then, the frequency division ratio of the second frequency dividing circuit 14b is set to the first frequency dividing circuit 1
Match the frequency division ratio of 4a. Therefore, in this case as well, the second clock 12b does not return time or skip time, the operating time of the processing program managed by the second clock 12b will not be lost, and The order will not be disturbed.

The processing contents of the time adjustment processing section 15 will be described in more detail. The time adjustment processing unit 15 obtains a time difference tn between the reference time Tr ticked by the reference clock 17 at the time adjustment start time T0 and the second processing time T2 ticked by the second clock 12b. Then, the following judgment is made.

(A) When Tr = T2: No time correction is necessary (b) When Tr <T2: Second clock 12b is advanced (advance of tn) (c) When Tr> T2: Second Clock 12b is delayed (delay of tn). As a result of the determination, if the time adjustment is not necessary (a), the frequency division ratio of the second frequency dividing circuit 14b to the second clock 12b is kept as it is. deep.

When the second clock 12b is advanced (b)
In order to increase the frequency, the frequency division ratio is temporarily increased to decrease the increment of the second clock 12b (delay the advance of the clock). And
When the time T2 of the second clock 12b coincides with the time of the reference clock 17, the frequency division ratio of the second frequency dividing circuit 14b is adjusted to the frequency division ratio of the first frequency dividing circuit 14a.

When the second clock 12a is delayed (c)
In order to temporarily reduce the frequency division ratio, the second clock 12b is increased in increments (advance the advance of the clock). Then, when the time T2 of the second clock 12b coincides with the time of the reference clock 17, the frequency division ratio of the second frequency dividing circuit 14b is adjusted to the frequency division ratio of the first frequency dividing circuit 14a.

As a method of adjusting the frequency division ratio of the second frequency division circuit 14b to the frequency division ratio of the first frequency division circuit 14a, the time adjustment processing section 15 causes the second frequency division circuit 14b to perform the first frequency division. The frequency division ratio of the frequency division circuit 14a is written in, but instead of this, the first frequency division circuit 14a and the second frequency division circuit 14b are used.
A switch is provided at the output part of the switch, and the switch is switched so as to input the first frequency dividing circuit 14a to the second clock 12b,
The frequency division ratio of the second timepiece 12b may be the same as the frequency division ratio of the first timepiece 12a.

Although the time of the second clock 12b is adjusted to the reference time of the reference clock 17, it may be adjusted to the first processing time T1 of the first clock 12a. This is because the first timepiece 12a is substantially the same as the reference time Tr of the reference timepiece 17 because the time is immediately corrected at the time adjustment start time T0 as shown in FIG.

Further, the frequency division ratio when the time of the second timepiece 12b is adjusted is such that the second timepiece 12b matches the first timepiece 12a by the timing of the start time of the next time adjustment. You may make it match slowly with a ratio. In this case, the time difference between the time of the time adjustment period and the time of the reference clock becomes small, and the operation of the processing program and the processing sequence are not disturbed. On the contrary, when the operation is not hindered, the adjustment may be performed quickly.

Next, during the time adjustment period (T0 to T01, T0 to T02) of the second clock 12b, when the time when the processing program operates is reached, the following processing is performed. As shown in FIG. 4, it is assumed that the processing program reaches the processing time t11 indicated by the second clock 12b during the time adjustment period (T0 to T01) of the second clock 12b. Then, the period Tn (Tn = t11 to t12) until time t12 when the processing of the processing program ends.
Performs the operation of returning the frequency division ratio of the second frequency dividing circuit 14b to the predetermined frequency division ratio during normal operation. Then, when the operation of the processing program is completed, the frequency division ratio at the time of correction is restored.

As a result, the processing program can be executed at normal processing timing, and the processing will not be hindered. Although FIG. 4 shows the case where the processing program is activated only once, the execution of the processing program is also processed in time increments according to the frequency division ratio during normal operation when the processing program is activated multiple times. .

In the above description, the period Tn for returning to the normal frequency division ratio is the operating time of the processing program, but with a margin, the time from the time point (frequency division circuit-α1) to the time point (frequency division circuit + α).
In the period up to 2), the time division may be set according to the normal frequency division ratio. That is, from before the time when the processing time of the processing program is reached (for example, α1 = 1 to 3 minutes before), after the time when the processing of the processing program is expected to end (for example, α2
= 1 to 5 minutes later) is temporarily returned to the normal frequency division ratio, and after that period, it is returned to the frequency division ratio at the time of correction again. As a result, the processing program can be surely executed at the normal processing timing, and the processing will not be hindered.

Next, a description will be given of the processing contents in the case where the time adjustment start time T0 is the operation time zone of the program which periodically executes the specific processing. In that case, the first clock 12
a immediately adjusts the time at the time T0 when the time is adjusted, and after the operating time zone of the processing program elapses, the second clock 12b
Correct the time of day.

FIG. 5 is an explanatory diagram of the processing contents of the time correction processing unit 15 when the time correction start time T0 is in the operation time zone of the processing program, and FIG.
FIG. 5 (b) is an explanatory view of the time adjustment of FIG.
FIG. 6 is an explanatory diagram of the time adjustment of FIG.

As shown in FIG. 5A, when there is a time correction start request at the time T0 within the operating time zone Tm of the processing program, the time correction processing unit 15 performs the time correction of the first clock 12a. Is the reference time Tr of the reference clock 17 immediately.
Is written in the first clock 12a, and the time T1 ticked by the first clock 12a is corrected to the reference time Tr.

On the other hand, for the second timepiece 12b, FIG.
As shown in (b), the operating time period Tm of the processing program
The correction of the time of the second clock 12b is started from the time T00 after the passage of.

Operating time zone Tm, which is a prohibited zone for time adjustment
Is before the time when the processing time of the processing program is reached, with the processing time Tn of the processing program interposed (for example, β1 = 1 to 1
From 2 minutes before) until after the time when the processing of the processing program is expected to end (for example, β2 = 1 to 5 minutes).

In the above description, the time adjustment is started at a predetermined time adjustment start time point so as to avoid the operating time range of the processing program. However, a time zone for invalidating the time adjustment may be provided. good. This means that when the reference clock 17 is provided in the host, when the time is adjusted, the reference time is transmitted from the host to each device and the time is adjusted, but the transmission speed between the devices is slow and the time is adjusted. If the processing priority of the program for transmitting the message is low, the reference time is not transmitted from the host to each device in a timely manner, so the time adjustment is invalid in such a time zone.

Further, although the frequency division ratio of the first frequency dividing circuit 14a has been described as a fixed value, this fixed value may be modifiable. This is because the reference clock 17 and the first clock 12a have the same time step. For example, the first clock 12
Based on the time difference between a and the reference timepiece 17, the first timepiece 12a obtains an appropriate frequency division ratio at which the time division of the reference timepiece 17 becomes the same, and operates the first timepiece 12a with the frequency division ratio. .

Now, the reference time of the reference clock 17 when the time is adjusted last time is Ta, the reference time of the reference clock 17 when the time is adjusted this time is Tb, and the time is adjusted next time. If the reference time of the wax reference clock 17 is Tc, the time of the first clock 12a this time is T1, and the frequency division ratio of the first clock 12a when there is no time delay is F1, specifically, the time difference (Tb -Ta) and the time difference (Tb-T2), the reference time Tc at the time of the time adjustment performed from the reference clock 17 expected next time is the same as the time of the first clock 12a at the time of the time adjustment. The first timepiece is operated with an appropriate frequency division ratio (F1 + α) that has been reviewed. As a result, the frequency division ratio of the first timepiece 12a can be set to an appropriate frequency division ratio that is the same as the time step of the reference timepiece 17.

Next, the operation and time adjustment of the first clock 12a and the second clock 12b at the time of power failure or power-on will be described. The first clock 12a is provided with a battery so that the clock can be clocked even when a power failure occurs. For example, the oscillator 13, the first frequency dividing circuit 14a, and the first clock 12a can be supplied with power from a battery in the event of a power failure. A battery backup is provided so that operation continues even if a power failure occurs and commercial power is not supplied. When a battery is provided, generally, it is operated by a commercial power supply during normal operation and by a battery during a power failure, but when it has low power consumption, it may be operated by a battery at all times. On the other hand, the second clock 12b saves the time like the first clock 12a at the time of power failure, but stops the ticks of time, and saves the time at the time of power failure.

When the power is turned on, the first clock 12a
If there is a time difference between the time and the time of the second clock 12b, the time correction processing unit 15 processes as if there was a time correction request for the time value indicated by the first clock 12a. For example,
When power is restored after a power failure, the first clock 12a keeps the time even when the power is lost, while the second clock 12b holds the time at the time of power failure, so that the time shifts when power is restored. Is occurring. The time adjustment processing unit 15 corrects this time difference.

That is, when the power is turned on, the first clock 12
Using a as a reference clock, the frequency division ratio corresponding to the time difference from the second clock 12b is set in the second frequency dividing circuit 14b, and time adjustment is performed as shown in FIG. When the time adjustment is completed, the frequency division ratio of the second frequency division circuit 14b is set to the same value as the frequency division ratio of the first frequency division circuit 14a. Also, by temporarily changing the frequency division ratio of the second clock 12b, it is possible to properly execute various program processes and processing sequences that normally operate. Therefore, even if there is a time lag, there is no need to perform special processing associated with it.

Further, in the case where the computer system is a system for accumulating and storing the process collection data, for example, there is an item in which the reliability of the value accumulated in the data is lost during the period in which the frequency division ratio of the second clock 12b is changed and processed. Adopts a method of storing the item together with a flag indicating that the data is “stored and stored at the time of initialization processing”, for example.

As a result, when data processing is performed by using (utilizing) the data stored and saved after the power failure is restored, the flag is checked in advance in accordance with the data processing, and the flag indicating that the stored data is reliable. If it is, the data processing is performed, and in other cases, “missing” can be processed.

Next, when the time difference between the time of the first clock 12a and the time of the second clock 12b exceeds the predetermined allowable range when the power is turned on, the time of the second clock 12b is set. I treated it as if there was no time difference, first
The time of the clock 12a is written in the second clock 12b and operated. In this case, the second timepiece 12b is operated at the normal frequency division ratio (the same frequency division ratio as the first timepiece 12a).

This is because the reliability of the accumulated data is low when the power failure occurs for a long period, for example, one month or one year, and the frequency division ratio of the second clock 12b is changed. This is because even if data is accumulated and a flag such as "accumulate and save when there is a large time difference" is stored together with the data, most of the accumulated data cannot be practically used.

Here, when the power is turned on, the first clock 12a is
May be forcibly adjusted to the reference time of the reference clock 17. In this case, the first clock 12a does not need to keep time at the time of power failure. That is, the battery for the first clock 12a to keep time at the time of power failure is unnecessary.
When the reference clock 17 is provided in a device such as a host that is a typical computer system, the reference time is read from the terminal to the host to obtain the reference time. Alternatively, the host side may detect that the terminal station has started up and request the terminal station to adjust the time.

[0076]

As described above, according to the present invention, it has the first clock for external processing and the second clock for internal processing, and the time which is suitable for the whole system is provided to the outside. It is possible to provide a time to the inside that does not cause a time jump or a time return that is suitable for internal processing, so it is possible to provide a time without any discomfort in system operation, and a process for a time jump or time return. Is unnecessary.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a computer clock device according to an embodiment of the present invention.

FIG. 2 is a first diagram for external processing according to the embodiment of the present invention.
Explanatory diagram of time correction of the clock.

FIG. 3 is a second diagram for internal processing according to the embodiment of the present invention.
Explanatory diagram of time correction of the clock.

FIG. 4 is an explanatory diagram of time adjustment of the second clock when the processing program is activated during the time adjustment period of the second clock according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of processing contents of a time correction processing unit when the start time of the time correction of the first clock and the second clock according to the embodiment of the present invention is in the operation time zone of the processing program.

[Explanation of symbols]

11 ... Clock device, 12a ... 1st clock, 12b ... 2nd clock, 13 ... Oscillator, 14a ... 1st frequency divider, 14b ...
Second frequency divider, 15 ... Time adjustment processing section, 16 ... Reference signal receiving section, 17 ... Reference clock

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Claims (10)

[Claims] 1. An oscillator that oscillates a clock at a predetermined oscillation frequency, a first frequency dividing circuit that divides the clock oscillation frequency of the oscillator by a predetermined frequency division ratio, and a first frequency dividing circuit. A first clock that counts the output and clocks the time for external processing, a second frequency dividing circuit that divides the oscillation frequency of the clock of the oscillator by a predetermined frequency dividing ratio, and a second frequency dividing circuit A clock device for a computer system, comprising: a second clock that counts the output and clocks the time for internal processing; and a time correction processing unit that corrects the times of the first clock and the second clock. . 2. The time adjustment processing unit, when the time adjustment start time comes, immediately corrects the reference time at the time adjustment start time with the division ratio fixed for the first clock,
The second clock is operated at a frequency division ratio in consideration of the time difference from the reference clock at the time of starting the time adjustment, and the time of the second clock is gradually adjusted at a constant ratio so that the time of the second clock becomes 1
2. The timepiece device for a computer system according to claim 1, wherein the frequency division ratio of the second clock is set to be the same as the frequency division ratio of the first clock if the time of the clock of 1 is matched. 3. The time adjustment processing unit, when the second clock is in the middle of adjusting the time, the time zone in which a program that periodically executes a specific process operates is a frequency division ratio during normal operation. 3. The timepiece device of the computer system according to claim 2, wherein the timepiece device is returned to the step of operating the second timepiece. 4. The time adjustment processing unit adjusts the time of the first clock at a time adjustment start time preset in the time adjustment processing unit, and the time adjustment start time periodically determines a specific process. When the operating time of the program
3. The timepiece device of a computer system according to claim 2, wherein the time of the second timepiece is corrected after the operating time period has elapsed. 5. The time adjustment processing unit, when performing the time adjustment of the second clock, has a frequency division ratio such that the time adjustment is completed at the time of the next time adjustment or a time in the vicinity thereof. 3. The timepiece device for a computer system according to claim 2, wherein the timepiece is operated. 6. The timepiece device for a computer system according to claim 1, wherein the reference timepiece is provided for each individual device constituting the computer system or for a host of the system. 7. The first clock is provided with a battery that supplies power even during a power failure, the first clock ticks the time even during a power failure, and the second clock stops during a power failure and stops at the time of the power failure. 2. The timepiece device for a computer system according to claim 1, wherein 8. The timepiece device for a computer system according to claim 7, wherein the time adjustment processing unit adjusts the time of the first clock to the time of the reference clock when the power is restored from the power failure. 9. The time adjustment processing unit determines whether the first clock and the second clock are different from each other when there is a time difference between the time of the first clock and the time of the second clock when the power is turned on. The second clock is operated at a division ratio in consideration of the time shift, the time of the second clock is gradually adjusted at a constant ratio, and if the time of the second clock matches the time of the first clock, the second clock is 2. The timepiece device for a computer system according to claim 1, wherein the frequency division ratio of said timepiece is the same as that of the first timepiece. 10. The time adjustment processing unit sets the time of the second clock to a time when the time difference between the time of the first clock and the time of the second clock is larger than a predetermined value when the power is turned on. 10. The timepiece device for a computer system according to claim 9, wherein the time is instantly set to the time of the first timepiece.