JP2003264805A - Multiplexing apparatus and multiplexing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variations in delays in multiplexing encoded packet data generated by encoding packet data comprising digital signals. <P>SOLUTION: A plurality of reception memories 12a to 12n store a plurality of input digital signal packets Sa to Sn. Further, a stuff packet generating section 13 selects packets to be multi-outputted next from outputs of a plurality of the reception memories 12a to 12n and an output of the stuff packet generating section 13 on the basis of switching control of a control section 15 and provides a multi-output, and controls a switching section 14 so as not to cause multiplex delay variations in the multi-output resulting from switching each input signal packet. The multiplexed signal is outputted as the multi-output digital signal packet in this way and a receiver side decodes the packet. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to multiplexing for transmitting packet data composed of digital signals, in particular one or more encoded packet data generated by encoding video, audio, etc., in a packet unit for transmission. The present invention relates to a multiplexing device and a multiplexing method, and more particularly to a multiplexing device and a multiplexing method for suppressing delay fluctuation during multiplexing.

[0002]

2. Description of the Related Art As a conventional example, there is a multiplexing system disclosed in Japanese Patent Laid-Open No. 11-215083 as shown in FIG. The present multiplexing system is a system that encodes a plurality of programs in, for example, digital broadcasting and then multiplexes and transmits them. The encoders 101a to 101n and the multiplexer 10 corresponding to the plurality of programs Pa to Pn are used.
It consists of 2. The multiplexing device 102 has each encoder 10
Each of the encoders 1a to 101n outputs one degree-multiplexed stream time-division-multiplexed in a packet unit to generate one degree-two multiplexed stream.
A plurality of receiving memories 103a to 103n for receiving the first-order multiplexed streams generated by 01a to 101n and temporarily storing the streams;
The switching unit 104 includes a switching unit 104 for selecting and multiplexing the first-order multiplexed stream stored in 03n, and a control unit 105 for controlling switching of the first-order multiplexed stream to be multiplexed in the switching unit 104. The control unit 105 also controls the multiplexing timing of the time reference information in each of the encoders 101a to 101n, which will be described in more detail in the section "Problems to be solved by the invention".

Next, an example of multiplexing processing in this multiplexing apparatus will be described with reference to FIG. FIG. 9 shows an operation example when four primary multiplexed streams Sa to Sd are multiplexed to generate one secondary multiplexed stream Se. Each rate of the primary multiplexing streams Sa to Sd is set to 2 Mbp.
s, 2 Mbps, 3 Mbps, and 3 Mbps. At this time, the number of packets at a certain reference time T is calculated from the rate ratio of each stream as follows: Primary multiplexed stream Sa: 2 Mbps → 2 packets Primary multiplexed stream Sb: 2 Mbps → 2 packets Primary multiplexed stream Sc: 3 Mbps → 3 packets The primary multiplexed stream Sd: 3 Mbps → 3 packets can be set.

Here, the control unit 105 in FIG. 8 determines the packet multiplexing order of each primary multiplexed stream at the reference time T based on the following (Procedure 1) to (Procedure 4). (Procedure 1) First, one packet is sequentially selected from all primary multiplexed streams regardless of the bit rate of each primary multiplexed stream. The section defined by this (Procedure 1) is set as a fixed priority section. (Procedure 2) Next, after all the packets of the primary multiplexing stream are selected in (Procedure 1), the packets of the primary multiplexing stream having the longest waiting time until the secondary multiplexing is performed in order from the packet. select. (Procedure 3) When there are a plurality of packets with the same degree of second-order multiplexing wait time in (Procedure 2), the packet with the highest bit rate is selected in order. (Procedure 4) When there are a plurality of packets having the same bit rate in (Procedure 3), the packets are selected according to the order of the fixed priority section defined in (Procedure 1).

In the example of FIG. 9, "a1-b1-c1-d1-c2-d2-a" is obtained by the above (procedure 1) to (procedure 4).
2-b2-c3-d3 "are multiplexed in this order. This multiplexing order is a multiplexing selection pattern, and the multiplexing operation is repeated by the multiplexing selection pattern with reference time T as a unit. .

[0006]

However, the above-mentioned multiplexer has a problem that the delay amount of each primary multiplexed stream due to multiplexing is not constant and fluctuation occurs. This fluctuation may cause a buffer failure in the decoder due to the influence of a shift in the time when the stream arrives at the decoder on the receiving side.

The above problem will be described below in more detail with reference to the multiplexing processing example shown in FIG. FIG. 10 shows the multiplexing intervals of the respective first-order multiplexed streams Sa to Sd regarding the second-order multiplexed stream in FIG. For example, the multiplexing intervals of the primary multiplexed stream Sa are not necessarily equal, such as a1-a2: 6 packet intervals a2-a3: 4 packet intervals a3-a4: 6 packet intervals, and vary at the multiplexing timing. Is occurring. Primary multiplexed streams Sb to S
The same applies to d. As described above, in the conventional multiplexer, the delay amount due to the multiplexing is not constant and fluctuation occurs, which may cause a buffer failure in the decoder on the receiving side.

Further, in the conventional multiplexer, the time base reference information is inserted only in the packet in the fixed priority order of the multiplex selection pattern of the secondary multiplexed stream, and the other multiplex of the multiplex selection pattern is inserted. A restriction is placed so that this time base reference information is not inserted in the packet. In the fixed priority section, each primary multiplexed stream S
With respect to a to Sd, the packets including the time base reference information are multiplexed one by one in a fixed order to suppress the multiplexing fluctuation. FIG. 11 shows an example of multiplexing timing of time reference information in the conventional multiplexing device. In FIG. 11, in the fixed priority section, the time reference information of the primary multiplexed streams Sa to Sd is always Sa → Sb → Sc.
Since one packet is multiplexed in the order of → Sd, it can be seen that the multiplexing interval of each packet including the time reference information is constant in the secondary multiplexing stream.

However, in this method, the multiplexing device imposes restrictions on the multiplexing timing of the time reference information for each encoder, and a plurality of such multiplexing devices are connected in series as shown in FIG. 12, for example. In this case, in the multiplexing device 401, the multiplexing device 301,
Delay fluctuations cannot be compensated for a plurality of time reference reference information included in each degree-two multiplexed stream output from the channels 302 and 30m, and there is a risk that the decoder on the receiving side cannot normally perform decoding.

The present invention has been made in order to solve the problems and drawbacks of the prior art as described above, and multiplexes a plurality of degree-one multiplexed streams in packet units to generate a degree-two multiplexed stream. Or a multiplexing device and a multiplexing method for further multiplexing a plurality of multiplexed secondary multiplexed streams, without restricting the multiplexing timing of time reference reference information in an encoder, and the primary multiplexed stream It is an object of the present invention to provide a multiplexing apparatus and a multiplexing method that can be applied not only when the above-mentioned multiplexing is performed but also when the secondary-multiplexed stream is multiplexed and which suppresses delay fluctuation due to the multiplexing.

[0011]

SUMMARY OF THE INVENTION A multiplexer according to the present invention is a digital signal multiplexer for receiving and multiplexing packets consisting of one or more digital signals, and a packet for receiving a plurality of digital signal packets. The packet multiplexing control means includes a receiving means, a packet multiplexing means for multiplexing the digital signal packets on a packet basis, and a packet multiplexing control means for controlling a packet multiplexing order. The digital signal packet sequence multiplexed and output from the means is controlled so that the received digital signal packets are output at equal intervals.

Further, the multiplexing device according to the present invention is based on the bit rates of a plurality of digital signal packets to be received and the packet multiplexing order by the packet multiplexing control means, under the control of the packet multiplexing control means. The bit rate of the digital signal packet multiplexed and output is set.

Further, the multiplexer according to the present invention, under the control of the packet multiplexing control means, receives a plurality of digital signals based on the multiplexing order of the packets and the bit rate of the digital signal packets to be multiplexed and output. It sets the bit rate of the packet.

The multiplexing device according to the present invention is an MPEG
Receives transport stream packets (hereinafter, TS packets) specified in 2-systems (ISO / IEC13818-1),
It is multiplexed in TS packet units.

Also, the multiplexing method according to the present invention is a digital signal multiplexing method for receiving and multiplexing a packet composed of one or more digital signals, and a packet receiving step of receiving a plurality of digital signal packets, A packet multiplexing step for multiplexing the digital signal packets packet by packet; and a packet multiplexing control step for controlling the packet multiplexing order, wherein the packet multiplexing control step comprises the digital output for the multiplexed output. In the signal packet train, the received digital signal packets are controlled so as to be output at equal intervals.

Further, the multiplexing method according to the present invention is based on the bit rate of a plurality of digital signal packets to be received and the packet multiplexing order by the packet multiplexing control step under the control of the packet multiplexing control step. The bit rate of the digital signal packet multiplexed and output is set.

Further, according to the multiplexing method of the present invention, a plurality of digital signals to be received are controlled by the packet multiplexing control step based on the packet multiplexing order and the bit rate of the digital signal packets to be multiplexed and output. It sets the bit rate of the packet.

The multiplexing method according to the present invention is an MPEG method.
Receives transport stream packets (hereinafter, TS packets) specified in 2-systems (ISO / IEC13818-1),
It is multiplexed in TS packet units.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing a first embodiment of a multiplexing apparatus according to the present invention. In the figure, 11 is a multiplexer, 12a to 12n are receiving memories for temporarily storing the input digital signal packets Sa to Sn, 13 is a stuff packet generating section for generating stuff packets, and 14 is receiving memories 12a to 12n.
A switching unit for switching and outputting the digital signal packet stored in the stuff packet and the stuff packet generated by the stuff packet generating unit 13, and a control unit 15 for controlling the switching of the switching unit 14.

Next, the operation will be described. The reception memories 12a to 12n temporarily store digital signal packets output from an encoder or a multiplexer (not shown). The stuff packet generator 13 receives the reception memory 1 in the multiplexed output digital signal packet of the multiplexer 11.
When there is no packet to be multiplexed and output next to 2a to 12n, and when it is necessary to forcibly stuff in order to prevent the multiplexing fluctuation of the input digital signal packets Sa to Sn in the multiplexed output digital signal packet. Generates and outputs a stuff packet. The switching unit 14 selects the packet to be multiplexed next based on the switching control by the control unit 15 from the outputs of the reception memories 12a to 12n and the stuff packet generation unit 13.

Next, the operation of the controller 15 will be described. First, each input digital signal packet Sa-S
Based on the bit rate of n, the reference time T satisfying the condition that the number of packets of each of the input digital signal packets Sa to Sn received during a certain reference time T is an integer is obtained. Next, the multiplexing selection pattern in the multiplexed output digital signal packet during the reference time T is determined by the following procedure. (Procedure 1) The number of packets that is a common multiple of the input digital signal packets Sa to Sn included in the reference time T is set as the pattern length of the multiplexing selection pattern. (Procedure 2) The input digital signal packets Sa to Sn included in the reference time T are arranged at equal intervals in the multiplexing selection pattern length calculated in the above (Procedure 1) without overlapping. (Procedure 3) When the arrangement cannot be performed in (Procedure 2), the pattern length obtained in (Procedure 1) is multiplied by m (m = 2, 3, 4 ...
・ (Procedure 2) is re-executed. (Procedure 4) If there is a vacant slot after the input digital signal packets Sa to Sd are arranged at equal intervals without overlapping each other in the above (Procedure 2), the stuff packet generated by the stuff packet generation unit in this vacant slot To generate a multiplexing pattern.

The control unit 15 controls the switching unit 14 based on the multiplexing selection pattern thus generated.

According to the above procedure, in the multiplexer according to the present invention, the multiplexing interval of each input digital signal packet in the multiplexed output digital signal packet becomes constant, so that the delay fluctuation due to the multiplexing can be suppressed. .

A specific example will be described with reference to FIG. FIG. 5 shows an operation example when one multiplexed output digital signal packet is generated by using the multiplexing method according to the present invention for the same four input digital signal packets Sa to Sd as shown in FIG. is there. First (procedure 1), from the ratio of the respective rates of the input digital signal packets Sa to Sd, as shown in FIG.
Input digital signal packet Sa: 2 Mbps → 2 packets Input digital signal packet Sb: 2 Mbps → 2 packets Input digital signal packet Sc: 3 Mbps → 3 packets Input digital signal packet Sd: 3 Mbps → It can be set to 3 packets. Therefore, the pattern length of the multiplexed selection pattern is set to 12 as a common multiple of (2, 2, 3, 3). Next, by (procedure 2), each input digital signal packet (Sa: 2 packets, Sb: 2 packets, Sc: 3 packets) within the reference time T is added to the multiplexing selection pattern length calculated in (procedure 1). Sd: 3 packets) are arranged at equal intervals without duplication. In the input digital signal packet Sa, two packets are multiplexed at equal intervals for a pattern length = 12, and therefore, six patterns Sa-1 to Sa-6 can be considered as shown in FIG. Similarly, for the input digital signal packet Sb, 6 patterns of patterns Sb-1 to Sb-6, and for the input digital signal packets Sc and Sd, 4 patterns each are listed as candidates. Among these, the input digital signal packet Sa: pattern Sa-1, the input digital signal packet Sb: pattern Sb-3, the input digital signal packet Sc: pattern Sc-2, the input digital signal packet Sd: pattern Sd-4 are combined. Since all the packets can be arranged in the multiplex selection pattern without overlapping, the condition of (Procedure 2) can be satisfied. Since the condition is satisfied in (Procedure 2), (Procedure 3) is skipped. Finally, by (procedure 4), stuff packets are arranged in slots # 5 and slot # 11 in which none of the packets Sa to Sd are arranged in the multiplexing selection pattern, and the multiplexing selection pattern is obtained by this. .

In the multiplexing selection pattern generated by the above procedure, the multiplexing interval of each input digital signal packet in the multiplexed output digital signal packet becomes constant.
For example, the multiplexing interval of the input digital signal packet Sa is a1-a2 = a2-a3 = a3-a4 = 6 packet intervals as shown in FIG. 7, and the input digital signal packet Sa is included in the multiplexed output digital signal packet Sa. Are evenly distributed.
The same applies to the input digital signal packets Sb to Sd.

As described above, the multiplexer according to the present invention can output each input digital signal packet at equal intervals in the stream after multiplexing, thereby suppressing delay fluctuation due to multiplexing. Therefore, it is possible to prevent the buffer failure at the decoder on the receiving side.

Further, in the multiplexing device according to the present invention, since each input digital signal packet can be stored at equal intervals in the multiplexed output digital signal packet, the multiplexing timing of the packet in which the time reference information is inserted The present invention can be applied without any restrictions, and can be applied not only to the first-order multiplexed stream but also to the second-order multiplexed stream.

Embodiment 2. The second embodiment is different from the above-described first embodiment in that the bit rate after multiplexing is set based on the bit rate of the received digital signal packet and the multiplexing order of the multiplexed packets by the packet multiplexing control means. . FIG. 2 is a block diagram showing a multiplexer according to the present invention. In the figure, 21 is a multiplexing device, 2
Reference numerals 2a to 22n are reception memories for temporarily storing the input digital signal packets Sa to Sn output from the encoders 27a to 27n, 23 is a stuff packet generation unit for generating stuff packets, and 24 is a reception memory 22a to 2n.
A switching unit that switches and outputs the digital signal packet stored in 2n and the stuff packet generated by the stuff packet generation unit 23, 25 is a control unit that controls switching of the switching unit 24, and 26 is selected by the switching unit 24. It is a multiplexing output unit that multiplexes and outputs the packets.

Next, the operation will be described. The reception memories 22a to 22n temporarily store the digital signal packets output from the encoders 27a to 27n. The stuff packet generation unit determines whether there is no packet to be multiplexed and output next in the reception memories 22a to 22n in the multiplexed output digital signal packet of the present multiplexer, and the input digital signal packets Sa to Sn in the multiplexed output digital signal packet. This is to generate and output a stuff packet when it is necessary to forcibly stuff in order to prevent the occurrence of the multiplexing fluctuation. Switching unit 24
Selects the next packet to be multiplexed from the reception memories 22a to 22n and the stuff packet generator 23 based on the switching control from the controller 25. Here, the control unit 2
5 generates a multiplexing selection pattern from the bit rate information of the digital signal packets output from the encoders 27a to 27n so that each input digital signal packet is multiplexed and output at equal intervals in the multiplexed output digital signal packet, The multiplexing order is set in the switching section 24, and the bit rate of the multiplexed output digital signal packet is set in the multiplexing output section 26 based on this multiplexing selection pattern.

As described above, in the multiplexer according to the present invention, the bit rates of a plurality of input digital signal packets to be received and the generation of the multiplex selection pattern by the same means as in the first embodiment are used to perform the post-multiplexing. It is possible to set the bit rate after multiplexing so that each input digital signal packet is output at equal intervals in the stream of, so that the delay fluctuation due to multiplexing can be suppressed, so that the decoder side Buffer failure can be prevented.

Further, in the multiplexing device according to the present invention, since each input digital signal packet can be stored at equal intervals in the multiplexed output digital signal packet, the multiplexing timing of the packet in which the time reference information is inserted is set. The present invention can be applied without any restrictions, and thus can be applied even when the encoders 37a to 37n are used as a multiplexing device.

Embodiment 3. This embodiment corresponds to the first embodiment described above.
With respect to, the bit rate of the digital signal packet to be received is set based on the multiplexing order of the multiplexed packets by the packet multiplexing control means and the bit rate after the multiplexing. FIG. 3 is a block diagram showing a multiplexing device according to the present invention. In the figure, 31 is a multiplexer, and 32a to 32n.
Is a reception memory for temporarily storing the input digital digital signal packets Sa-Sn output from the encoders 37a-37n, 33 is a stuff packet generation unit for generating stuff packets, and 34 is a reception memory 32a-3.
A switching unit that switches and outputs the digital signal packet stored in 2n and the stuff packet generated by the stuff packet generation unit 33, 35 is a control unit that controls switching of the switching unit 34, and 36 is selected by the switching unit 34. It is a multiplexing output unit that multiplexes and outputs the packets.

Next, the operation will be described. The reception memories 32a to 32n temporarily store the digital signal packets output from the encoders 37a to 37n. The stuff packet generation unit determines whether there is no packet to be multiplexed and output next in the reception memories 32a to 32n in the multiplexed output digital signal packet of the present multiplexer, and the input digital signal packets Sa to Sn in the multiplexed output digital signal packet. This is to generate and output a stuff packet when it is necessary to forcibly stuff in order to prevent the occurrence of the multiplexing fluctuation. Switching unit 34
Selects the next packet to be multiplexed from the reception memories 32a to 32n and the stuff packet generator 33 based on the switching control from the controller 35. Here, the control unit 3
5 generates a multiplexing selection pattern so that each input digital signal packet is output at equal intervals in the multiplexed output digital signal packet, sets the multiplexing order for the switching unit 34, and performs the above multiplexing. The rate control of the encoders 37a to 37n is performed based on the selection pattern and the bit rate of the multiplexed output digital signal packet.

As described above, in the multiplexing apparatus according to the present invention, the bit of each input digital signal packet is calculated from the bit rate of the multiplexed selection pattern generated by the means similar to that described in the first embodiment and the bit rate of the multiplexed stream. It is possible to set the rate, which allows each input digital signal packet to be output at equal intervals in the stream after multiplexing, and delay fluctuations due to multiplexing can be suppressed, so that the decoder side Buffer failure can be prevented.

Further, in the multiplexing device according to the present invention, since each input digital signal packet can be stored at equal intervals in the multiplexed output digital signal packet, the multiplexing timing of the packet in which the time reference information is inserted is set. The present invention can be applied without any restrictions, and thus can be applied even when the encoders 37a to 37n are used as a multiplexing device.

Fourth Embodiment This embodiment corresponds to the first embodiment described above.
Receives digital signal packets about MPEG2-system
The present invention relates to a multiplexing device that receives TS packets and multiplexes them in TS packet units when the TS packets are defined in s (ISO / IEC13818-1). FIG. 4 is a block diagram showing a multiplexer according to the present invention. In the figure, 41 is a multiplexer, 42a to 42n are reception memories for temporarily storing the input TS packets Sa to Sn,
Reference numeral 43 is a null TS packet generation unit that generates a null TS packet, and 44 is a switching unit that switches and outputs the input TS packet stored in the reception memories 42a to 42n and the null TS packet generated by the null TS packet generation unit 43. ,
A control unit 45 controls switching of the switching unit 44.

Next, the operation will be described. The reception memories 42a to 42n temporarily store input TS packets from an encoder or a multiplexing device (not shown). Null TS
When there is no TS packet to be multiplexed and output next in the reception memories 42a to 42n in the multiplexed output TS packet of the present multiplexer, the packet generation unit 43 inputs the input TS packet Sa to Sn in the multiplexed output TS packet.
This is to generate and output a null TS packet when it is necessary to forcibly stuff in order to prevent the occurrence of the multiplexing fluctuation of the above. The switching unit 44 selects a packet to be multiplexed next from the reception memories 42a to 42n and the null TS packet generation unit 43 based on the switching control from the control unit 45. Here, the control unit 45 is the first embodiment.
By the same means as described, a multiplexing selection pattern is generated so that each input TS packet is output at equal intervals in the multiplexed stream, and the multiplexing order is set in the switching unit 44.

As described above, the multiplexer according to the present invention can output each input TS signal packet in the stream after multiplexing at equal intervals, thereby suppressing delay fluctuation due to multiplexing. Therefore, it is possible to prevent the breakdown of the buffer on the decoder side.

Further, in the multiplexing device according to the present invention, since each input TS packet can be stored at equal intervals in the multiplexed output TS packet, the time reference reference value (PCR) specified in MPEG2-systems is multiplexed. It is possible to suppress fluctuations in the data, and it is possible to apply the method without restricting the timing at which the encoder multiplexes the PCR. Therefore, the present invention can be applied not only to the encoder output of each input TS packet Sa to Sn but also to the multiplexer output.

[0040]

According to the present invention, since the received digital signal packets are output at equal intervals in the multiplexed output digital signal packet sequence, delay fluctuation due to multiplexing can be suppressed. It is possible to prevent buffer failure at the decoder on the receiving side, and it can be applied without any restrictions on the multiplexing timing of the packet in which the time reference information is inserted. It is also applicable when multiplexing the next multiplexed stream.

According to the present invention, the packet multiplexing control means controls the multiplexing based on the bit rates of a plurality of received digital signal packets and the packet multiplexing order of the packet multiplexing control means. Since the bit rate of the output digital signal packet is set, delay fluctuation due to multiplexing can be suppressed, so that buffer failure on the decoder side can be prevented.

Further, according to the present invention, the bits of the plurality of digital signal packets to be received are controlled by the packet multiplexing control means based on the multiplexing order of the packets and the bit rate of the digital signal packets multiplexed and output. Since the rate is set, delay fluctuation due to multiplexing can be suppressed, so that buffer failure on the decoder side can be prevented.

Further, according to the present invention, MPEG2-systems
Since the transport stream packet (TS packet) specified in (ISO / IEC13818-1) is received and multiplexed in TS packet units, delay fluctuation due to multiplexing can be suppressed. It is possible to prevent buffer breakdown in the decoder on the side, and it can be applied without any restriction on the multiplexing timing of the packet in which the time reference information is inserted, which allows not only the primary multiplexing stream but also the secondary multiplexing stream. It is also applicable when multiplexing multiplexed streams.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a multiplexing device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the multiplexing device according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of the multiplexing device according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the multiplexing device according to the present invention.

FIG. 5 is a diagram showing an example of a multiplexing operation of the multiplexing device according to the present invention.

FIG. 6 is a diagram showing an example of a procedure for generating a multiplexing selection pattern of the multiplexing device according to the present invention.

FIG. 7 is a timing diagram showing that the delay of each input signal is fixed in the multiplexed output of the multiplexer according to the present invention.

FIG. 8 is a block diagram of a conventional multiplexer.

FIG. 9 is a diagram showing an example of a multiplexing operation in a conventional multiplexing device.

FIG. 10 is a timing diagram when delay fluctuations of an input signal occur in a conventional multiplexer.

FIG. 11 is a timing diagram showing that the multiplexing interval of the time reference information is constant in the conventional multiplexing device.

FIG. 12 is a block diagram showing an example of a system configuration that cannot be applied to a conventional multiplexing device.

[Explanation of symbols]

11, 21, 31, 102, 301, 302, 30m,
401 multiplexers 12a, 12b, 12n, 22a, 22b, 22n, 3
2a, 32b, 32n, 103a, 103b, 103n
Reception memory 13, 23, 33 Stuff packet generation unit 14, 24, 34, 104 Switching unit 15, 25, 35, 105 Control unit 26, 36 Multiplexing output unit 27a, 27b, 27n, 37a, 37b, 37n, 1
01a, 101b, 101n, 201, 202, 20
x, 211, 212, 21y, 2m1, 2m2, 2mz
Encoder 43 Null TS packet generator

Claims (8)

[Claims] 1. A digital signal multiplexer that receives and multiplexes packets consisting of one or more digital signals, and a packet receiving unit that receives a plurality of digital signal packets, and the digital signal packets are multiplexed in packet units. Packet multiplexing means for multiplexing, and packet multiplexing control means for controlling the multiplexing order of the packets, wherein the packet multiplexing control means includes the digital signal packet string multiplexed and output from the multiplexing means. A multiplexer that controls so that each received digital signal packet is output at equal intervals. 2. A digital signal packet that is multiplexed and output under the control of the packet multiplexing control means based on the bit rates of a plurality of received digital signal packets and the packet multiplexing order of the packet multiplexing control means. 2. The multiplexing device according to claim 1, wherein the bit rate of is set. 3. The control of the packet multiplexing control means sets the bit rates of a plurality of received digital signal packets based on the packet multiplexing order and the bit rate of the digital signal packets multiplexed and output. A multiplexing device according to claim 1, characterized in that 4. A transport stream packet (hereinafter referred to as TS) defined in MPEG2-systems (ISO / IEC13818-1).
4. The multiplexing device according to claim 1, wherein the multiplexing device receives a packet and multiplexes it in TS packet units. 5. A digital signal multiplexing method for receiving and multiplexing a packet composed of one or more digital signals, comprising a packet receiving step of receiving a plurality of digital signal packets, and multiplexing the digital signal packets in packet units. And a packet multiplexing control step for controlling the packet multiplexing order, wherein the packet multiplexing control step is performed by the received digital signals in the multiplexed digital signal packet sequence. A multiplexing method characterized by controlling so that signal packets are output at equal intervals. 6. A digital signal packet that is multiplexed and output under the control of the packet multiplexing control step based on the bit rates of a plurality of received digital signal packets and the packet multiplexing order of the packet multiplexing control step. 6. The multiplexing method according to claim 5, wherein the bit rate of is set. 7. The control of the packet multiplexing control step sets the bit rates of a plurality of digital signal packets to be received based on the packet multiplexing order and the bit rate of the digital signal packets multiplexed and output. The multiplexing method according to claim 5, which is characterized in that 8. A transport stream packet (hereinafter referred to as TS) defined in MPEG2-systems (ISO / IEC13818-1).
Packet) is received and multiplexed in TS packet units.