JP2003263889A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress current consumption at the time of write-in. <P>SOLUTION: This device is provided with column a plurality of column selector circuits 21A, 21B selecting respectively a pair of bit line out of a plurality of pairs of bit lines 3-6, a plurality of pre-charge equalizing circuits 7A, 7B connected respectively to a plurality of pairs of bit lines 3-6, a column address decoder 11 selecting the column selector circuit 21A, 21B, and a pre- charge control circuit 23 which pre-charges a bit line not to be written and does not pre-charge a bit line to be written before write-in by decoding a plurality of column selecting signals 8, 9 outputted from the column address decoder 11 and pre-charge signals 13, 14. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to low power consumption of a semiconductor memory device.

[0002]

2. Description of the Related Art FIG.
The circuit diagram of RAM is shown. In FIG. 7, 1A and 1B are plural memory cells, 2 is a word line (WL) connected to the plural memory cells 1A and 1B, and 3 to 6 are plural pairs of memory cells connected to the plural memory cells 1A and 1B. Bit line (BL0, /
BL0, BL1, / BL1), 7A, 7B are a plurality of pairs of bit lines (BL0, / BL0, BL1, / BL1) 3 to 6
And a plurality of precharge / equalize circuits 21A and 21B connected to the power supply voltage VDD for precharging and equalizing to the power supply voltage VDD.
/ BL0, BL1, / BL1) A plurality of column selector circuits for selecting a pair of bit lines among 3 to 6, 8 and 9
Is a column selection signal (CA0, CA1) for selecting each of the plurality of column selector circuits 21A, 21B, and 10 is a plurality of pairs of bit lines (BL0, / BL0, BL1, / BL1) 3 via the column selector circuits 21A, 21B. Is a write buffer connected to 6 to store data to be written in the memory cells 1A and 1B, and 11 is a column selection signal (CA
0, CA1) 8, 9 are column address decoders, 12 is a column address given to the column address decoder 11, and 15 is a precharge signal (PRC).

In the semiconductor memory device having the above-mentioned structure, a plurality of pairs of bit lines 3 to 6 for transmitting data of a plurality of memory cells 1A and 1B are connected to the precharge / equalize circuits 7A and 7B, and read. Before and before writing, the plurality of pairs of bit lines 3 to 6 are precharged to the power supply voltage VDD by the precharge / equalize circuits 7A and 7B.

At the time of writing, write data is transmitted from the write buffer 10 to the pair of bit lines selected by the column address 12, and one of the pair of selected bit lines is set to the ground voltage VSS.

FIG. 8 is a timing diagram showing the operation of the circuit of FIG. In FIG. 8, read cycle 0 (CA0 selection / activation), write cycle 1 (CA0 selection / activation), write cycle 2 (CA0 selection / activation), write cycle 3 (CA0 selection / activation), write State of clock CLK and column address in each cycle of cycle 4 (CA1 selection / activation) Column A
ddress, precharge signal PRC, column selection signals CA0, CA1, state of word line WL, state of pair of bit lines BL0, / BL0, pair of bit lines BL
1, / BL1 state is shown.

In FIG. 8, in the read cycle 0, the write cycle 1, the write cycle 2 and the write cycle 3, the column selection signal CA0 becomes "H" (activated) and the column selection signal CA1 becomes "L" (inactivated). ), The pair of bit lines BL0, / BL0 is in the selected state and the pair of bit lines BL1, / BL1 is in the non-selected state. In the write cycle 4, since the column selection signal CA0 is "L" and the column selection signal CA1 is "H", the pair of bit lines BL0, / B
L0 becomes a non-selected state, and a pair of bit lines BL1, / B
L1 is in the selected state.

In the read cycle 0, the pair of bit lines BL0 and / BL0 selected by the column address drop one potential from the power supply voltage VDD to an intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS. In each of the write cycles 1 to 4, the pair of bit lines BL0, / BL0, selected by the column address is lowered in potential from the power supply voltage VDD to the ground voltage VSS by the write operation by the write buffer 10. Let
In addition, the potential of the pair of unselected bit lines is also the power supply voltage VDD.
To the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS.

After the end of access regardless of reading or writing, each pair of bit lines is precharged every cycle.

[0009]

However, according to the above configuration, when the write data in the write cycle 1 is the same as the write data in the write cycle 2, one of the pair of bit lines once selected in the write cycle 1 is selected. Despite lowering the potential to the ground voltage VSS, after the writing is completed, the pair of bit lines are precharged to the power supply voltage VDD and then again in the write cycle 2, one potential of the same pair of bit lines is set to the ground potential VSS. Lower to. This consumes useless current.

An object of the present invention is to solve the above conventional problems and to provide a semiconductor memory device capable of reducing the current consumption when continuously transmitting the same data to the same bit line. To do.

[0011]

The present invention reduces the current consumption when the same data is continuously transmitted to the same bit line by not precharging the bit line to be written before writing. Is.

A detailed description will be given below.

According to another aspect of the semiconductor memory device of the present invention, the memory cell includes a memory cell, a bit line connected to the memory cell, and a precharge circuit connected to the bit line. The bit line connected to is not precharged.

According to this structure, the bit line connected to the memory cell to be written is not precharged before the write operation. Therefore, when continuously transmitting the same data to the same bit line, It is possible to avoid wasteful repetition of precharge and discharge of charges. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. That is, when the write data in the write cycle is the same as the write data in the previous write cycle, the current that drives the bit line can be reduced. In this case, if the load capacitance of the bit line is Cb, then 1
The charge amount of Cb × VDD per bit line can be reduced. However, VDD is a power supply voltage.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, and a plurality of column selectors for selecting one of the plurality of bit lines. Circuit, multiple precharge circuits respectively connected to multiple bit lines, hold circuit for holding column address to select column selector circuit, last accessed column address stored in hold circuit and this time If the column address accessed previously matches the column address accessed this time based on the comparison result of the comparator and the column address accessed this time, the column address accessed this time before writing It has a precharge control circuit to prevent precharging the designated bit line.

According to this structure, when the previously accessed column address and the currently accessed column address match, the bit line designated by the currently accessed column address is not precharged before writing. Therefore, when the same data is continuously transmitted to the same bit line, it is possible to avoid wasteful repetition of precharge and discharge of charges. as a result,
In the write cycle, the current consumption when continuously transmitting the same data to the same bit line can be reduced.

According to another aspect of the semiconductor memory device of the present invention, in the semiconductor memory device of claim 2, the precharge control circuit is provided in a supply path to the plurality of precharge circuits for supplying a periodic precharge signal for a write cycle. And a gate circuit which is cut off when the column address accessed last time and the column address accessed this time match based on the comparison result of the comparator and conducts when they do not match.

According to this structure, the same operation as that of the second aspect is provided.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the second aspect, further comprising a plurality of weak precharge circuits which are respectively connected to a plurality of bit lines and have a weaker current driving capability than the plurality of precharge circuits. Further, the weak precharge circuit connected to bit lines other than the bit line designated by the column address accessed this time is operated.

According to this structure, in addition to the same effect as that of claim 2, since the bit lines other than the bit line designated by the column address accessed this time are precharged by the weak precharge circuit, they are accessed this time. It is possible to avoid the voltage drop of bit lines other than the bit line specified by the column address.

Further, by providing the weak precharge circuit to avoid the voltage drop of the bit lines other than the bit line designated by the column address accessed this time, the following operational effects are obtained. That is, when the precharge is not performed by the weak precharge circuit, when the operating frequency is low, or when the same column address is continuously selected, the potential of the unselected bit line is changed to the memory cell due to the leak current. Lower than the writing level of
The data in the memory cells connected to the unselected bit lines may be rewritten. Such a malfunction can be prevented by the weak precharge circuit.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, and a plurality of column selectors for selecting one bit line among the plurality of bit lines. A circuit, a plurality of precharge circuits respectively connected to a plurality of bit lines, a column address decoder for selecting a column selector circuit, and a plurality of column selection signals and precharge signals output from the column address decoder. Therefore, a precharge control circuit for precharging a bit line which is not a writing target before writing and preventing a bit line which is a writing target from being precharged is provided.

According to this structure, the bit lines not to be written are precharged before writing and the bit lines to be written are not precharged, so that the same data is continuously transmitted to the same bit line. In this case, it is possible to avoid wasteful repetition of precharge and discharge of electric charges. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. Further, the circuit configuration is simple and can be realized more easily than in the case of claim 2.

A semiconductor memory device according to a sixth aspect is the semiconductor memory device according to the fifth aspect, wherein the precharge control circuit is provided in a supply path to the plurality of precharge circuits for a periodic precharge signal for a write cycle. Of the plurality of column selection signals, the supply path of the precharge signal to the precharge circuit corresponding to the column selection signal in the selected state is cut off, and the precharge corresponding to the column selection signal in the non-selected state is cut off. It is composed of a gate circuit that conducts a supply path of a precharge signal to the circuit.

According to this structure, the same operation as that of the fifth aspect is provided.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells arranged in an array, a plurality of bit lines connected to the plurality of memory cells, and one bit line of the plurality of bit lines are provided. A plurality of column selector circuits to be selected, a plurality of precharge circuits respectively connected to a plurality of bit lines, and a word line connected to a plurality of memory cells are provided. The same number as the number of column selectors is provided, which are individually connected to a plurality of memory cells in a one-to-one correspondence with column addresses, and only one word line corresponding to the column address is activated by the word line selection circuit and read. Before writing, a plurality of bit lines are precharged, and before writing, a plurality of bit lines are not precharged.

According to this structure, the same number of column selectors as the number of word lines are provided in a plurality of memory cells in the same row, and the word lines are individually connected to the plurality of memory cells in a one-to-one correspondence with column addresses. Since only one word line corresponding to the column address is activated by the word line selection circuit, a plurality of bit lines are precharged before reading, and a plurality of bit lines are not precharged before writing. In the case where the same data is continuously transmitted to the same bit line, useless repetition of precharge and discharge of charges can be avoided. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. Moreover, since only one word line corresponding to the selected bit line is selected and the word line corresponding to the non-selected bit line is not activated, no current flows from the bit line to the memory cell. Therefore, the current flowing through the non-selected bit line can be reduced.

According to an eighth aspect of the present invention, in the semiconductor memory device according to the first, second, fifth or seventh aspect, the column address for selecting the bit line is arranged above the memory address.

According to this structure, since the column address for selecting the bit line is arranged above the memory address, it is possible to reduce the change in the bit line selected in each write cycle, and in the case of continuous writing. In addition, the probability that the same bit line is continuously selected is increased, and the current consumption can be further reduced.

[0030]

1 is a circuit diagram showing the configuration of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, 16A and 16B are a plurality of pairs of bit lines (BL
0, / BL0, BL1, / BL1) 3 to 6 respectively connected to a plurality of precharge / equalize circuits 7A and 7B.
A plurality of weak precharge circuits having a weaker current driving capability than the weak precharge circuits 16A and 16B connected to bit lines other than the pair of bit lines designated by the column address accessed this time operate. 17 is a column address 12 for selecting the column selector circuits 21A and 21B.
Is a column address register as a hold circuit for holding. Reference numeral 18 is a comparator for comparing the previously accessed column address held in the column address register 17 with the currently accessed column address.

Reference numeral 22 denotes a pair of bits designated by the column address accessed this time before writing when the column address accessed last time and the column address accessed this time match based on the comparison result of the comparator 18. It is a precharge control circuit that prevents the line from being precharged. The precharge control circuit 22 is composed of a gate circuit including an AND circuit 22A and a NOR circuit 22B, and has a periodic write precharge signal (PRC_W) 13 for a write cycle and a periodic read precharge for a read cycle. Signal (PRC_R) 14
Are provided in the supply path to the plurality of precharge / equalize circuits 7A and 7B. Then, the periodic read precharge signal (PRC_
R) 14 is passed unconditionally. In addition, a periodic write precharge signal (PRC_
W) 13 is blocked when the previously accessed column address and the currently accessed column address match based on the comparison result of the comparator 18, and passes when the column address does not match. The output signal of the precharge control circuit 22 becomes the precharge signal (PRC) 15.

The configuration other than the above is the same as that of the conventional example shown in FIG.

In the semiconductor memory device having the above-described structure, at the time of writing, the write data output from the write buffer 10 is transmitted to the pair of bit lines selected by the column address 12, eg, 3 and 4. The potential of one of the selected pair of bit lines 3 and 4 is set to the ground voltage VS.
The data in the memory cell 1A holding the data connected to the selected pair of bit lines 3 and 4 is rewritten to S.

At this time, a pair of non-selected bit lines 5 and 6
The weak precharge circuit 16B having a weak current drive capability, which is connected to, operates to hold the potentials of the pair of unselected bit lines 5 and 6 at the power supply voltage VDD.

At this time, the column address 12 at the time of writing
And the previously accessed column address 12 held in the column address register 17 are compared by the comparator 8, and when the comparison result shows a match, the precharge control circuit 22 selects the pair of column addresses 12 selected. For bit lines 3 and 4, precharge before writing.
Do not precharge with the equalize circuits 7A and 7B. When the previously read or written data is the same as the data currently written in the memory cells 1A and 1B, the current for precharging the selected pair of bit lines 3 and 4 can be reduced.

FIG. 2 is a timing diagram showing the operation of the circuit of FIG. In FIG. 2, read cycle 0 (CA0 selection / activation), write cycle 1 (CA0 selection / activation), write cycle 2 (CA0 selection / activation), write cycle 3 (CA0 selection / activation), write State of clock CLK and column address in each cycle of cycle 4 (CA1 selection / activation) Column A
ddress and column address register 17 status Column A
ddress Register and column selection signals CA0, CA1
, The precharge signal PRC, the state of the word line WL, the state of the pair of bit lines BL0, / BL0, and the state of the pair of bit lines BL1, / BL1.

In FIG. 2, read cycle 0, write cycle 1, write cycle 2, write cycle 3
Then, since the column selection signal CA0 is "H" and the column selection signal CA1 is "L", the pair of bit lines BL0, / BL0 is in the selected state and the pair of bit lines BL1, / BL1 is It is in a non-selected state. In the write cycle 4, the column selection signal CA0 is "L" and the column selection signal CA1 is "H".
The pair of bit lines BL0 and / BL0 are in a non-selected state,
The pair of bit lines BL1, / BL1 are in the selected state.

In the read cycle 0, the pair of bit lines selected by the column address lowers one potential from the power supply voltage VDD to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS. In each of the write cycles 1 to 4, the pair of bit lines selected by the column address drop one potential from the previous state to the ground voltage VSS by the write operation by the write buffer 10. Further, the potentials of the pair of unselected bit lines are also held at the power supply voltage VDD. When the write data is inverted, one potential of the selected pair of bit lines drops from the power supply voltage VDD to the ground voltage VSS and the other potential rises from the ground voltage VSS to the power supply voltage VDD.

Here, each cycle will be described in detail.

In the read cycle 0, the column selection signal CA0 is selected (activated) and the memory cell 1A is selected.
The data is read out from one of the pair and the potential of one of the pair of precharged bit lines 3 and 4 drops to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS.

In the write cycle 1, the column address 12 in the read cycle 0 held in the column address register 17 is compared with the column address 12 in the write cycle 1, and when the comparison result shows a match, that is, the same 1 When the pair of bit lines 3 and 4 are subsequently selected, the pair of bit lines 3 and 4 selected by the column address 12 is not precharged before writing. When the data read in the read cycle 0 and the data written in the write cycle 1 are the same, as compared with the case of precharging the selected pair of bit lines 3 and 4, Cb × ( The charge amount can be reduced by (VDD-Vm). The pair of unselected bit lines 5 and 6 are supplied with the power supply voltage VDD by the precharge circuit 16 having a weak drive capability.
Held in.

Similarly, in the write cycle 2, the column address 12 in the write cycle 1 held in the column address register 17 is compared with the column address 12 in the write cycle 2, and when the comparison result shows a match, that is, When the same pair of bit lines 3 and 4 is selected, the 1 selected by the column address 12 before writing.
The paired bit lines 3 and 4 are not precharged. Write data in write cycle 1 and write cycle 2
When the write data is the same, the charge amount of the pair of bit lines 3 and 4 can be reduced by Cb × VDD as compared with the case of precharging the selected pair of bit lines 3 and 4.

In the write cycle 3, the column address 12 in the write cycle 2 held in the column address register 17 is compared with the column address 12 in the write cycle 3, and when the comparison result shows a match, that is, the same 1 When the pair of bit lines 3 and 4 is selected, the pair of bit lines 3 and 4 selected by the column address 12 is not precharged before writing. When the write data in the write cycle 2 is different from the write data in the write cycle 3, the consumption of the charge amount is equal to that in the case of precharging the selected pair of bit lines 3 and 4.

In the write cycle 4, the column address 12 in the write cycle 3 held in the column address register 17 is compared with the column address 12 in the write cycle 4, and when the comparison result shows a mismatch,
That is, when a different pair of bit lines 5 and 6 is selected,
Before writing, the pair of bit lines 5 and 6 is precharged.

According to the semiconductor memory device of this embodiment, when the column address 12 accessed last time and the column address 12 accessed this time match, the column address 12 accessed this time before writing is designated. Since the pair of bit lines 3 to 6 are not precharged, when the same data is continuously transmitted to the same pair of bit lines 3 to 6, there is no waste of precharge and discharge of charges. You can avoid repetition.
As a result, in the write cycle, it is possible to reduce the current consumption when continuously transmitting the same data to the same pair of bit lines.

The weak precharge circuits 16A and 16B are also provided.
Since the bit lines other than the pair of bit lines designated by the column address accessed this time are precharged by the weak precharge circuit, the pair of bits designated by the column address accessed this time is provided. It is possible to avoid the voltage drop of the pair of bit lines 5 and 6 other than the lines 3 and 4, for example.

FIG. 3 is a circuit diagram showing the structure of a semiconductor memory device according to the second embodiment of the present invention. In FIG. 3, reference numeral 23 denotes a plurality of column selection signals (CA0, CA1) 8 and 9 output from the column address decoder 11, a periodic write precharge signal (PRC_W) 13 for a write cycle, and a periodical write cycle. By pre-charging the read precharge signal (PRC_R) 14 to precharge the bit lines 3 to 6 which are not write targets before writing and not precharging the bit lines 3 to 6 which are write targets It is a control circuit.

This precharge control circuit 23 is AND
The gate circuit is composed of circuits 23A and 23B and NOR circuits 23C and 23D, and a periodic write precharge signal (PRC_W) 13 for a write cycle and a periodic read precharge signal (PRC_R) 14 for a read cycle. Are provided in the supply path to the plurality of precharge / equalize circuits 7A and 7B.

Then, the periodic read precharge signal (PRC_R) 14 for the read cycle is passed unconditionally. Further, the periodic write precharge signal (PRC_W) 13 for the write cycle is passed when the column selection signals CA0 and CA1 are inactive,
Shut off when active. Precharge control circuit 2
3 output signals are precharge / equalize circuits 7A, 7
Precharge signal (PRC0, PRC
1) 19 and 20.

The configuration other than the above is the same as that of the conventional example shown in FIG.

In the semiconductor memory device having the above configuration, at the time of writing, the write data output from the write buffer 10 is transmitted to the pair of bit lines 3, 4 or 5, 6 selected by the column address 12. Then, one of the potentials of the selected pair of bit lines, for example, 3, 4 is pulled down to the ground voltage VSS, and the data of the memory cell 1A holding the data connected to the pair of bit lines 3, 4 is rewritten. At this time, the selected pair of bit lines 3 and 4 is not precharged, and the unselected pair of bit lines 5 and 6 is precharged. If the previously read or written data is the same as the data currently written to the memory cell,
The current that precharges the pair of bit lines 3, 4 or 5, 6 can be reduced.

FIG. 4 is a timing diagram showing the operation of the circuit of FIG. In FIG. 4, read cycle 0 (CA0 selection / activation), write cycle 1 (CA0 selection / activation), write cycle 2 (CA0 selection / activation), write cycle 3 (CA0 selection / activation), write State of clock CLK and column address in each cycle of cycle 4 (CA1 selection / activation) Column A
ddress, column selection signals CA0, CA1, precharge signals PRC0, PRC1, state of word line WL, state of pair of bit lines BL0, / BL0, state of pair of bit lines BL1, / BL1 And are shown.

In FIG. 4, read cycle 0, write cycle 1, write cycle 2, write cycle 3
Then, since the column selection signal CA0 is "H" and the column selection signal CA1 is "L", the pair of bit lines BL0, / BL0 is in the selected state and the pair of bit lines BL1, / BL1 is It is in a non-selected state. In the write cycle 4, the column selection signal CA0 is "L" and the column selection signal CA1 is "H".
The pair of bit lines BL0 and / BL0 are in a non-selected state,
The pair of bit lines BL1, / BL1 are in the selected state.

In the read cycle 0, the pair of bit lines selected by the column address lowers one potential from the power supply voltage VDD to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS. In each of the write cycles 1 to 4, the pair of bit lines selected by the column address drop one potential from the previous state to the ground voltage VSS by the write operation by the write buffer 10. The potentials of the pair of unselected bit lines also drop from the power supply voltage VDD to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS, but return to the power supply voltage VDD each time they are precharged. When the write data is inverted, one potential of the selected pair of bit lines drops from the power supply voltage VDD to the ground voltage VSS and the other potential rises from the ground voltage VSS to the power supply voltage VDD.

Here, each cycle will be described in detail.

In the read cycle 0, the column selection signal CA0 is selected (activated) and the memory cell 1A
The data is read out, and the potential of one of the pair of precharged bit lines 3 and 4 drops to Vm.

In the write cycle 1, the selected pair of bit lines 3 and 4 is not precharged but the unselected pair of bit lines 5 and 6 is precharged. When the data read in the read cycle 0 and the data written in the write cycle 1 are the same, Cb × for the pair of bit lines 3 and 4 compared to the case of precharging the selected pair of bit lines 3 and 4. The charge amount can be reduced by (VDD-Vm). The pair of unselected bit lines 5 and 6 are precharged before writing is started.

Similarly, in the write cycle 2, without precharging the selected pair of bit lines 3 and 4,
The pair of unselected bit lines 5 and 6 are precharged before writing is started. When the write data in the write cycle 1 and the write data in the write cycle 2 are the same, Cb for the pair of bit lines 3 and 4 is larger than that in the case of precharging the selected pair of bit lines 3 and 4. The charge amount can be reduced by × VDD.

In the write cycle 3, since the same pair of bit lines as in the write cycle 2 is selected, the pair of bit lines 3 and 4 are not precharged before writing. When the write data in the write cycle 2 is different from the write data in the write cycle 3, the consumption of the charge amount is equal to that in the case of precharging the selected pair of bit lines 3 and 4.

In the write cycle 4, when a pair of bit lines 5 and 6 different from the write cycle 3 is selected, the pair of bit lines 3 and 4 is precharged before writing and the pair of bit lines 5 and 6 is precharged. 6 is not precharged. At this time, the amount of charge consumed is equal to that in the case of precharging the selected pair of bit lines 5 and 6.

According to the semiconductor memory device of this embodiment, a pair of bit lines not to be written, for example, 5 and 6 are precharged before writing and a pair of bit lines 3 and 4 to be written are precharged. Since charging is not performed, useless repetition of precharging and discharging of electric charges can be avoided when the same data is continuously transmitted to the same pair of bit lines. As a result, in the write cycle, it is possible to reduce the current consumption when the same data is continuously transmitted to the same pair of bit lines 3 and 4. Further, the circuit configuration is simple and can be realized more easily than in the case of the first embodiment.

FIG. 5 is a circuit diagram showing the structure of a semiconductor memory device according to the third embodiment of the present invention. In FIG. 5, 2a is a word line connected to the memory cell 1A connected to the pair of bit lines 3 and 4, and 2b is a word line connected to the pair of bit lines 5 and 6. The number of memory cells 1A, 1B is the same as the number of column selectors in the plurality of memory cells 1A, 1B having the same word line.
B is individually connected. 24 is a word line (WL) 2
Is a word line selection circuit that selectively activates one word line (WL0, WL1) 2a, 2b corresponding to the column address when the AND circuit 24A,
It is composed of a gate circuit composed of 24B.

As the precharge signal, a periodic read precharge signal (P
RC_R) 14 is provided, and the write precharge signal for the write cycle is not provided. Therefore, the precharge precharges the plurality of pairs of bit lines 3 to 6 before reading, and does not precharge the plurality of pairs of bit lines 3 to 6 before writing.

The configuration other than the above is the same as that of the conventional example shown in FIG.

In the semiconductor memory device having the above configuration, at the time of writing, the write data output from the write buffer 10 is transmitted to the pair of bit lines 3, 4 or 5, 6 selected by the column address 12. Then, one of the potentials of the selected pair of bit lines, for example, 3, 4 is pulled down to the ground voltage VSS, and the data of the memory cell 1A holding the data connected to the pair of bit lines 3, 4 is rewritten. At this time, only the word line (WL0) 2a of the memory cell 1A connected to the pair of bit lines 3 and 4 selected by the column address 12 is activated, and the memory connected to the unselected pair of bit lines 5 and 6 is activated. Word line of cell 1B (W
L1) 2b is not activated, and a pair of bit lines 3 to 6
Does not precharge. When the data read or written the previous time and the data written in the memory cell this time are the same, the current for precharging the pair of bit lines 3, 4 or 5, 6 can be reduced. Furthermore, since the word line 2b of the memory cell 1B connected to the unselected pair of bit lines 5 and 6 is not activated, no current flows through the unselected pair of bit lines 5 and 6.

FIG. 6 is a timing chart showing the operation of the circuit shown in FIG. In FIG. 6, read cycle 0 (CA0 selection /
Activation), write cycle 1 (CA0 selection / activation), write cycle 2 (CA0 selection / activation), write cycle 3 (CA0 selection / activation), write cycle 4 (CA1 selection / activation) State of clock CLK and column address in Column A
ddress, column selection signals CA0 and CA1, precharge signal PRC, and state of word lines WL0 and WL1,
The state of the pair of bit lines BL0, / BL0 and the state of the pair of bit lines BL1, / BL1 are shown.

In FIG. 6, read cycle 0, write cycle 1, write cycle 2, write cycle 3
Then, since the column selection signal CA0 is "H" and the column selection signal CA1 is "L", the pair of bit lines BL0, / BL0 is in the selected state and the pair of bit lines BL1, / BL1 is It is in a non-selected state. In the write cycle 4, the column selection signal CA0 is "L" and the column selection signal CA1 is "H".
The pair of bit lines BL0 and / BL0 are in a non-selected state,
The pair of bit lines BL1, / BL1 are in the selected state.

In the read cycle 0, the pair of bit lines selected by the column address lowers one potential from the power supply voltage VDD to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS. In each of the write cycles 1 to 4, the pair of bit lines selected by the column address drop one potential from the previous state to the ground voltage VSS by the write operation by the write buffer 10. Further, the potentials of the pair of unselected bit lines also maintain the power supply voltage VDD. When the write data is inverted, one potential of the selected pair of bit lines drops from the power supply voltage VDD to the ground voltage VSS and the other potential rises from the ground voltage VSS to the power supply voltage VDD.

Here, each cycle will be described in detail.

In the read cycle 0, the column selection signal CA0 is selected (activated) and the memory cell 1A is selected.
The data is read out from one of the pair and the potential of one of the pair of precharged bit lines 3 and 4 drops to the intermediate potential Vm between the power supply voltage VDD and the ground voltage VSS. At this time, since the unselected word line WL1 is not activated, the pair of unselected bit lines 5 and 6 remain precharged to the power supply voltage VDD.

Next, in the write cycle 1, 1
The paired bit lines 3 to 6 are not precharged. Data read in read cycle 0 and write cycle 1
When the same data is written in, the selected pair of bit lines 3 and 4 is C compared to the case of precharging.
The charge amount can be reduced by b × (VDD−Vm).

Similarly, in the write cycle 2, the pair of bit lines 5 and 6 are not precharged. When the write data in the write cycle 1 and the write data in the write cycle 2 are the same, Cb for the pair of bit lines 3 and 4 is larger than that in the case of precharging the selected pair of bit lines 3 and 4. The charge amount can be reduced by × VDD.

In write cycle 3, the same pair of bit lines 3 and 4 as in write cycle 2 are selected and 1
The paired bit lines 3 to 6 are not precharged. Write data in write cycle 2 and write cycle 3
If the write data is different from the write data in, the consumption of the charge amount is equal to that in the case of precharging the selected pair of bit lines 3 and 4.

In the write cycle 4, even if a pair of bit lines different from the write cycle 3 is selected, the pair of bit lines 3 to 6 is not precharged. At this time, the amount of charge consumed is equal to that in the case of precharging the selected pair of bit lines 5 and 6. Since no current flows from the unselected pair of bit lines 5 and 6 to the memory cells 1A and 1B in the read cycle 0 to the write cycle 3, the memory cells connected to the unselected pair of bit lines 5 and 6 The charge amount can be reduced by Cb × (VDD−Vm) every cycle as compared with the case of activating the 1B word line WL1 and precharging a pair of unselected bit lines.

According to this embodiment, the same number of column selectors as the number of column selectors are provided in a plurality of memory cells in the same row of word lines, and the plurality of memory cells 1A and 1B are individually associated with the column addresses in a one-to-one correspondence. One word line 2a, 2b connected to the column address corresponding to the column address is activated by the word line selection circuit 24 to precharge a plurality of pairs of bit lines 3 to 6 before reading, and a plurality of bit lines 3 to 6 before writing. Since the paired bit lines 3 to 6 are not precharged, it is possible to avoid wasteful repetition of precharge and charge discharge when continuously transmitting the same data to the same pair of bit lines. it can. As a result, in the write cycle, it is possible to reduce the current consumption when continuously transmitting the same data to the same pair of bit lines. Moreover, by selecting only one word line corresponding to the selected bit line and not activating the word line corresponding to the non-selected bit line,
Since no current flows from the bit line to the memory cell, the current flowing through the non-selected bit line can be reduced.

In each of the above-described first to third embodiments, when the column selection address is arranged on the upper side of the memory address, the memory access is made as compared with the case where the column selection address is arranged on the lower side of the memory address. At this time, the probability that the same column, that is, the same pair of bit lines is selected is increased, and the current consumption can be further reduced.

Further, by using the memory cells of the horizontal layout, the number of word lines is increased and the number of column selections, that is, the number of bit lines is decreased while maintaining the bit line length which is almost the same as the memory cell of the vertical layout as a memory macro. Thus, the probability of selecting the same column, that is, selecting the same pair of bit lines can be increased, and the bit line precharge current can be reduced.

[0078]

According to the semiconductor memory device of the first aspect of the present invention, since the bit line connected to the memory cell to be written is not precharged before the write operation, the same is continuously applied. When transmitting data to the same bit line, useless repetition of precharge and discharge of charges can be avoided. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. That is, when the write data in the write cycle is the same as the write data in the previous write cycle, the current that drives the bit line can be reduced.

According to the semiconductor memory device of the second aspect of the present invention, when the column address accessed last time and the column address accessed this time match, the column address specified this time is accessed before writing. Since the bit line to be precharged is not precharged, it is possible to avoid wasteful repetition of precharge and discharge of charge when continuously transmitting the same data to the same bit line. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line.

According to the semiconductor memory device of the third aspect of the present invention, the same effect as that of the second aspect can be obtained.

According to the semiconductor memory device of the fourth aspect of the present invention, in addition to the same effect as the second aspect, a weak precharge circuit is provided for bit lines other than the bit line designated by the column address accessed this time. I will precharge with
It is possible to avoid the voltage drop of bit lines other than the bit line specified by the column address accessed this time.

According to the semiconductor memory device of the fifth aspect of the present invention, the bit lines which are not the write target are precharged before the write and the bit lines which are the write target are not precharged. Therefore, when the same data is transmitted to the same bit line, it is possible to avoid wasteful repetition of precharge and discharge of charges. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. Further, the circuit configuration is simple and can be realized more easily than in the case of claim 2.

According to the semiconductor memory device of the sixth aspect of the present invention, the same effect as that of the fifth aspect can be obtained.

According to the semiconductor memory device of the seventh aspect of the present invention, the same number of column selectors as the number of column selectors are provided in a plurality of memory cells having word lines in the same row, and the plurality of word lines correspond to column addresses in a one-to-one correspondence. Only one word line individually connected to a memory cell and corresponding to a column address is activated by a word line selection circuit, a plurality of bit lines are precharged before reading, and a plurality of bit lines are written before writing. Therefore, when the same data is continuously transmitted to the same bit line, it is possible to avoid wasteful repetition of precharge and discharge of charges. As a result, in the write cycle, it is possible to reduce current consumption when continuously transmitting the same data to the same bit line. Moreover, since only one word line corresponding to the selected bit line is selected and the word line corresponding to the non-selected bit line is not activated, no current flows from the bit line to the memory cell. Therefore, the current flowing through the non-selected bit line can be reduced.

According to the semiconductor memory device of the eighth aspect of the present invention, since the column address for selecting the bit line is arranged in the higher order of the memory address, the change of the bit line selected in each write cycle is reduced. This makes it possible to increase the probability that the same bit line will be continuously selected when writing data continuously, and further reduce current consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operation according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a timing diagram showing an operation according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

FIG. 8 is a timing chart showing an operation in a conventional example.

[Explanation of symbols]

1A, 1B memory cells 2,2a, 2b Word line 3-6 bit lines 7 Precharge / equalize circuit 8, 9 column selection signal 10 write buffer 11 column address decoder 12 column address 13 Write precharge signal 14 Read precharge signal 15, 19, 20 Precharge signal 16 Weak precharge signal 17 column address register 18 Comparator

Claims (8)

[Claims] 1. A memory cell, a bit line connected to the memory cell, and a precharge circuit connected to the bit line, the memory cell being connected to the memory cell to be written before a write operation. A semiconductor memory device characterized in that a bit line is not precharged. 2. A plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of column selector circuits for selecting one bit line among the plurality of bit lines, and a plurality of the plurality of column selector circuits. A plurality of precharge circuits respectively connected to the bit lines, a hold circuit for holding a column address for selecting the column selector circuit, a previously accessed column address held in the hold circuit, and a currently accessed column address. It is specified by the comparator that compares the column address with the column address that is accessed this time before writing if the previously accessed column address and the currently accessed column address match based on the comparison result of the comparator. Semiconductor memory having a precharge control circuit for preventing precharge of the bit line Storage device. 3. A precharge control circuit is provided in a supply path of a periodic precharge signal for a write cycle to a plurality of precharge circuits, and a column address last accessed based on a comparison result of a comparator. 3. The semiconductor memory device according to claim 2, further comprising: a gate circuit that shuts off when the column address accessed this time matches and conducts when the column address does not match. 4. Bits other than the bit line designated by the column address accessed this time are further provided with a plurality of weak precharge circuits each connected to a plurality of bit lines and having a weaker current driving capability than the plurality of precharge circuits. 3. The semiconductor memory device according to claim 2, wherein a weak precharge circuit connected to the line is operated. 5. A plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a plurality of column selector circuits for selecting one bit line among the plurality of bit lines, and a plurality of the plurality of column selector circuits. A plurality of precharge circuits respectively connected to the bit lines, a column address decoder for selecting the column selector circuit, and a plurality of column selection signals and precharge signals output from the column address decoder A semiconductor memory device comprising: a precharge control circuit that precharges a bit line that is not a write target and does not precharge a bit line that is a write target. 6. A precharge control circuit is provided in a supply path of a periodic precharge signal for a write cycle to a plurality of precharge circuits, and a column selection signal selected from a plurality of column selection signals is selected. A gate circuit for interrupting the supply path of the precharge signal to the precharge circuit corresponding to the signal and for making the supply path of the precharge signal to the precharge circuit corresponding to the column selection signal in the non-selected state conductive. 5. The semiconductor storage device according to item 5. 7. A plurality of memory cells arranged in an array, a plurality of bit lines connected to the plurality of memory cells, and a plurality of column selectors for selecting one bit line of the plurality of bit lines. Circuit, a plurality of precharge circuits respectively connected to the plurality of bit lines, and a word line connected to the plurality of memory cells, wherein the word line is a column selector in a plurality of memory cells in the same row. The same number as the number is provided, and each word line selection circuit activates only one word line corresponding to the column address, which is individually connected to the plurality of memory cells in a one-to-one correspondence with the column address. It is characterized in that the plurality of bit lines are precharged before reading, and the plurality of bit lines are not precharged before writing. The semiconductor memory device according to. 8. The semiconductor memory device according to claim 1, wherein a column address for selecting a bit line is arranged above a memory address.