JP2003263340A - Debug device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store only information necessary for a debugging operation in a trace memory. <P>SOLUTION: This debug device stores, in the trace memory 16, trace information including at least one of processor information generated by a microprocessor 11, a memory 12 and an I/O 13 when the microprocessor 11 is run. A trace information control part 14 uses a trace data input part 15 to store processor information selected arbitrarily by a user via a user interface of a debugger 21 in the trace memory 16 as trace information. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging device that supports debugging of equipment using a microprocessor, and more particularly to a debugging device that can effectively utilize memory resources of a trace memory.

[0002]

2. Description of the Related Art In debugging software for a microprocessor, a debugging device such as an in-circuit emulator (In-Circuit Emulator) is often used. The in-circuit emulator has a "tracer function" that shows the traced result of the execution status of the program, a "breakpoint function" that specifies the place to stop the program, and a program written in machine language as functions to support debugging work. There is a "disassembly function" for converting a to assembly language.

When a defective portion of a program is detected and its cause is specified, information on the cause of the defectiveness is used by using information such as a bus state at the time of processor execution stored in a memory element (trace memory) by a tracer function. It is necessary to perform analysis work.

The information required to identify the cause of a defect differs from program to program.
The user could not set the information to be stored in the trace memory as the trace information. Therefore, memory resources cannot be effectively used because information that is not necessary for debugging work is stored in the trace memory. Further, the user has to select the information necessary for the debugging work from the information stored in the trace memory, so that the debugging work cannot be performed efficiently.

As a conventional technique for effectively utilizing the trace memory, there is a "microprogram debugging method" disclosed in Japanese Patent Laid-Open No. 5-158735. According to the present invention, it is possible to perform multi-step tracing with a small-capacity storage element, but it is not possible to select and store information necessary for debugging work.

Further, as another conventional technique for effectively utilizing the trace memory, Japanese Patent Laid-Open No. 6-197 is known.
There is an "emulator" disclosed in Japanese Patent No. 36. The present invention saves the capacity of the trace memory and facilitates the analysis work by causing the target microprocessor to execute the program in units of one instruction only in a predetermined area of the debug-symmetrical program. However, according to the present invention, when executing a predetermined program area, it is necessary to break and register information in the trace memory, so that trace information cannot be collected efficiently.

Further, as another conventional technique for effectively utilizing the trace memory, Japanese Patent Laid-Open No. 7-1
There is a "microprocessor bus trace device" disclosed in Japanese Patent No. 3806. According to the present invention, the trace information can be stored in the trace memory only when it matches the preset processor signal state. However, according to the present invention, it is necessary to preset the processor signal state of the information to be traced, so that the cause of the defect may not be identified.

As described above, in the conventional technique, it is not possible to efficiently perform the debugging work by storing only the information necessary for the debugging work in the trace memory.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to store only the information necessary for debugging in a trace memory.

[0010]

In order to achieve the above-mentioned object, the present invention is a debug device for storing in a trace memory trace information constituted by including at least one processor information generated at the time of processor execution. In addition, the debug device is characterized in that the processor information arbitrarily selected by the user is stored in the trace memory as the trace information. This allows the trace memory to store only the information required by the program to be debugged. That is, it is possible to prevent the trace information from including information unnecessary for debugging the program.

In the above configuration, means for allowing the user to set the information indicating the processor information to be stored in the trace memory as the trace information as the trace condition, and the trace condition being replaced with the identification code and included in the trace information and stored in the trace memory It is preferable to further have means. In this way, the trace information of the trace condition is not stored in the trace memory, in other words, the trace condition is converted into the identification code and then stored in the trace memory, so that the trace memory can be used efficiently. Further, it is more preferable that the processor information stored in the trace memory as the trace information is set for each trace condition. In this way, the trace information required for each trace condition is stored in the trace memory. For example, even the same processor information may be stored as trace information in the trace memory or may not be stored as unnecessary information depending on the debug location of the program. In other words, it is possible to prevent unnecessary information from being included in the trace information and necessary information from not being included in the trace information, depending on the location of the program.

In any of the above-mentioned configurations of the present invention, it is preferable that the apparatus further comprises means for presenting the trace information stored in the trace memory to the user. This allows
For example, trace information can be set / presented according to the program to be debugged. In addition, it is possible not to present the trace condition as the trace information. Alternatively, trace information can be set / presented for each trace condition. Therefore, the user can efficiently perform the debugging work by using the presented trace information.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment in which the present invention is preferably implemented will be described. In Figure 1,
1 shows a debug device according to the present embodiment. This debugging device has an emulator 10 and a host computer 20. The emulator 10 is the microprocessor 1
1, memory 12, I / O 13, trace information control unit 1
4, a trace data input unit 15, a trace memory 16 and a trace data transfer unit 17. The microprocessor 11, the memory 12, and the I / O 13 are functional units to be debugged, and output processor information such as an address bus and a data bus. The trace information control unit 14
Information preset by the user is extracted as trace information from the information included in the input processor information. The trace information input unit 15 is the trace information control unit 1.
The trace information extracted by 4 is stored in the trace memory 16. The trace memory 16 is a memory that stores trace information, and can be a RAM, NVRAM, or the like. The trace data transfer unit 17 sends the trace information stored in the trace memory 16 to the host computer 20. The host computer 20 has a debugger 21 and a trace presentation unit 22. The debugger 21 is a user interface (U
I: For example, a keyboard, a pointing device, a touch panel, a voice recognition device, etc.). The user
The trace information control unit 14 sets information to be extracted from the processor information as trace information via the UI. The debugger 21 acquires the trace information stored in the trace memory 16 from the emulator 10 via the trace information transfer unit 17. The trace display unit 22 is a device for presenting the trace information to the user, and for example, a liquid crystal panel as an image display unit, a speaker as an audio output unit, or the like can be applied.

The operation of the debug device according to the present embodiment will be described. The user uses the UI provided in the debugger 21 to set the type of information to be extracted as the trace information. The setting contents are notified to the trace information control unit 14,
For example, it is stored in a non-volatile memory or the like. After that, when the trace is started, the processor information is input from the microprocessor 11, the memory 12 and the I / O 13 to the trace information control unit 14. The trace information control unit 14 extracts information to be used as trace information from the processor information based on the held setting contents. The trace information input unit 15 stores the trace information extracted by the trace information control unit 14 in the trace memory 16. As a result, only the information desired by the user can be stored in the trace memory 16 as the trace information.

The trace data transfer unit 17 reads the trace information from the trace memory 16 and sends it to the host computer 20. When the debugger 21 acquires the trace information transmitted by the trace data transfer unit 17, it uses the trace presenting unit 22 to present the trace information to the user. Thereby, only the information desired by the user can be presented to the user as trace information.

[Second Embodiment] A second embodiment in which the present invention is preferably implemented will be described. FIG. 2 shows the debug device according to the present embodiment. The debug device of this embodiment is the same as that of the first embodiment except that it has a trace condition control unit 18 instead of the trace information control unit 14. The trace condition control unit 18 replaces, in the information included in the input processor information, the part that indicates the trace condition in the information that matches the condition (trace condition) preset by the user with the identification code, and uses it as the trace information. It is input to the trace data input unit 15. Further, the debugger 21 sets the timing information stored as trace information in the trace memory 16 as a trace condition.
Further, in the present embodiment, the user uses the UI provided in the debugger 21 to set the trace condition.

The operation of the debug device according to the present embodiment will be described. The user sets the trace condition using the UI. The setting content is notified to the trace condition control unit 18, and is stored in, for example, a non-volatile memory. afterwards,
When the trace is started, the processor information is input from the microprocessor 11, the memory 12 and the I / O 13 to the trace condition control unit 18. Trace condition control unit 18
Of the information included in the input processor information,
The trace condition information of information that matches the preset trace condition is replaced with the identification code and input to the trace data input unit 15. The trace data input unit 15 stores the input trace information in the trace memory 16.
As a result, the trace condition of the information that matches the condition set by the user is converted into the identification code and the trace memory 1
6 can be stored. For example, the information set as the trace condition can be set not to be stored in the trace memory 16 as the trace information. In addition, the trace presentation unit 2
Since the trace information presented by 2 to the user does not include information unnecessary for the debugging work, the debugging work can be performed efficiently.

[Third Embodiment] A third embodiment preferably implementing the present invention will be described. FIG. 3 shows the debug device according to the present embodiment. The debug device of the present embodiment further includes a trace condition control unit 18,
It is similar to the first embodiment. In this embodiment, the user uses the UI provided in the debugger 21 to set the timing information to be stored as trace information in the trace memory 16 as the trace condition. Further, processor information to be stored as trace information in the trace memory 16 is set for each trace condition.

The operation of the debug device according to the present embodiment will be described. The user uses the UI to set the type of information to be stored in the trace memory 16 as trace information among the information included in the processor information and the trace condition. The setting contents are notified to the trace information control unit 14 and the trace condition control unit 18, respectively, and are held in a non-volatile memory or the like. After that, when the trace is started, the processor information shows the microprocessor 11, the memory 12, and the I
/ O13 is input to the trace condition control unit 18. The trace condition control unit 18 inputs, to the trace information control unit 14, information that matches the trace condition among the information included in the processor information. The trace information control unit 14 stores only the type of information set by the user among the information input from the trace condition control unit 18 in the trace memory 16 as the trace information.

The debugger 21 acquires the trace information stored in the trace memory 16 via the trace data transfer unit 17, and based on the trace condition and the type of the trace information set for each trace condition, the trace content. Is presented to the user as a trace result using the trace presenting unit 22.

As a result, the trace information required for each trace condition is stored in the trace memory. In other words, it is possible to control storing only the necessary information in the trace memory without storing unnecessary information in the trace memory according to the debugged portion of the program.

FIG. 4 shows an example of the trace information and the contents of information set for each trace condition and stored in the trace memory as trace information. Trace information is (D1)
In the case of the processor information 1 to 4 shown in (4), the information fetched in the trace memory 16 is (D2),
(D3). When the trace condition A (D2) is set, only the processor information 1 is loaded, and when the trace condition C (D3) is set, the processor information 2 and 4 are loaded. In the execution state (D4), the processor information 1 is used under the trace condition A, and the processor information 2 and 4 are used as the processor information under the trace condition C.
It becomes a writing target to the No. Therefore, trace memory 1
The contents captured in 6 are as shown in (D5), and the data stored in the trace memory 16 has the structure shown in (D6). By doing so, the trace information can be set / displayed by the program to be debugged. Also, the trace condition can be prevented from being displayed as trace information. Furthermore, trace information can be set and displayed for each trace condition. That is, the debug state enables efficient debugging.

The above embodiments are examples of preferred embodiments of the present invention, and the present invention can be variously modified without departing from the spirit thereof.

[0024]

As is apparent from the above description, according to the present invention, only the information necessary for debugging the program to be debugged can be stored in the trace memory as the trace information. Therefore, only the information necessary for debugging can be presented to the user, so that debugging can be performed efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a debug device according to a first exemplary embodiment in which the present invention is preferably implemented.

FIG. 2 is a block diagram showing a configuration of a debug device according to a second exemplary embodiment in which the present invention is preferably implemented.

FIG. 3 is a block diagram showing a configuration of a debug device according to a third exemplary embodiment in which the present invention is preferably implemented.

FIG. 4 is a diagram showing an example of contents of trace information and information set for each trace condition and stored in a trace memory as trace information.

[Explanation of symbols]

10 emulator 11 microprocessors 12 memories 13 I / O 14 Trace information control unit 15 Trace data input section 16 trace memory 17 Trace data transfer unit 18 Trace condition controller 20 Host computer 21 Debugger 22 Trace presentation section

Claims (4)

[Claims] 1. A debug device for storing, in a trace memory, trace information configured to include at least one processor information generated when a processor is executed, wherein the processor information arbitrarily selected by a user is stored in the trace memory. A debug device characterized by storing as information in the trace memory. 2. Means for causing a user to set information indicating the processor information to be stored in the trace memory as the trace information as a trace condition, and replacing the trace condition with an identification code and including it in the trace information to the trace memory. The debug device according to claim 1, further comprising a storing unit. 3. The debug device according to claim 2, wherein the processor information stored in the trace memory as the trace information is set for each trace condition. 4. The debug device according to claim 1, further comprising means for presenting the trace information stored in the trace memory to a user.