JP2003259235A - Image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relieve transfer delay of a control signal for controlling reading of an image pickup device. <P>SOLUTION: The image pickup device has a pixel area (1) composed of a plurality of pixels and for generating electric charge corresponding to incident light quantity, horizontal scanning circuits (3 and 4) for reading the electric charge from the pixel area in each row, a pad (6) for inputting a control signal for controlling the horizontal scanning circuits, and a signal line for transmitting the control signal from the pad to the horizontal scanning circuits. The signal line is wired such that the ratio of the distance between the pad and the horizontal scanning circuit (3) to the distance between the pad and the horizontal scanning circuit (4) is smaller than a prescribed ratio. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device, and more particularly to a structure of an output system of a solid-state image pickup device which is widely used for an image input device such as a video camera or a digital still camera.

[0002]

2. Description of the Related Art In recent years, in solid-state imaging devices, the cell size of photoelectric conversion elements has been energetically reduced by using a miniaturization process, and the number of pixels has been increased. Such solid-state image pickup devices include, for example, CCD (charge coupled device) type, M
There are OS type, AMI, CMD, BASIS and the like.

FIG. 5 shows a schematic structure of a conventional area sensor. In the figure, reference numeral 101 denotes a pixel region that includes a plurality of pixels and that generates charges according to the amount of incident light, 102 denotes a vertical scanning circuit that controls the vertical reading of the charges that are generated in the pixel region 101, and 103 and 104 denote pixels. Area 1
01 is a horizontal scanning circuit for controlling the horizontal reading of the charges generated in 01. The above structure is usually integrally formed on the same chip, and a plurality of pads 105 for electrically connecting to an external device are formed around the same chip.

In the example shown in FIG. 5, a signal for controlling the horizontal scanning circuits 103 and 104 is input from the pad 106 among the plurality of pads 105, and the horizontal scanning circuits 103 and 104 are controlled via the signal line 107. A signal is input.

FIG. 6 shows another configuration example of the conventional area sensor. 6, the same components as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted. In the example shown in FIG.
Of the plurality of pads 105, a signal for controlling the horizontal scanning line circuit 103 is input from the pad 108 and a signal for controlling the horizontal scanning line circuit 104 is input separately from the pad 109 to connect the signal lines 110 and 111. Control signals are input to the horizontal scanning circuits 103 and 104, respectively.

FIG. 7 also shows horizontal scanning circuits 103 and 1.
It is a figure which shows the detailed structure when 04 is a shift register. In this case, the control signal is a clock signal, and the internal control signal generation unit generates clock signals CLK1 and CLK2 whose phases are mutually shifted by 180 °, and switches of each transfer stage of the shift register via the signal lines 122a and 122b, respectively. Entered in.

[0007]

However, in the configuration shown in FIG. 5, since the signal lines from the pad 106 to the horizontal scanning circuits 103 and 104 have different lengths, horizontal scanning is performed after the control signal is input to the pad 106. There is a slight difference between the time required to reach the circuit 103 and the time required to reach the horizontal scanning circuit 104.

On the other hand, in the structure shown in FIG.
And 109 to the horizontal scanning circuits 103 and 104 can have substantially the same length. However, as shown in FIG. 7, in both FIG. 5 and FIG. 6, there are signal lines for transmitting the input control signal in the horizontal scanning circuits 103 and 104, and the signal line 107 and the pad 10 are provided.
There is a difference in time until the control signal arrives between the side closer to 8 and 109 and the side farther away.

In particular, a large-format sensor has a large delay due to a signal line, and a sensor having a large number of pixels has a short reading period, which has a large effect. The delay difference between the horizontal scanning circuits may cause, for example, a shift in the transfer timing or the reset timing at the time of horizontal scanning, resulting in an offset difference between output channels and an output variation such as shading.

The present invention has been made in view of the above problems, and an object thereof is to alleviate a transfer delay of a control signal for controlling readout of an image pickup device.

[0011]

In order to achieve the above object, an image pickup device of the present invention comprises a plurality of pixels, photoelectric conversion means for generating electric charges according to the amount of incident light, and photoelectric conversion means for each row. First and second for reading out charges for each
Reading means, input means for inputting a control signal for controlling the first and second reading means, and a signal for transmitting the control signal from the input means to the first and second reading means. The signal line has a ratio of a distance from the input unit to the first reading unit and a distance from the input unit to the second reading unit to be smaller than a predetermined ratio. To be wired.

According to a preferred aspect of the present invention, the signal line is branched at an intermediate point between the first and second reading means.

According to a preferred aspect of the present invention, the signal line is further branched at an intermediate point in the longitudinal direction of each of the first and second reading means.

Preferably, in the signal line, the distance from the input means to the first reading means and the distance from the input means to the second reading means are substantially the same.

According to a preferred aspect of the present invention, the signal line is branched at a substantially central point of the first and second reading means.

According to a preferred aspect of the present invention, the signal line is further branched at a substantially central point in the longitudinal direction of each of the first and second reading means.

According to a preferred aspect of the present invention, the first and second reading means are shift registers, and the transfer stages of the shift registers have substantially the same number of branched signal lines. Connect the transfer stage.

According to a preferred aspect of the present invention, the image pickup device is a CMOS type image pickup device.

[0019]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
As an example of the configuration of the image pickup apparatus in the embodiment of the
The structure of an OS type solid-state imaging device is shown. In FIG. 1, reference numeral 1 is a pixel region that includes a plurality of pixels and that generates charges according to the amount of incident light. Reference numeral 2 is a vertical scanning circuit that controls vertical reading of charges generated in the pixel region 1. Reference numerals 3 and 4 are pixels. It is a horizontal scanning circuit that controls horizontal reading of charges generated in the region 1. The above structure is usually integrally formed on the same chip, and a plurality of pads 5 for electrically connecting to an external device are formed around the same chip.

Further, among the plurality of pads 5, the pad 6 is a pad for inputting a control signal, and the control signal is input to the horizontal scanning circuits 3 and 4 via the signal line 7.

In FIG. 1, for convenience of illustration, the pixel area 1 is vertically 4
Although a case is shown in which 12 pixels arranged in columns and 3 rows in the horizontal direction are included, it is actually composed of a very large number of pixels.

The pixel has photodiodes D11 to D43 for generating optical signal charges, and the anode side is grounded in this example. The cathode sides of the photodiodes D11 to D43 are connected to the gates of the amplification MOSs M311 to M343 via the transfer MOSs M111 to M143. The gates of the amplification MOSs M311 to M343 have reset MOS M2 for resetting them.
The sources of 11 to M243 are connected, and the reset MOS
The drains of M211 to M243 are connected to the reset power supply. Further, amplification MOSs M311 to M343
Drain is connected to the power supply and source is select MOS M
It is connected to the drains of 411 to M443.

The gate of the transfer MOS M111 is
It is connected to a first row selection line (vertical scanning line) PTX1 which extends in the horizontal direction. Similar transfer MOSs M121, M131, M1 of other pixel cells arranged in the same row
The gates of 41 are also commonly connected to the first row selection line PTX1. The gate of the reset MOS M211 has a second row selection line (vertical scanning line) PR which is arranged to extend in the horizontal direction.
Connected to ES1. Similar reset MOSs M221, M231, M24 of other pixel cells arranged in the same row
The gates of 1 are also commonly connected to the second row selection line PRES1. The gate of the selection MOS M411 has a third row selection line (vertical scanning line) PSEL arranged to extend in the horizontal direction.
Connected to 1. Gates of similar selection MOSs M421, M431, M441 of other pixel cells arranged in the same row are also commonly connected to the third row selection line PSEL1. These first to third row selection lines are used for the vertical scanning circuit block 2
And a signal voltage is supplied based on the operation timing described later.

The remaining rows shown in FIG. 1 are provided with pixel cells and row selection lines having the same structure. These row selection lines include PTX2 to PTX3, PRES2 to PRES3, and PTX formed by the vertical scanning circuit block 2.
SEL2-PSEL3 are supplied.

The source of the selection MOS M411 is
It is connected to a vertical signal line V1 arranged to extend in the vertical direction. Similar selection MOS of pixel cells arranged in the same column
The sources of M412 and M413 are also connected to the vertical signal line V1. The vertical signal line V1 is connected to the load MOS N82. The remaining vertical signal lines V2 to V shown in FIG.
Similarly, in 4, the selection MOS and the load MOS are connected. Further, the sources of the load MOSs N82 to N85 are connected to the common GND line 4, and the gates are connected to the gate of the input MOS N81 and the voltage input terminal 8.

The vertical signal line V1 is connected to a capacitor CT1 for temporarily holding a signal via a clamp capacitor C01 and a transfer switch N201, and connected to an inverting input terminal of the differential amplifier circuit 11 via a horizontal transfer switch N301. To be done.
The non-inverting input terminal of the differential amplifier circuit 11 is the reset voltage Vres of the horizontal output line, and the inverting input terminal is the reset switch N.
12 to the reset voltage Vres of the horizontal output line. The terminal on the opposite side of the signal holding capacitor CT1 is grounded. Clamp capacitance C01 and transfer switch N2
The connection point with 01 is connected to the clamp power supply via the clamp switch N101. The gate of the horizontal transfer switch N301 is connected to the column selection line H1 and is connected to the horizontal scanning circuit block 4. A read circuit having a similar configuration is provided for the remaining vertical signal lines V2 to V4 shown in FIG. In addition, the clamp switch N connected to each row
101-N104 gates and transfer switch N301
~ N304 gate is clamp signal input terminal PC0R
And a transfer signal input terminal PT, which are commonly connected to each other, and are supplied with signal voltages based on operation timings described later.

Next, the operation of the image pickup apparatus having the above configuration will be described with reference to FIG. Photodiode D
Prior to reading out the optical signal charges from 11 to D43,
The signal φPRES1 to the gates of the reset MOSs M211 to M241 becomes high level. As a result, the gates of the amplification MOSs M311 to M341 are reset to the reset power supply. Reset MOS M211 to M241
After the signal .phi.PRES1 to the gate of the clamp switches N101 to N104 becomes high level at the same time as the signal .phi.PRES1 to the low level, the selection M
Signal φPSEL to the gates of OS M411 to M441
1 becomes high level. As a result, the reset signal (noise signal) on which the reset noise is superimposed is read out to the vertical signal lines V1 to V4, and the clamp capacitors C01 to C04.
Clamped to. At the same time, transfer switches N201 to N2
The signal φPT to the gate of 04 becomes high level, and the signal holding capacitors CT1 to CT4 are reset to the clamp voltage.

Next, the clamp switches N101 to N10
The signal φPC0R to the gate of 4 returns to the low level. Next, the signal φPTX1 to the gates of the transfer MOSs M111 to M141 becomes high level, and the optical signal charges of the photodiodes D11 to D41 change to the amplification MOS M31.
At the same time as being transferred to the gates of 1 to M341, optical signals are read out to the vertical signal lines V1 to V4. Next, transfer MOS
After the signal φPTX1 to the gates of M111 to M141 returns to the low level, the transfer switches N201 to N20
The signal φPT to the gate of 4 goes low. As a result, the change (optical signal) from the reset signal is read out to the signal holding capacitors CT1 to CT4. By the operation up to this point, the optical signals of the pixels connected to the first row are held in the signal holding capacitors CT1 to CT4 connected to the respective columns.

Next, reset MOSs M211 to M24
Signal φ PRES1 to the gate of 1 and transfer MOS M
The signal φPTX1 to the gates of 111 to M141 is at the high level, the gate control signals of the switches N81 to M84 are at the low level, and the optical signal charges of the photodiodes D11 to D41 are reset.

After that, the horizontal transfer switches N3 of each column are supplied by the signals φH1 to φH4 from the horizontal scanning circuits 3 and 4.
The gates of 01 to N304 sequentially become high level, and the voltages held in the signal holding capacitors CT1 to CT4 are sequentially read to the inverting input terminal of the differential amplifier circuit 11 and sequentially output to the output terminal OUT. The reset switch 12 resets the inverting input terminal of the differential amplifier circuit 11 to the reset voltage Vres of the horizontal output line between signal readings in each column. With the above, reading of the pixel cells connected to the first row is completed.

Similarly, the signals of the pixel cells connected to the second and subsequent rows are sequentially read by the signal from the vertical scanning circuit block, and the reading of all pixel cells is completed.

Further, in the above-mentioned configuration, since charge is read from each row by using the two-system reading circuit, the MOS switches 13 and 14 are alternately turned on by using the signal φPCHSEL and its inverted signal, so that the amplifier 15 causes the pixels to be read. The signals read out in the order of arrangement are output.

As described above, the horizontal scanning circuits 3 and 4
Outputs φH1 to φH4 based on a control signal input from the pad 6 so that the charges read from each pixel are sequentially transferred to the differential amplifier circuit 11. In the first embodiment, as shown in FIG. 1, the signal line 7 is a wiring that branches at a substantially central point of the horizontal scanning circuits 3 and 4, so that the distance from the pad 6 to the horizontal scanning circuit 3 can be increased. , The distance from the pad 6 to the horizontal scanning circuit 4 becomes substantially equal. For this reason,
Reading can be performed without a delay difference between the horizontal scanning circuits 3 and 4.

If the wiring is made redundant in order to reduce the difference in the transfer delay of the control signal, then the reading process will take a long time. This causes a timing difference with other signal processing, and therefore the distance from the pad 6 to the horizontal scanning circuit 3 and the distance from the pad 6 to the horizontal scanning circuit 4 are increased.
It is preferable to use the shortest wiring as long as the ratio of the distances to the distance is less than or equal to a predetermined ratio.

<Second Embodiment> Next, a second embodiment of the present invention will be described.

In the second embodiment, in addition to the signal line branch wiring described in the first embodiment, the horizontal scanning circuit 3 is used.
A configuration for reducing the drive delay inside 4 and 4 will be described.

FIG. 3 is a block diagram showing the concept of wiring of signal lines in the image pickup apparatus according to the second embodiment. Figure 1
The same reference numbers are given to the same configurations as those shown in FIG. The configuration shown in FIG. 3 differs from the configuration shown in FIG. 1 in the wiring of the signal line 17 for transmitting a control signal for controlling the horizontal scanning circuits 3 and 4.

As shown in FIG. 3, the signal line 17 first branches at a substantially central point between the horizontal scanning circuits 3 and 4. Further, the horizontal scanning circuits 3 and 4 are branched at substantially central points in the longitudinal direction. With such wiring, the control signal transmission delay inside the horizontal scanning circuits 3 and 4 can be alleviated.

FIG. 4 is a diagram showing an example of a detailed circuit configuration of a horizontal scanning circuit in the case where a signal line is further branched in addition to the branch shown in FIG. 3 and finally each horizontal scanning circuit is branched into four. Is. In the configuration shown in FIG. 4, the horizontal scanning circuit is composed of a shift register.

In the figure, the control signal (clock signal in this case) input from the pad 6 is the horizontal scanning circuits 3 and 4.
It is input to the internal control signal generation unit 21 provided in each. The internal control signal generator 21 has a phase of 180 ° with respect to each other.
The shifted clocks CLK1 and CLK2 are generated and input to the switch SW of each transfer stage of the shift register via the signal lines 27a and 27b, respectively. As can be seen from FIG. 4, since the signal line length from the pad 6 to each switch is equal, the switches can be driven without delay between the switches.

Although FIG. 4 shows a shift register composed of four transfer stages, in reality, it corresponds to the number of pixels arranged in one row of the pixel area, and a very large number of transfer stages are provided. Have. Therefore, when the signal line is finally branched into four lines as shown in FIG. 4, for example, the transfer stage of about 1/4 of the number of pixels in one row is controlled per branch line.

Further, the number of branching of the signal line in each horizontal scanning circuit is not limited to the above, and it is possible to wire any number. However, if the wiring is made redundant in order to alleviate the transfer delay difference of the control signal, then the read processing will take time this time. This is
As it may cause the timing to be out of sync with other signal processing,
It is preferable to perform the wiring in consideration of the delay difference related to the transfer of the control signal, the time required for the read processing, and the timing of other signal processing.

[0044]

As described above, according to the present invention, it is possible to reduce the transfer delay of the control signal for controlling the reading of the image pickup device.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of drive signals of the image pickup apparatus according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of an image pickup apparatus according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a detailed configuration of a horizontal scanning circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional imaging device.

FIG. 6 is a block diagram showing another configuration of a conventional imaging device.

FIG. 7 is a diagram showing a detailed configuration of a conventional horizontal scanning circuit.

[Explanation of symbols]

1 pixel area 2 Vertical scanning circuit 3, 4 horizontal scanning circuit 5, 6 pads 7, 17, 27a, 27b Signal line

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takumi Hiyama             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Tetsuya Itano             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Katsuhito Sakurai             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Fumihiro Inui             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation F-term (reference) 4M118 AA10 AB01 BA14 CA02 FA06                       FA33 FA50                 5C024 CX27 CX35 EX25 GY31 GZ42

Claims (8)

[Claims] 1. A photoelectric conversion means comprising a plurality of pixels for generating charges according to an amount of incident light; first and second reading means for reading charges from the photoelectric conversion means for each row; An input unit for inputting a control signal for controlling the first and second reading units; and a signal line for transmitting the control signal from the input unit to the first and second reading units, The signal line is wired such that the ratio of the distance from the input unit to the first read unit and the distance from the input unit to the second read unit is smaller than a predetermined ratio. A characteristic imaging device. 2. The image pickup apparatus according to claim 1, wherein the signal line is branched and wired at an intermediate point between the first and second reading means. 3. The image pickup device according to claim 2, wherein the signal line is further branched and wired at an intermediate point in the longitudinal direction of each of the first and second reading means. 4. The signal line is characterized in that a distance from the input means to the first reading means and a distance from the input means to the second reading means are substantially the same. The imaging device according to any one of 1 to 3. 5. The image pickup apparatus according to claim 4, wherein the signal line is branched and wired at a substantially central point of the first and second reading means. 6. The image pickup device according to claim 5, wherein the signal line is further branched and wired at a substantially central point in the length direction of each of the first and second reading means. 7. The first and second read means are shift registers, and among the transfer stages of the shift registers,
7. The image pickup apparatus according to claim 3, wherein substantially the same number of transfer stages are connected to the branched signal lines. 8. The image pickup device according to claim 1, wherein the image pickup device is a CMOS type image pickup device.