JP2003258780A - Data receiving apparatus, data communication system, data receiving method, and data communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately transfer data even within an LSI to be operated in an extremely high-speed clock frequency. <P>SOLUTION: Within the data receiving side block of the LSI, three flip-flops (F/F) 13-15 to be driven by three clocks deviating their phases just for 1/3 cycle in the same frequency and a clock selecting mechanism 16 are located and when a synchronizing signal is transmitted from a data transmitting side block, the three F/F respectively sample the synchronizing signal with their own clocks. Then, the clock selecting mechanism 16 selects a clock deviating its phase just for 1/3 cycle from the clock of the F/F first sampling the synchronizing signal as a reception clock signal, and the selected reception clock signal is supplied to a buffer 17. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer technique, for example, a data transfer technique inside an LSI which operates at a high clock frequency.

[0002]

2. Description of the Related Art Due to the progress of LSI process technology, LS
The I circuit structure is becoming finer, highly integrated, and operating frequency is becoming faster. It is considered that this technological trend will continue for the next several years, and in the near future, the operating frequency inside the LSI will reach a region exceeding 10 GHz. As miniaturization of LSI progresses, the size of the basic circuit becomes smaller and the area of the entire circuit becomes smaller accordingly, which reduces the signal delay and enables higher clock frequencies. On the other hand, the signal line width becomes thinner. The signal delay on the line tends not to be improved so much due to the increase of the impedance and the influence of the load capacitance component.

[0003]

L at very high frequencies
When operating the SI, a completely synchronous circuit structure is possible in an LSI having a finite size in which clock skew, variation in delay time within the LSI, and the like are managed by using the same clock when viewed locally. However, it is expected that it will be very difficult to use the same frequency clock in all areas in perfect synchronization due to the influence of signal delay on the line. For example, in data transfer between modules existing at positions distant from each other in the layout inside the LSI, the arrival time at the receiving side may exceed one clock cycle due to the delay of the wiring between the modules.

In actual LSI design, automatic layout and wiring are used partially or wholly for layout design, and it is impossible to completely manage the delay for all signal lines. Also, it is not realistic to manage all the signal delays by manually wiring all of them.

That is, at the time of high-speed transfer, the clock skew in the LSI is adjusted, and the delay time due to data transfer is accurately estimated in consideration of variations and noise, and a flip-flop (hereinafter referred to as F / F) on the receiving side Accurate transfer cannot be performed without adjustment so as to satisfy the setup time and hold time, but there is a problem that it is difficult to estimate them in the LSI.

Therefore, an object of the present invention is to perform accurate data transfer even in an LSI operating at a very high clock frequency.

[0007]

A data receiving apparatus according to the present invention is a data receiving apparatus which is connected to a data transmitting apparatus and receives transmission data transmitted from the data transmitting apparatus. Having N clock signals displaced by 1 / N (N is an integer of 3 or more) cycles, selecting a specific clock signal from among the N clock signals as a reception clock signal, and selecting the reception signal The transmission data is received using a clock signal.

The data receiving device is connected to a data transmitting device for transmitting a predetermined synchronization signal before transmitting the transmission data, and the N clocks are transmitted when the synchronization signal is transmitted from the data transmitting device. The synchronization signal is received using each of the signals, and a specific clock signal is selected as the reception clock signal from the N clock signals based on the reception state of the synchronization signal.

Each of the data receiving devices is associated with one of the N clock signals, and when the synchronizing signal is transmitted from the data transmitting device, the data receiving device provides the clock signal associated with itself. Using N data receiving units that receive the synchronization signal and the data receiving unit that first started receiving the synchronization signal from the N data receiving units, and detect the data receiving unit And a clock signal selecting unit for selecting, as the received clock signal, a clock signal whose phase is delayed by 1 / N cycle from the assigned clock signal.

The data receiving device is characterized in that the receiving clock is selected from three clock signals having the same frequency and a phase displaced by 1/3 cycle.

The data receiving device is characterized in that a dummy bit, which is a non-significant signal, is received from the data transmitting device during a certain period from the reception of the synchronization signal to the reception of the transmission data.

[0012] The data receiving device determines whether or not the transmission data can be received, and when the result of the reception availability determination indicates that the transmission data can be received, the transmission data is received. Is transmitted to the data transmitting device, and if the reception of the transmission data is impossible as a result of the reception permission judgment, the reception of the transmission data is not possible. It is characterized in that a reception impossibility notice for notifying that it is impossible is transmitted to the data transmission device.

The data receiving device has a buffer for accumulating transmission data, and determines whether or not the data can be received based on the accumulation status of the buffer.

The data receiving device is connected to a data transmitting device for transmitting a data frame including the transmission data and a predetermined synchronizing signal and having a predetermined frame structure,
When the data frame is transmitted from the data transmission device, the synchronization signal included in the data frame is received using each of the N clock signals,
A specific clock signal is selected as the reception clock signal from the N clock signals based on the reception state of the synchronization signal, and the transmission data included in the data frame is received using the selected reception clock. It is characterized by doing.

The data receiving device receives from the data transmitting device a data frame including the synchronization signal, dummy bits, start bits, command bits and the transmission data.

When the data receiving device receives the command bit included in the data frame, the data receiving device analyzes the received command bit to determine the structure of the transmission data.

The data receiving device may start receiving the transmission data after receiving the start bit included in the data frame.

The data receiving device receives a command bit having a predetermined number of received bits, and after receiving data for the number of received bits indicated by the command bit,
Data reception is terminated and the selection of the reception clock signal is canceled.

The data receiving device is an LSI circuit.

A data communication system according to the present invention is a data communication system having a data transmitting device for transmitting transmission data and a data receiving device for receiving the transmission data from the data transmitting device. Transmits a predetermined synchronization signal prior to the transmission of the transmission data, and the data receiving device has the same frequency and a phase of 1 /
When the synchronization signal is transmitted from the data transmission device, the clock signal has N clock signals which are displaced by N (N is an integer of 3 or more) cycles, and the N clock signals are respectively used for the synchronization signal. When a synchronization signal is received, a specific clock signal is selected as a reception clock signal from the N clock signals based on the reception state of the synchronization signal, and the transmission data is transmitted from the data transmission device, The transmission data is received by using the selected reception clock signal.

The data transmitting device is characterized in that it transmits a dummy bit, which is a non-significant signal, to the data receiving device during a certain period after the transmission of the synchronization signal and before the transmission of the transmission data.

The data receiving device determines whether or not the transmission data is receivable, and if the transmission data is receivable as a result of the reception propriety determination, the transmission data Sending a receivable notification notifying that reception is possible to the data transmission device,
As a result of the reception propriety determination, if the transmission data cannot be received, a reception prohibition notification for notifying that the transmission data cannot be received is transmitted to the data transmission device, The transmitting device transmits the transmission data to the data receiving device when receiving the receivable notification from the data receiving device, and transmits the transmitting data to the data receiving device when the receivable notification is received from the data receiving device. The feature is that transmission of data is stopped.

The data transmission device transmits a data frame including the transmission data and a predetermined synchronization signal and having a predetermined frame structure, and the data reception device receives the data frame from the data transmission device. In this case, each of the N clock signals is used to receive the synchronization signal included in the data frame, and a specific clock signal is selected from the N clock signals based on the reception state of the synchronization signal. Is selected as the reception clock signal, and the transmission data included in the data frame is received using the selected reception clock.

The data transmitting device and the data receiving device are each an LSI circuit.

A data receiving method according to the present invention is a data receiving method for receiving transmission data transmitted from a data transmitting device, wherein the phase is displaced by 1 / N (N is an integer of 3 or more) cycles at the same frequency. And selecting a specific clock signal from the N clock signals as a reception clock signal, and receiving the transmission data using the selected reception clock signal. And

A data communication method according to the present invention is a data communication method including a data transmission process for transmitting transmission data and a data reception process for receiving the transmission data from the data transmission process. The process transmits a predetermined synchronization signal prior to the transmission of the transmission data,
In the data reception processing, the phase is 1 / N (N
Has N clock signals that are displaced by an integer of 3 or more cycles, and when the synchronization signal is transmitted by the data transmission process, the synchronization signal is transmitted using each of the N clock signals. Receiving, selecting a specific clock signal from the N clock signals as a reception clock signal based on the reception state of the synchronization signal, and selecting the transmission data when the transmission data is transmitted by the data transmission processing. It is characterized in that the transmission data is received using a reception clock signal.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Next, a first embodiment of the present invention will be described with reference to the drawings. Figure 1
FIG. 3 is a block diagram showing the concept of an intra-LSI block data transfer system according to the first embodiment of the present invention. In FIG. 1, a transmission side block 10 is used as an LSI block.
0 and the receiving side block 101 are connected by a transmission path, and the receiving side is provided with a clock selection mechanism section and a buffer. An optimum reception clock is selected using this clock selection mechanism section, and serial data is received by the buffer. The transmitting block 100 corresponds to a data transmitting device, and the receiving block 101 corresponds to a data receiving device.

Next, the configurations of the clock selection mechanism section and the buffer will be described with reference to FIG. The clock selection mechanism unit includes three F / Fs 13 to 15 and a clock selection mechanism 16 for clock selection. And these 3
Three F / F are three clocks CLKA and CLK respectively
It is driven by B and CLKC. This CLKA, CLK
B and CLKC are supplied from a clock generation circuit (not shown). Also, CLKA, CLKB, CLKC
Have the same frequency, and their phase relationships are delayed by 1/3 cycle from CLKB to CLKA and from CLKC to CLKB as shown in FIG. Further, CLKA control line 10, CLKB control line 11, CLK
The clock is gated by the C control line 12. Further, at first, no clock is supplied from the clock selection mechanism 16 to the buffer 17. In addition, F / F13
15 to 15 correspond to the data receiving unit, and the clock selection mechanism 16
Corresponds to the clock signal selection unit.

First, the synchronizing signal sent from the transmitting side block is once sampled by the three F / Fs in the clock selecting mechanism section. Assuming that the F / F that has sampled the data first is driven by CLKA, the clock selection mechanism uses the CLKB control line 11 and CLKC.
The control line 12 is activated, CLKB and CLKC are stopped from being supplied to the F / F, and the other two F / Fs driven by them stop sampling the synchronization signal.

On the other hand, the clock selection mechanism 16 drives the C / F for driving the F / F which samples the synchronization signal at the beginning.
CL that is not LKA but 1/3 cycle later than that
KB is selected as a reception clock signal for sampling the reception side block and is supplied to the buffer 17. The reason for doing the above is that the CLKA that drives the F / F that first samples the synchronization signal is
This is because if the setup time of the buffer is barely satisfied, the setup time may not be satisfied even with a slight change in the condition of the transmission line, and the possibility that accurate data transfer may not be achieved is eliminated. Although not shown in the figure, conversely, it is possible that the hold time is very short. Therefore, for the same reason, the CLKA that drives the first sampled F / F is not selected, and a more reliable CLKB is selected. Select. Then, the receiving block uses the selected CLKB to receive the actual data transmitted from the transmitting block after the synchronization signal.

In the above description, the supply of CLKB and CLKC to the F / F driven by CLKB and CLKC is stopped, but without doing this, sampling is performed by CLKB and CLKC in the selection mechanism. A logic that does not use the generated synchronization signal may be adopted. That is, the logic may be such that the sampled synchronization signal is not used for clock selection.

As described above, it becomes possible to realize high-speed transfer of serial data in transfer between blocks in an LSI even at a high-speed frequency.

In the above description, the case of using three clock signals having the same frequency and the phase being displaced by 1/3 cycle has been described, but the present invention is not limited to this, and the same frequency and the phase are used. If N clock signals that are displaced by 1 / N cycle are used, N may be 3 or more.

As described above, according to the first embodiment, the LS
In data transfer between a certain data transmission side block and another data reception side block in I, one data line is provided between the transmission side block and the reception side block, and three types of clocks and data reception are performed at the reception side block. And a means for selecting an optimum clock, the serial data sent from the transmitting block is sampled by the receiving block using one of three clocks having different phases. Therefore, the receiving block can perform accurate transfer because it can perform sampling using a highly reliable clock even when operating at a high frequency.

Embodiment 2. In the second embodiment of the present invention, the transmitting block sends a non-significant signal as a dummy bit in order to make time for clock selection for a certain period after sending the synchronization signal, and thereafter, It is equipped with a mechanism for preventing data loss by sending actual data.

That is, since there is a time required for the clock selection in the clock selection mechanism 16, if the real data is sent without a gap after the sync signal is sent, the sampling of several bits from the head of the real data fails. .
Therefore, while the clock is being selected, the dummy bit is transmitted from the transmitting block to prevent data sampling failure.

Embodiment 3. As shown in FIG. 6, the third embodiment of the present invention further includes a status signal (receivable notification, unreceivable notification) indicating whether or not data can be received in the transfer method in the first embodiment.

As shown in FIG. 7, the status signal is output from the buffer monitoring mechanism 18 in the receiving side block to the transmitting side block. The receiving side block consumes the received data or the like to empty the buffer. When the buffer becomes available without consumption, it notifies the transmitting block that the receiving block can receive. As an example of changing the state of the above state signal, when the data transfer from the transmission side block to the reception side block is completed, “reception is not possible (busy)”, when the reception side block consumes the reception data and the buffer becomes empty. It may be "ready".

Fourth Embodiment Further, in the fourth embodiment, the transmission side block is provided with a mechanism for monitoring the above status signal, and if the transmission side block has a transfer request and the above status signal is “ready”, data transfer is performed. And do not start data transfer if reception is not possible.

Embodiment 5. In the fifth embodiment of the present invention, the transmission side block transmits a synchronization signal for selecting a reception clock, a dummy bit, a data body, etc. as transmission data in the form of one frame data. That is, as an example, as shown in FIG. 5, a synchronization bit 41, a dummy bit 42, a start bit 43, and a command bit 4
4, a data frame having a frame structure composed of fields of data bits 45 is transmitted.

Sixth Embodiment In the sixth embodiment of the present invention, in the transmission side block, in the transmission data having the frame structure as shown in FIG. 5, the configuration of the data bit 45 is uniquely determined by the value of the command bit 44 of the frame. Data having the structure

That is, the data sent from the transmitting side block to the receiving side block is, for example, in FIG. 5, when the command bit 44 indicates read (data read), the data bit 45 reads out the target address, write (data write). ) Data bit 45
Has a frame structure composed of a write destination address and write data, and the command bit 44 stores bit number information of the data. Further, the receiving block has a mechanism for determining the value of the command bit and the configuration of the data bit. The present description is an example, and the frame structure can be freely defined.

Embodiment 7. In the seventh embodiment of the present invention, the receiving block shown in the fifth embodiment is provided with a mechanism for detecting the start bit which is the first significant signal after detecting the synchronization bit, and the start bit is added. Upon detection, start receiving data to the buffer.

Embodiment 8. In the eighth embodiment of the present invention, the receiving block shown in the sixth embodiment is sampled with data of a constant bit length determined based on the content of the command bit, and then the data receiving operation is completed. A mechanism for canceling the selection of the reception clock signal selected upon completion of this is added, and the reception clock signal is selected again at the time of subsequent data reception.

That is, as shown in FIG. 8, the command bit storage unit 19 and the buffer monitoring mechanism 18 are provided in the receiving side block.
In addition, the buffer monitoring mechanism 18 prevents the clock for driving the buffer from being supplied to the buffer at the time when the buffer stores data for the number of bits defined by the command bit, and is selected by the clock selection mechanism 16. A signal for deselecting the received clock signal is sent so that the clock can be selected again by subsequent data.

In the above first to eighth embodiments, the data receiving device and the data communication system according to the present invention have been described, but the data receiving method and the data communication method according to the present invention can be realized by the same processing procedure. Is.

Here, the characteristics of the data transfer methods shown in the first to eighth embodiments will be described again.

The data transfer method shown in the first embodiment is
In data transfer using a single line, it has three types of clock signals having the same frequency but different phases, and selects the optimum receiving clock from the above three types based on the reception state of the synchronization signal sent from the transmitting side. It is characterized by

The data transfer method shown in the second embodiment is
The transmitting side sends a synchronization signal, then sends a dummy bit (insignificant signal) for a certain period of time, and then sends actual data.

The data transfer method shown in the third embodiment is
It is characterized in that the receiving side has means for notifying the transmitting side of the status information indicating whether the data can be received or cannot be received, through a line different from the single line.

The data transfer method shown in the fourth embodiment is
When the receiving side completes the reception of all the data sent from the transmitting side, it sets the status signal to "unreceivable", and when the receiving side consumes the data and the resources related to the data reception are released. The status signal is set to "receivable".

The data transfer system shown in the fourth embodiment is
If there is a data transfer request and the status signal is "receivable", the transmitting side starts data transfer, and if "receivable", it does not start data transfer.

The data transfer method shown in the fifth embodiment is
It is characterized in that the transmission data has a frame structure including fields of a synchronization bit, a dummy bit, a start bit, a command bit, and a data bit.

The data transfer method shown in the sixth embodiment is
The configuration of the data bit part of the transmission frame is uniquely determined by the command bit part of the same frame.

The data transfer system shown in the seventh embodiment is
It is characterized in that the receiving side starts data reception when the first significant signal (start bit) is detected after detecting the synchronization signal.

The data transfer system shown in the eighth embodiment is
After receiving the data, the receiving side fetches the data having the bit length based on the content of the command bit, completes the data receiving operation, and cancels the setting of the optimum receiving clock.

[0057]

As described above, according to the present invention, an optimum clock signal is selected from a plurality of clock signals which are out of phase at the same frequency, based on the reception state of the synchronization signal, and the selected reception clock is selected. Since the transmission data is received using the signal, there is an effect that the data can be accurately transmitted even in an LSI that operates at a high frequency for which perfect synchronous design is difficult.

Further, according to the present invention, since the data received during the fixed period after the reception of the synchronization signal is the dummy bit, there is an effect that the data loss during the selection of the reception clock signal can be prevented.

Further, according to the present invention, since the receivable notification and the unreceivable notification are transmitted as a result of the reception propriety determination, it is possible to prevent the transmission data from being transmitted even in the unreceivable state. can do.

Further, according to the invention, even when a data frame having a frame structure is transmitted, the optimum clock signal can be selected based on the reception state of the synchronization signal included in the data frame, and the data frame can be selected. There is an effect that appropriate processing can be performed on various data included in.

[Brief description of drawings]

FIG. 1 is a block diagram showing a transmission side block and a reception side block.

FIG. 2 is a block diagram showing configurations of a clock selection mechanism section and a buffer.

FIG. 3 is a diagram showing the phase relationship of three clocks that are sampling clock selection candidates.

FIG. 4 is a diagram showing a setup time and a hold time in data sampling.

FIG. 5 is a diagram showing a frame structure of transmission data of a transmission side block.

FIG. 6 is a block diagram showing a transmission side block and a reception side block.

FIG. 7 is a block diagram showing a configuration of a clock selection mechanism unit, a buffer, and the like.

FIG. 8 is a block diagram showing a configuration of a clock selection mechanism unit, a buffer, and the like.

[Explanation of symbols]

1 Clock selection mechanism section and buffer, 10 CLKA
Control line, 11 CLKB control line, 12 CLKC control line, 13 flip-flop, 14 flip-flop, 15 flip-flop, 16 clock selection mechanism, 17 buffer, 18 buffer monitoring mechanism, 19
Command bit storage unit, 41 synchronization bits, 42 dummy bits, 43 start bits, 44 command bits, 45 data bits, 100 data transmitting side blocks, 101 data receiving side blocks.

Claims (20)

[Claims] 1. A data receiving device, which is connected to a data transmitting device and receives transmission data transmitted from the data transmitting device, wherein phases are 1 / N (N is an integer of 3 or more) cycles at the same frequency. With N clock signals being displaced, said N
A data receiving apparatus, characterized in that a specific clock signal is selected as a reception clock signal from the individual clock signals, and the transmission data is received using the selected reception clock signal. 2. The data receiving device is connected to a data transmitting device that transmits a predetermined synchronization signal before transmitting the transmission data, and the N number of the data receiving devices are connected when the synchronization signal is transmitted from the data transmitting device. Receiving the synchronization signal using each of the clock signals, and selecting a specific clock signal as the reception clock signal from the N clock signals based on the reception state of the synchronization signal. Item 1. The data receiving device according to item 1. 3. The data receiving device is associated with any one of the N clock signals, and when the synchronization signal is transmitted from the data transmitting device, a clock associated with itself is provided. A N data receiving unit that receives the synchronization signal using a signal, and a data receiving unit that first starts receiving the synchronization signal from the N data receiving units, and the detected data receiving unit is detected. The phase is 1 / N from the clock signal associated with
The data receiving apparatus according to claim 2, further comprising a clock signal selection unit that selects a clock signal delayed by a cycle as the reception clock signal. 4. The data receiving device according to claim 1, wherein the data receiving device selects the reception clock from three clock signals having the same frequency and a phase displaced by 1/3 cycle. Data receiving device. 5. The data receiving device receives a dummy bit, which is a non-significant signal, from the data transmitting device during a certain period after receiving the synchronization signal and before receiving the transmission data. 1. The data receiving device according to 1. 6. The data receiving device determines whether or not the transmission data can be received, and determines whether the transmission data can be received as a result of the reception permission / inhibition determination. A reception enable notification for notifying that the transmission data can be received is transmitted to the data transmission device, and as a result of the reception permission / inhibition determination, if the transmission data cannot be received, the transmission data The data reception device according to claim 1, wherein a reception prohibition notification for notifying that reception is impossible is transmitted to the data transmission device. 7. The data receiving apparatus according to claim 6, wherein the data receiving apparatus has a buffer for accumulating transmission data, and determines whether or not the data can be received based on the accumulation status of the buffer. 8. The data receiving device is connected to a data transmitting device for transmitting a data frame including the transmission data and a predetermined synchronization signal, and having a predetermined frame structure, wherein the data frame is transmitted from the data transmitting device. Receiving the synchronization signal contained in the data frame using each of the N clock signals when transmitted,
A specific clock signal is selected as the reception clock signal from the N clock signals based on the reception state of the synchronization signal, and the transmission data included in the data frame is received using the selected reception clock. The data receiving device according to claim 1, wherein 9. The data receiving device receives from the data transmitting device a data frame including the synchronization signal, dummy bits, start bits, command bits, and the transmission data. The data receiving device according to 1. 10. The data receiving device, when receiving the command bit included in the data frame, analyzes the received command bit to determine a configuration of the transmission data. Item 10. The data receiving device according to Item 9. 11. The data receiving apparatus according to claim 9, wherein the data receiving apparatus starts receiving the transmission data after receiving the start bit included in the data frame. 12. The data receiving device receives a command bit indicating a predetermined number of received bits, receives data of the number of received bits indicated by the command bit, and then ends data reception, 10. The data receiving device according to claim 9, wherein the selection of the reception clock signal is canceled. 13. The data receiving device according to claim 1, wherein the data receiving device is an LSI circuit. 14. A data communication system, comprising: a data transmission device for transmitting transmission data; and a data reception device for receiving the transmission data from the data transmission device, wherein the data transmission device transmits the transmission data. Prior to transmitting a predetermined synchronization signal, the data receiving device has N clock signals whose phases are displaced by 1 / N (N is an integer of 3 or more) cycles at the same frequency. When the synchronization signal is transmitted, the synchronization signal is received by using each of the N clock signals, and a specific clock signal is selected from the N clock signals based on the reception state of the synchronization signal. Is selected as a reception clock signal, and when the transmission data is transmitted from the data transmission device, the reception clock signal is selected using the selected reception clock signal. A data communication system characterized by receiving transmitted data. 15. The data transmitting apparatus transmits a dummy bit, which is a non-significant signal, to the data receiving apparatus during a certain period after transmitting the synchronization signal and before transmitting the transmission data. The data communication system according to claim 14. 16. The data receiving device determines whether or not the transmission data is receivable, and if the transmission data is receivable as a result of the reception propriety determination, the transmission is performed. A reception enable notification for notifying that data can be received is transmitted to the data transmission device, and if the transmission data cannot be received as a result of the reception availability determination, the reception of the transmission data is performed. Is transmitted to the data transmitting device, the data transmitting device, when receiving the receivable notification from the data receiving device, to the data receiving device 15. The transmission data is transmitted by transmitting the transmission data, and the transmission of the transmission data is stopped when the reception prohibition notification is received from the data receiving device. Data communication system. 17. The data transmitting apparatus transmits a data frame including the transmission data and a predetermined synchronization signal and having a predetermined frame structure, wherein the data receiving apparatus receives the data frame from the data transmitting apparatus. Receiving the synchronization signal contained in the data frame using each of the N clock signals when transmitted,
A specific clock signal is selected as the reception clock signal from the N clock signals based on the reception state of the synchronization signal, and the transmission data included in the data frame is received using the selected reception clock. The data communication system according to claim 14, wherein: 18. The data communication system according to claim 14, wherein each of the data transmitting device and the data receiving device is an LSI circuit. 19. A data reception method for receiving transmission data transmitted from a data transmission device, wherein N clocks whose phases are displaced by 1 / N (N is an integer of 3 or more) cycles at the same frequency. Has a signal, said N
A data receiving method, wherein a specific clock signal is selected as a reception clock signal from the individual clock signals, and the transmission data is received using the selected reception clock signal. 20. A data communication method, comprising: a data transmission process for transmitting transmission data; and a data reception process for receiving the transmission data from the data transmission process, wherein the data transmission process comprises: A predetermined synchronization signal is transmitted prior to transmission, and the data reception process has N clock signals whose phases are displaced by 1 / N (N is an integer of 3 or more) cycles at the same frequency. When the synchronization signal is transmitted by processing, the synchronization signal is received using each of the N clock signals, and a specific clock is selected from the N clock signals based on the reception state of the synchronization signal. When a signal is selected as a reception clock signal and the transmission data is transmitted by the data transmission processing, the reception clock signal is selected using the selected reception clock signal. A data communication method characterized by receiving transmitted data.