JP2003258626A - Programmable logic device, non-volatile memory and data reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To exactly reproduce the stored data in a ferroelectric capacitor used in a programmable logic device when the power is turned on, improve the reliability of the stored data in ferroelectric SRAM cells, composed of SRAM memory cells with the ferroelectric capacitors attached thereto, and quickly start logic operations after power is turned on. <P>SOLUTION: When the power is turned on, a configuration memory 23 is fed with an externally supplied power voltage Vdd with a delay, depending on the time constant according to the characteristics of a ferroelectric capacitor. The drop in the externally supplied power voltage Vdd is detected to fully apply the power voltage to ferroelectric SRAM cells, and then its power source is cut off. Information whether configuration information are already written or not are held in the ferroelectric SRAM cells. If not yet written or already written, the output of a logic block is forcibly disabled or enabled, respectively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic device using a ferroelectric capacitor, and more particularly to a programmable logic device that can be used as a programmable logic block manufactured on a single integrated circuit. The present invention also relates to a configuration of a non-volatile memory having a ferroelectric capacitor, which can be used in the programmable logic device and other IC cards and the like, and a method of reproducing stored data thereof.

[0002]

2. Description of the Related Art In a programmable logic device whose logic state is determined according to the data stored in an SRAM type memory cell, configuration information for prescribing the operation of this device is provided outside the device even after the power is turned off. A non-volatile memory such as a PROM or EPROM for holding is required. Therefore, there are drawbacks such as an increase in the number of devices, an increase in cost, and an increase in board area.

Therefore, a programmable logic device has been proposed in which a ferroelectric capacitor is added to an SRAM type memory cell and the dielectric polarization thereof is used to retain the configuration information even after the power is turned off (Patent No. 3121862). SRAM-type memory cell (hereinafter referred to as ferroelectric SRA) to which this ferroelectric capacitor is added.
A programmable logic device including M cells) is considered to be a particularly desirable technique because it can achieve higher speed than a device using a non-volatile memory such as a PROM.

By the way, normally, in a programmable logic device of a type in which configuration information is loaded from an external non-volatile memory, SRAM is turned on after power is turned on.
The output driver of the logic block is disabled until data based on the configuration information is written to the type memory cell. This means that no configuration information has been written, ie SRA
This is because if the data held in the M-type memory cell is not set, incorrect wiring may be connected.
If wirings that are erroneously connected are driven by different drivers to different logic states, the voltage of the wirings becomes unstable (wiring signal conflict), resulting in a large current consumption.

[0005]

However, in recent years,
Tamura et al. Have reported that ferroelectric capacitors have the property of dynamically fluctuating (T.Tamura et al., ISIF
digest, p. 1.2.2, 2001). Due to this property, it has been found that when a voltage that sharply increases when the power is turned on is applied to the ferroelectric SRAM cell, the data based on the dielectric polarization state of the ferroelectric capacitor may not be normally reproduced.

Further, when the power is cut off, the ferroelectric SRA is used.
In order to ensure the reliability of the information stored in the M cell, it is desirable to turn off the power supply after the power supply voltage is fully applied to the ferroelectric SRAM cell. However, the ferroelectric SR
If the power supply voltage is fully applied to the AM cell, a phenomenon called so-called imprint in which the hysteresis curve of the ferroelectric capacitor changes occurs, and it becomes difficult to rewrite the data of the ferroelectric capacitor.

Further, in the programmable logic device using the ferroelectric SRAM cell, once the configuration information is written, the information is accumulated even after the power is turned off, so that no wiring conflict occurs when the power is turned on. Therefore, it is not necessary to disable the output driver every time the power is turned on. Nevertheless, as in the past, disabling the output driver at power-on delays the start of logic operation after power-up.

The present invention has been made in view of the above problems, and it is possible to accurately reproduce the data stored in the ferroelectric capacitor when the power is turned on, and the ferroelectric SRA.
The reliability of the data stored in the M cell can be further increased,
Another object of the present invention is to provide a programmable logic device using a ferroelectric capacitor that can quickly start a logic operation after power is turned on. Another object of the present invention is to provide a non-volatile memory capable of accurately reproducing the data stored in the ferroelectric capacitor when the power is turned on, and a data reproducing method thereof.

[0009]

In order to achieve the above object, the present invention relates to a programmable logic device using a ferroelectric SRAM cell, in which a power supply voltage supplied from the outside when a power supply is turned on is applied to the ferroelectric material. A configuration in which a ferroelectric SRAM cell is used as an SRAM cell drive voltage with a time constant delayed according to the characteristics of the capacitor.
It is characterized in that it is supplied to a memory. According to this invention, when the power is turned on, the power supply voltage supplied from the outside is
SR delayed with a time constant according to the characteristics of the ferroelectric capacitor
It is supplied to the configuration memory as an AM cell drive voltage.

Further, according to the present invention, when the power supply is cut off, before the SRAM cell drive voltage supplied to the configuration memory actually drops, the drop of the power supply voltage supplied from the outside is detected, and the ferroelectric SR in body SRAM cell
The power supply is shut off after the AM cell drive voltage is fully applied. According to the present invention, when the drop of the power supply voltage supplied from the outside is detected, the ferroelectric SRAM
The power is shut off after the SRAM cell driving voltage is fully applied to the cell.

Further, according to the present invention, one of the ferroelectric SRAM cells is made to hold the information as to whether or not the configuration information has been written, and the output of the logic block is forcibly forced before the writing. , While enabling the output of the logic block if it has been written. According to the present invention, the output of the logic block is forcibly disabled before writing the configuration information, and after writing the configuration information,
The output of the logic block is enabled.

Further, according to the present invention, a pair of inverters forming a ferroelectric SRAM cell has a structure in which a resistance element is connected between a drain terminal of an n-channel transistor and a power supply line. According to the present invention, even if the resistance value of the resistance element of one inverter differs from the resistance value of the resistance element of the other inverter by about 20%, the potential change at the output node of each inverter at power-on is small. Therefore, the accumulated data of the ferroelectric capacitor is accurately reproduced.

Further, according to the present invention, the pair of inverters forming the ferroelectric SRAM cell is composed of an n-channel transistor and a p-channel transistor having a size equal to or smaller than the size of the n-channel transistor. According to the present invention, it takes more time for the potential of the output node of each inverter to rise when the power is turned on, and the ferroelectric capacitor responds sufficiently. Therefore, the accumulated data of the ferroelectric capacitor is accurately reproduced. It

Further, according to the present invention, when the ferroelectric SRAM cell is powered on, a pair of bit signal lines are precharged, and then a switch is connected between each bit signal line and the output node of the pair of inverters. Turn on for a short time. According to this invention, the potential of the output node of each inverter rises when the power is turned on, and the operating points of both ferroelectric capacitors are changed in the direction in which the difference in equivalent capacitance between the pair of ferroelectric capacitors increases. Accumulated data of the ferroelectric capacitor is accurately reproduced.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a main part of a programmable logic device according to Embodiment 1 of the present invention. As shown in FIG. 1, the programmable logic device according to the first exemplary embodiment includes a power supply voltage detection / supply circuit 21, a ferroelectric SRAM cell control circuit 22, and a memory that stores configuration information (hereinafter referred to as a configuration memory. And)
Equipped with 23. Configuration memory 2
3 is mainly composed of a ferroelectric SRAM cell. The programmable logic device also includes a look-up table (not shown), programmable wiring (not shown), and a programmable input / output circuit (programmable I / O) not shown.

A power supply voltage Vdd is supplied to the power supply voltage detection / supply circuit 21 from an external power supply terminal 24. A smoothing capacitor 26 is connected to the power supply line 25 of the power supply voltage Vdd. The power supply voltage detection / supply circuit 21 is a ferroelectric SR
The SRAM cell drive voltage PWR is supplied to the AM cell control circuit 22. The ferroelectric SRAM cell control circuit 22 supplies a rising-controlled power supply voltage to the configuration memory 23 when the power is turned on.

Further, the power supply voltage detection / supply circuit 21 is provided with a power supply voltage detection terminal VDET. The power supply voltage Vdd is directly supplied to the power supply voltage detection terminal VDET from the external power supply terminal 24 without passing through the smoothing capacitor 26. The power supply voltage detection / supply circuit 21 detects the power supply voltage Vdd and supplies a voltage detection signal PDET to the ferroelectric SRAM cell control circuit 22. The ferroelectric SRAM cell control circuit 22 supplies various control signals to the configuration memory 23 when the power is cut off.

FIG. 2 is a block diagram showing an example of the configuration memory 23. For example, as shown in FIG. 2, the configuration memory 23 includes a shift register 31 for transferring the configuration information and a write for writing the data supplied from the shift register 31 into the ferroelectric SRAM cell 33. It is composed of a circuit 32, a ferroelectric SRAM cell 33, and a sense amplifier / output buffer 34 including precharge.

The output of the ferroelectric SRAM cell 33 is supplied to a look-up table (not shown) via the sense amplifier / output buffer 34. In order to control this configuration memory 23, the ferroelectric SRA
A word line control signal WL and a plate line control signal PL are supplied to the M cell 33, and a write control signal WE is supplied to the write circuit 32 from the ferroelectric SRAM cell control circuit 22.

FIG. 3 is a circuit diagram showing an example of a ferroelectric SRAM cell. For example, as shown in FIG. 3, a ferroelectric SRAM cell has two p-type inverters forming a pair of inverters.
Channel transistors 41, 42 and two n-channel transistors 43, 44, two access transistors 45, 46 consisting of n-channel transistors,
It is composed of two ferroelectric capacitors 47 and 48.

The first inverter has a structure in which the drain terminal of the first p-channel transistor 41 and the drain terminal of the first n-channel transistor 43 are commonly connected. Similarly, the second inverter has a configuration in which the drain terminal of the second p-channel transistor 42 and the drain terminal of the second n-channel transistor 44 are commonly connected. Then, the first inverter and the second inverter are connected to each other so that their outputs become the inputs of the counterpart, thereby forming an SRAM type memory cell.

The source terminals of the first and second p-channel transistors 41 and 42 are connected to the SRAM cell drive voltage P.
It is connected to the SRAM cell power supply line 51 to which WR is applied. First and second n-channel transistor 4
Each of the source terminals 3, 44 is grounded. The first access transistor 45 has a node (storage node S1) which is an output terminal of the first inverter,
It is connected to the bit signal line 52 to which the bit line control signal BL is supplied. The second access transistor 46 has a node serving as an output terminal of the second inverter (referred to as a storage node S2) and a bit line control signal B.
It is connected to the bit signal line 53 to which the inverted signal XBL of L is supplied.

The gate terminals of the first and second access transistors 45 and 46 are connected to the signal line 54 to which the word line control signal WL is supplied. First ferroelectric capacitor 47 and second ferroelectric capacitor 48
Are each storage nodes S1 and S2,
It is connected to the signal line 55 to which the plate line control signal PL is supplied.

Here, the access transistors 45 and 4
Reference numeral 6 is used to take out the information stored in the SRAM type memory cell to the outside and take in write data. If the information to be extracted is only the 1-bit non-inverted information, the second access transistor 46
May be omitted.

The plate line control signal PL is used to control the writing to the memory cell and to prevent the characteristics of the ferroelectric substance from being deteriorated by applying a high voltage to the memory cell in the data holding state. This is a control signal. The ferroelectric capacitors 47 and 48 are made of a ferroelectric material mainly composed of PZT (lead zirconate titanate) or a ferroelectric material having a bismuth layered perovskite structure such as SBT (bismuth strontium tantalate). Composed.

FIG. 4 is a circuit diagram showing an example of a power supply circuit which constitutes the power supply voltage detection / supply circuit 21. For example, as shown in FIG. 4, a CR circuit including a capacitor 63 and a resistance element 64 is connected between the non-inverting input terminal of the operational amplifier 61 and the terminal 62 to which the power supply voltage Vdd is applied. Therefore, the SRAM cell drive voltage PWR output from the operational amplifier 61 slowly increases from the rise of the power supply. The operational amplifier 61 is composed of a circuit capable of driving up to a full rail.

The output terminal of the operational amplifier 61 and SR
A load capacitance 66 is connected between the terminal 65 that outputs the AM cell drive voltage PWR. The output of the operational amplifier 61 is fed back to the inverting input terminal of the operational amplifier 61. The circuit shown in FIG. 4 is a circuit for controlling the power supply with a time constant of 100 nsec, and the resistance value of the resistance element 64 and the capacitance of the capacitor 63 are 10 kΩ and 10 respectively.
pF. The start-up time constant depends on the characteristics of the ferroelectric capacitor and is appropriately selected according to the ferroelectric material. The time constant of 100 nsec is a typical value when PZT is used as the ferroelectric material.

FIG. 5 is a circuit diagram showing an example of the power supply voltage detection circuit constituting the power supply voltage detection / supply circuit 21. For example, as shown in FIG. 5, 3.0V detectors 71 and 2.7.
The V detection unit 72 is provided, and the power supply voltage detection terminal VD
When the voltage applied to ET becomes 3.0V, a relatively high potential high is output as the voltage detection signal PDET, and once the voltage rises, the voltage detection signal PDET goes high until the voltage becomes 2.7V or less. It has a hysteresis characteristic of keeping at. This is to allow a margin for the momentary drop of the power supply due to the increase of the load.

The 3.0V detecting portion 71 is obtained by resistance-dividing the power supply voltage Vdd by the resistance element 73 having the resistance value r1 and the resistance element 74 having the resistance value (1.7 × r1) which is 1.7 times the resistance value. Voltage (1.7 × Vdd / (1 + 1.7)) and 1.1 output from the bandgap reference circuit 75.
The first comparator 76 compares the V reference voltage Vref. The output of the first comparator 76 is high until the power supply voltage Vdd reaches from zero to 3.0 V, but the power supply voltage Vdd
When dd becomes 3.0 V, the output of the first comparator 76 switches to low, which has a relatively low potential.

Similarly, the 2.7V detector 72 has a resistance value r
1 resistance element 77 and a resistance value 1.5 times that (1.5 × r
A voltage (1.5 × Vdd / (1 + 1.5)) obtained by resistance-dividing the power supply voltage Vdd by the resistance element 78 of 1).
And the reference voltage Vref of 1.1V output from the bandgap reference circuit 79, to the second comparator 80.
Compare by. When the power supply voltage Vdd is 2.7 V or higher, the output of the second comparator 80 is high, but when the power supply voltage Vdd becomes lower than 2.7 V, the output of the second comparator 80 switches to low. Here, by adopting the bandgap reference circuits 75 and 79, it is possible to obtain a stable voltage in which the characteristic variation is extremely small with respect to the power source variation and the temperature variation.

The output of the first comparator 76 and the output of the second comparator 80 are input to the first NAND gate 81 and the second NAND gate 82, respectively. Then, the first NAND gate 81 and the second NAND gate 8
The outputs of 2 are the inputs of the other side of each other.
The terminal 83 that outputs the voltage detection signal PDET has a first N
The output of the AND gate 81 is supplied.

FIG. 6 is a diagram showing an example of the look-up table. For example, as shown in FIG.
The up table is composed of a plurality of latches 91 and multiplexers 92, and the number thereof is not particularly limited, but for example, 16 ferroelectric SRAMs based on 4-bit inputs (A, B, C, D). The cell output is selected. By changing the data stored in the ferroelectric SRAM cell, the look-up table can be changed to AN.
D gate, NAND gate, AND gate with inverted input, OR gate, NOR gate, exclusive OR gate,
It comprises an AND-OR gate, a multiplexer, a latch or a flip-flop.

FIG. 7 is a schematic diagram for explaining the programmable wiring. As shown in FIG. 7, the pass transistor 101 is provided in the middle of the wiring, and the source / drain terminal of the pass transistor 101 is connected to the connection terminals 102 and 102 with the wiring. Pass transistor 1
The output of the ferroelectric SRAM cell 103 (strictly speaking, the output of the output buffer) is supplied to the gate terminal of 01. The pass transistor 101 is turned on / off according to the output potential level of the ferroelectric SRAM cell 103, thereby controlling the wiring connection.

Before describing the configuration of the programmable wiring in the first embodiment, the configuration of a general programmable wiring will be described. FIG. 14 is a diagram for explaining the configuration of a general programmable wiring. Figure 1
In the example shown in FIG. 4, the data written in the memory cell is written before the data is written in the ferroelectric SRAM cell or immediately after the power supply of the SRAM type memory cell to which the ferroelectric capacitor is not added is turned on. Is in an indeterminate state. Therefore, for example, among the output buffers 1, 2, 3, 4 the first output buffer 1 and the third output buffer 3 simultaneously pass transistors 5, 6, 7,
There is a possibility that the corresponding transistors 5 and 7 of 8 will be turned on.

Also, since the look-up table output is similarly indeterminate, output 1 from the look-up table can be high and output 3 from the look-up table can be low. is there. As a result, a high output and a low output compete with each other on the lower wiring track 9, the potential of this wiring is maintained at an intermediate potential, and a large current flows. In order to prevent this, the conventional programmable logic device has a configuration in which the output from the look-up table is disabled until the writing of the configuration information is completed after the device power is supplied.

However, in the programmable logic device using the ferroelectric SRAM cell as in the first embodiment, since the configuration information only needs to be written once, it is necessary to perform the configuration each time the power is turned on. There is no. Therefore, the first embodiment has the following configuration.

FIG. 8 is a diagram for explaining the configuration of the programmable wiring in the first embodiment. As shown in FIG. 8, information as to whether or not the configuration information has been written is held in the fifth ferroelectric SRAM cell,
The held information is output via the output buffer 119 corresponding to the fifth ferroelectric SRAM cell. The output information is used as the first to fourth AND gates 121, 122, 123,
124 and inputs to each AND gate 121,
122, 123, and 124, each of the ferroelectric SRA
Output buffers 111, 112, 11 corresponding to M cells
Input the output information of 3,114.

The AND gates 121, 122,
ON / OFF of each pass transistor 115, 116, 117, 118 is controlled based on the output of 123, 124, and the output from the look-up table is supplied to the wiring track. By doing so, before writing the configuration information, the output of the logic block in the programmable logic device is forcibly disabled so that the output of the programmable logic device does not cause a conflict. On the other hand, after the configuration is written, it enables the output of the logic block in the programmable logic device.

The memory holding the information as to whether or not the configuration information has been written is the ferroelectric S.
Not limited to the RAM cell, a normal 2T2C type ferroelectric memory cell or a 1T1C type ferroelectric memory cell may be used. Although the configuration of the programmable I / O is not particularly illustrated, the I / O is based on the output of the ferroelectric SRAM cell.
The O port input / output is selected.

FIG. 9 shows a ferroelectric SRA having the structure shown in FIG.
It is a chart showing the state of each control signal during the basic operation of the M cell. When writing data to the ferroelectric SRAM cell,
The SRAM cell section power is turned on. Both the write control signal WE and the word line control signal WL become high. The plate line control signal PL switches from high to low.

When reading data, the SRAM cell part power supply is turned on. The write control signal WE becomes low and the word line control signal WL becomes high. The plate line control signal PL is half the power supply voltage Vdd, that is, V
It becomes dd / 2. During a normal logic operation of the programmable logic device, that is, at this time, the ferroelectric SRAM cell is in a state of holding data, and the SRAM cell power supply is turned on. Both the write control signal WE and the word line control signal WL become low, and the plate line control signal PL becomes Vdd / 2.

As described above, the plate line control signal PL changes to Vdd / 2 during the data read and the normal logic operation.
The reason is that the imprint phenomenon described above does not occur. As a circuit for generating a potential of Vdd / 2, a circuit conventionally used in a DRAM or the like can be used. Alternatively, it may be configured to apply a potential of Vdd / 2 from the outside. The operation of other control signals is basically the same as that of the SRAM.

FIG. 10 is a diagram showing an example of a control sequence when the power source of the ferroelectric SRAM cell is turned on. Figure 10
As shown in, each control signal is first set. that time,
As shown in FIG. 11, which shows the state of each control signal before the power supply is turned on, the SRAM cell power supply is in the off state. It is safest to set the write control signal WE, the word line control signal WL, and the plate line control signal PL to low.

Continuing, as shown in FIG. 10, when the clock frequency is 40 MHz, 4 clocks, that is, 10 clocks.
The power supply voltage is supplied in 0 nsec. After the power is turned on, the configuration memory is read. Thereby, look-up table, programmable wiring and programmable I / O
Are set to a predetermined logical operation. Then, the reset state of the device is released, and normal logic operation is started. The clock frequency and the number of cycles required to supply the power supply voltage are variously selected according to the material of the ferroelectric capacitor.

FIG. 12 is a diagram showing an example of a control sequence when the power is cut off. As shown in FIG. 12, when the power-off is detected, the entire configuration memory is written. After that, it enters a cutoff waiting state.
As described above, when the power supply voltage Vdd supplied to the power supply voltage detection terminal VDET becomes lower than, for example, 2.7 V, the cutoff of the power supply is detected.

When the supply of the power supply voltage Vdd from the outside is cut off, the potential of the normal power supply terminal, that is, the power supply line 25 to which the smoothing capacitor 26 is connected in FIG. 1 gradually drops, but the smoothing capacitor 26 is connected. The potential of the non-source voltage detection terminal VDET sharply drops. Therefore, by monitoring the potential change of the power supply voltage detection terminal VDET, it is possible to detect the interruption of the power supply before the power supply voltage supplied to the ferroelectric SRAM cell actually drops. For example, when the smoothing capacitor 26 is 0.1 μF, it takes 200 nsec for the voltage drop of 0.2 V to occur even if the device current consumption is 100 mA.
This corresponds to 8 clocks at a clock of 40 MHz, and writing to the entire configuration memory can be sufficiently performed.

FIG. 13 shows the state of each control signal when the power is cut off. At the time of rewriting (writing) of all the configuration memories, the power supply of the SRAM cell section is in the ON state, and the write control signal WE and the word line control signal W
Both L are low, and the plate line control signal PL switches from high to low. By this, before power off,
The power supply voltage is fully applied to the ferroelectric capacitor. In the cut-off waiting state, the power supply of the SRAM cell section is on, and the write control signal WE, the word line control signal WL, and the plate line control signal PL are all low. Each of these control signals is set based on the voltage detection signal PDET.

According to the first embodiment described above, when the power is turned on, the power supply voltage Vdd supplied from the outside is configured as the SRAM cell drive voltage PWR delayed by a time constant according to the characteristics of the ferroelectric capacitor. Since the data is supplied to the memory 23, the data stored in the ferroelectric capacitor can be accurately reproduced when the power is turned on.

Further, according to the first embodiment, when the drop of the power supply voltage Vdd supplied from the outside is detected, the SRAM cell drive voltage PWR is fully applied to the ferroelectric SRAM cell and then the power is cut off. Therefore, the ferroelectric SRA
It is possible to further improve the short-term and long-term reliability of the accumulated data of M cells.

Further, according to the first embodiment, the output of the logical block is forcibly disabled before the writing of the configuration information, and the output of the logical block is enabled after the writing of the configuration information. Once the configuration information has been written, the logical operation after power-on can be started quickly.

As described above, in the first embodiment,
In order to accurately reproduce the data stored in the ferroelectric capacitor when the power is turned on, it is assumed that the SRAM cell drive voltage PWR is supplied to the ferroelectric SRAM cell with a time constant that depends on the characteristics of the ferroelectric capacitor. . However, instead of delaying the supply of the SRAM cell drive voltage PWR, the data stored in the ferroelectric capacitor can be accurately reproduced when the power is turned on by the configurations of the second to fourth embodiments described below.

(Second Embodiment) First, before describing the second embodiment, how the stored data in the ferroelectric capacitor is reproduced when the ferroelectric SRAM cell is powered on, I will explain that. The structure of the ferroelectric SRAM cell is as shown in FIG.
Therefore, description will be given here using the reference numerals given in FIG. At the same time when the power is turned on, the SRAM cell drive voltage PW
R shall be supplied. FIG. 15 shows the hysteresis curve and operating point of the ferroelectric capacitor. Also, FIG.
6 shows simulation results of the SRAM cell drive voltage PWR and potential changes of the storage nodes S1 and S2 when the power is turned on.

As shown in FIG. 15, before the power is turned on, the pair of ferroelectric capacitors 47 and 48 correspond to the potentials (high or low) of the storage nodes S1 and S2 at the time of the previous power shutdown. As a result, residual charges having different directions are stored. As shown in FIG. 16, the potentials of the storage nodes S1 and S2 are zero at the initial stage when the power is turned on. Then, as the SRAM cell drive voltage PWR rises, the p-channel transistors 41 and 42 are turned on and current starts to flow. As a result, the potentials of the storage nodes S1 and S2 rise,
Depending on the direction of the residual charges of the ferroelectric capacitors 47 and 48, the potential of the storage node S1 and the storage node S
The potential of 2 gradually changes.

For example, assume that the potential of storage node S1 was high and the potential of storage node S2 was low at the previous power-off time. In this case, when the power is turned on again, the potential applied to the ferroelectric capacitor 47 connected to the storage node S1 is in the same direction, so the equivalent capacitance of this ferroelectric capacitor 47 is
It is smaller than the other ferroelectric capacitor 48 connected to the node S2. Therefore, the potential of storage node S1 rises faster than the potential of storage node S2.

Since the potential of the storage node S1 reaches the potential at which the n-channel transistor becomes conductive before the potential of the storage node S2, the n-channel transistor 44 connected to the storage node S2.
Turns on. Thereby, the potential of the storage node S2 is pulled down to zero, while the storage node S2
The potential of the node S1 becomes the SRAM cell drive voltage PWR. That is, the potentials of the storage nodes S1 and S2 are determined, and the data stored in the ferroelectric capacitors 47 and 48 are reproduced.

However, the p-channel transistors 41 and 4
If the threshold value of 2 varies, the rising patterns of the potentials of the storage nodes S1 and S2 become opposite, and the data stored in the ferroelectric capacitors 47 and 48 cannot be accurately reproduced. In order to prevent this, in the ferroelectric SRAM cell according to the second embodiment, the size of the p-channel transistors 41 and 42, which is 1.5 to 2 times the size of the conventional n-channel transistors 43 and 44, is changed, The size is the same as or smaller than the size of the n-channel transistors 43 and 44. A ferroelectric SRAM cell having such a size ratio is easily manufactured by a conventional SRAM process.

In FIG. 17, the n-channel transistor 43,
For the case where the size ratio of the p-channel transistors 41 and 42 to 44 is 1 and the case where the size ratio is 1.5, p
The result of simulating the potential change at the time of power-on of the storage node on the side where the potential should be fixed high is shown by changing the threshold variation ΔVth of the channel transistors 41 and 42. As is clear from FIG. 17, when the size ratio is 1, the potential of the storage node is ΔV.
It becomes high at th = 10 mV (curve a), but ΔVth
= 12 mV (curve b) is low. Therefore, the threshold value of the p-channel transistors 41 and 42 is 1
Ferroelectric capacitor 4 even if it varies by about 0 mV
It can be seen that the data accumulated in 7, 48 are accurately reproduced.

On the other hand, when the size ratio is 1.5, ΔVth = 8 mV (curve d) is already stored.
The potential of the node becomes low, and the data is not reproduced accurately. From the simulation result, according to the second embodiment, the p-channel transistor 4
It can be seen that the margin of variation in the threshold values of 1,42 becomes large. It is easily understood that if the size ratio is smaller than 1, the margin of variation in the threshold values of the p-channel transistors 41 and 42 becomes larger.

As described above, according to the second embodiment, since the p-channel transistors 41 and 42 have the same size as or smaller than the n-channel transistors 43 and 44, the potentials of the storage nodes S1 and S2 are turned on when the power is turned on. It takes longer to rise, and the ferroelectric capacitor 47,
48 becomes fully responsive. As a result, the potential difference between the storage nodes S1 and S2 becomes large, and the read operation can be stably performed even if the threshold values of the p-channel transistors 41 and 42 vary. Therefore, the data stored in the ferroelectric capacitors 47 and 48 are accurately reproduced.

(Third Embodiment) FIG. 18 shows a third embodiment.
FIG. 3 is a circuit diagram showing a configuration of a ferroelectric SRAM cell according to the present invention. As shown in FIG. 18, the ferroelectric SRAM cell according to the third embodiment uses resistance elements 241 and 242 instead of the p-channel transistors 41 and 42 in the ferroelectric SRAM cell shown in FIG. is there. The resistance elements 241 and 242 are connected between the SRAM cell part power supply line 51 and the storage nodes S1 and S2, respectively. The resistance values of the resistance elements 241 and 242 are not particularly limited, but are, for example, about 10 kΩ. Since other configurations are the same as the configurations shown in FIG. 3, the same configurations as those in FIG. 3 are denoted by the same reference numerals as those in FIG. The ferroelectric SRAM cell according to the third embodiment is a conventional SR cell.
It is easily manufactured by the AM process.

The influence of variations in resistance values of the resistance elements 241 and 242 will be described. n-channel transistor 4
The off-resistance value of 3,44 is estimated to be 200 kΩ, and the set value of the resistance value of the resistance elements 241 and 242 is set to 10 kΩ, but the resistance value of one resistance element 242 varies and is 8 kΩ.
Suppose that was. n-channel transistors 43, 4
Assuming that the threshold value of 4 is 0.5 V, the storage node S when one of the n-channel transistors turns on.
The potential difference between 1 and S2 is approximately 5 mV according to the following calculation formula.

0.5 V × 10 kΩ / 200 kΩ-0.5
V × 8 kΩ / 200 kΩ = 0.5 V × 2 kΩ / 200 k
Ω = 5mV

In other words, even if the resistance values of the resistance elements 241 and 242 have a variation of 20%, the potential variation of the storage nodes S1 and S2 when the n-channel transistor is turned on is only about 5 mV, and the ferroelectric capacitor. Data reading from 47 and 48 is normally performed.

FIG. 19 shows the resistance value R of the resistance element connected to the storage node on the side where the potential should be determined to be high.
The result of simulating the potential change at the time of power-on of the storage node on the side where the potential should be fixed high is shown by changing (setting value: 10 kΩ). As is apparent from FIG. 19, in the initial stage of power-on, the potentials of the storage nodes S1 and S2 rise almost in the same manner as the rise of the SRAM cell drive voltage PWR. And the resistance value R is 1
For 0 kΩ (curve e), 9 kΩ (curve f) and 8 kΩ (curve g), the storage node potential is high. On the other hand, the resistance value R is 7 kΩ (curve h), 6 k
It is low for Ω (curve i) and 5 kΩ (curve j). Also from this simulation result, the resistance element 24
It can be seen that the data stored in the ferroelectric capacitors 47 and 48 can be accurately reproduced even if the resistance values of 1 and 242 vary by about 20%.

As described above, according to the third embodiment, since the pair of inverters forming the ferroelectric SRAM cell are composed of the resistance elements 241, 242 and the n-channel transistors 43, 44, one resistance element 241 is formed. Even if the resistance value of the storage element S1 differs from the resistance value of the other resistance element 242 by about 20%, the storage nodes S1, S
Since the influence of 2 on the potential change is small, the reading operation can be stably performed. Therefore, the data stored in the ferroelectric capacitors 47 and 48 are accurately reproduced.

(Fourth Embodiment) FIG. 20 shows a fourth embodiment.
FIG. 6 is a waveform diagram showing changes in respective control signals and potentials of storage nodes S1 and S2 in the data reproducing method of the ferroelectric SRAM cell according to the first embodiment. The structure of the ferroelectric SRAM cell is the same as that shown in FIG. 3 or FIG. Figure 2
As shown in 0, when the power is turned on, the bit signal lines 52, 5
After precharging 3 to the high level, the word line control signal WL is set to the high level for a short time, and the access transistors 45 and 46 serving as switches are short time (several nanoseconds).
Only, and the SRAM cell drive voltage PWR is increased from there.

In this way, the storage node S
Since charges are injected into the storage cells S1 and S2, the SRAM cell drive voltage PWR rises with the potentials of the storage nodes S1 and S2 slightly raised. As a result, as shown in the hysteresis curve and operating point of the ferroelectric capacitor in FIG. 21, the difference between the equivalent capacitances (slopes at the operating point) of the ferroelectric capacitors 47 and 48 is larger than that in FIG. Then, the operating points of the ferroelectric capacitors 47 and 48 are changed. Therefore, according to the fourth embodiment, the potential difference between the storage nodes S1 and S2 becomes large, and stable read operation can be performed.
Accumulated data in the ferroelectric capacitors 47 and 48 are accurately reproduced.

In the above, the present invention is not limited to the above-mentioned respective embodiments, but can be variously modified. For example, the power supply circuit and the power supply voltage detection circuit are not limited to the configuration shown in FIG. 4 or 5. Further, the clocks, resistance values, capacitance values, and the like mentioned in the embodiments are examples, and the present invention is not limited to these. The ferroelectric SRAM cell according to the second or third embodiment can be used not only as a programmable logic device but also as a nonvolatile memory such as an IC card or a memory card. Further, the data reproducing method of the ferroelectric SRAM cell according to the fourth embodiment is not limited to the ferroelectric SRAM cell forming the programmable logic device, but may be used as a nonvolatile memory such as an IC card or a memory card. It is also applicable to body SRAM cells.

[0070]

According to the present invention, in a programmable logic device using a ferroelectric SRAM cell, when a power is turned on, a power supply voltage supplied from the outside has a time constant corresponding to the characteristics of the ferroelectric capacitor. Since the delayed SRAM cell drive voltage is supplied to the configuration memory, the data stored in the ferroelectric capacitor can be accurately reproduced when the power is turned on.

Further, according to the present invention, when the drop of the power supply voltage supplied from the outside is detected, the power is cut off after the SRAM cell drive voltage is fully applied to the ferroelectric SRAM cell. It is possible to further improve the short-term and long-term reliability of the accumulated data of the ferroelectric SRAM cell.

Further, according to the present invention, the output of the logic block is forcibly disabled before the writing of the configuration information, and after the writing of the configuration information.
Since the output of the logic block is enabled, once the configuration information is written, the logic operation after power-on can be started quickly.

Further, according to the present invention, a ferroelectric SRAM
In the cell, the data stored in the ferroelectric capacitor can be accurately reproduced when the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a programmable logic device according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a configuration memory configuring the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a ferroelectric SRAM cell that constitutes the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a power supply circuit that constitutes the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a power supply voltage detection circuit configuring the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an example of a look-up table forming the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 7 is a schematic diagram for explaining a programmable wiring forming the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 8 is a diagram for explaining a configuration of programmable wirings that configure the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 9 is a table showing states of respective control signals at the time of basic operation of the ferroelectric SRAM cell forming the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 10 is a diagram showing an example of a control sequence at power-on of the ferroelectric SRAM cell that constitutes the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 11 is a table showing states of respective control signals before power-on of a ferroelectric SRAM cell forming the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 12 is a diagram showing an example of a control sequence when the programmable logic device according to the first embodiment of the present invention is powered off.

FIG. 13 is a table showing states of respective control signals at the time of power-off of the programmable logic device according to the first exemplary embodiment of the present invention.

FIG. 14 is a diagram for explaining the configuration of a general programmable wiring.

FIG. 15 is a diagram showing a hysteresis curve and an operating point of a ferroelectric capacitor when a drive voltage is supplied to a ferroelectric SRAM cell at the same time when power is turned on.

FIG. 16 is a diagram showing a simulation result of potential changes of the SRAM cell drive voltage PWR and the storage nodes S1 and S2 when the drive voltage is supplied to the ferroelectric SRAM cell at the same time when power is turned on.

FIG. 17 is a ferroelectric substance SR according to a second embodiment of the invention.
For an AM cell (size ratio 1) and a general ferroelectric SRAM cell (size ratio 1.5), variations in the threshold value of the p-channel transistor and the storage node on the side where the potential should be determined to be high It is a figure which shows the result of having simulated the relationship with the electric potential change at the time of power-on.

FIG. 18 is a ferroelectric substance SR according to a third embodiment of the invention.
It is a circuit diagram which shows the structure of an AM cell.

FIG. 19 is a ferroelectric substance SR according to a third embodiment of the invention.
FIG. 3 is a diagram showing a result of simulating the relationship between the resistance value of the resistance element connected to the storage node on the side where the potential should be determined to be high in the AM cell and the potential change when the storage node is powered on. is there.

FIG. 20 is a ferroelectric substance SR according to the fourth embodiment of the present invention.
FIG. 6 is a waveform diagram showing changes in respective control signals and potentials of storage nodes S1 and S2 in the method of reproducing data in the AM cell.

FIG. 21 is a ferroelectric substance SR according to a fourth embodiment of the invention.
It is a figure which shows the hysteresis curve and operating point of the ferroelectric capacitor at the time of power-on in the data reproduction method of AM cell.

[Explanation of symbols]

PWR SRAM cell drive voltage S1, S2 Output node (storage node) Vdd power supply voltage 21 power supply circuit, power supply voltage detection circuit (power supply voltage detection / supply circuit) 22 ferroelectric SRAM cell control circuit 26 smoothing capacitance 41, 42 p Channel transistor 43, 44 n-channel transistor 45, 46 Switch (access transistor) 47, 48 Ferroelectric capacitor 51 Power supply line (SRAM cell part power supply line) 52, 53 Bit signal line 61 Operational amplifier 63 Capacitor 64, 241, 242 Resistance element

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B015 HH05 JJ11 KA10 KA33 KB74                       QQ17 QQ18                 5J042 BA10 BA11 CA08 CA20 DA03

Claims (9)

[Claims] 1. A SRAM type memory cell, to which a ferroelectric capacitor is connected, wherein the ferroelectric type capacitor has a memory cell which retains data even after power-off by utilizing dielectric polarization of the ferroelectric type capacitor. A programmable logic device whose logic state is determined according to the data stored in a memory cell, wherein the power supply voltage supplied from the outside is delayed with a time constant according to the characteristics of the ferroelectric capacitor when the power is turned on. A programmable logic device comprising a power supply circuit for supplying the SRAM type memory cell. 2. A SRAM type memory cell, to which a ferroelectric capacitor is connected, has a memory cell which retains data even after power-off by utilizing dielectric polarization of the ferroelectric type capacitor. A programmable logic device whose logic state is determined according to the data stored in a memory cell, which is externally applied to the SRAM type memory cell before the SRAM cell drive voltage drops when the power is turned off. A power supply voltage detection circuit that detects a drop in the supplied power supply voltage, and a ferroelectric SRAM that applies a full SRAM cell drive voltage to the ferroelectric SRAM cell after detecting a drop in the power supply voltage supplied from the outside. A programmable logic device comprising: a cell control circuit. 3. A SRAM type memory cell to which a ferroelectric capacitor is connected and which has a memory cell which retains data even after the power is cut off by utilizing the dielectric polarization of the ferroelectric type capacitor. A programmable logic device whose logic state is determined according to the data stored in a memory cell, which has a ferroelectric capacitor and retains the data even after the power is cut off by using the dielectric polarization of the ferroelectric capacitor. Possible,
A memory that retains information as to whether or not data that determines a logical state has been written, and based on the information that is retained in the memory, the programmable logic device if the data that determines a logical state is not yet written. And a programmable wiring in which the output of the logic block is forcibly disabled and the output of the logic block is enabled when it has been written, and the programmable logic device. 4. A SRAM type memory cell to which a ferroelectric capacitor is connected and which has a memory cell which retains data even after power-off by utilizing the dielectric polarization of the ferroelectric type capacitor. A programmable logic device whose logic state is determined according to the data stored in a memory cell, wherein the power supply voltage supplied from the outside is delayed with a time constant according to the characteristics of the ferroelectric capacitor when the power is turned on. And a power supply circuit for supplying power to the SRAM type memory cell, and a power supply voltage supplied from the outside before the SRAM cell drive voltage supplied to the SRAM type memory cell drops when the power is cut off. After detecting a drop in the power supply voltage supplied from the outside, a SRAM cell drive voltage is applied to the ferroelectric SRAM cell. It has a ferroelectric SRAM cell control circuit to be applied to the memory and a ferroelectric capacitor, and can use the dielectric polarization of the ferroelectric capacitor to retain data even after the power is cut off.
A memory that retains information as to whether or not data that determines a logical state has been written, and based on the information that is retained in the memory, the programmable logic device if the data that determines a logical state is not yet written. And a programmable wiring in which the output of the logic block is forcibly disabled and the output of the logic block is enabled when it has been written, and the programmable logic device. 5. The power supply circuit receives the power supply voltage supplied from the outside as an input, and outputs S to the ferroelectric SRAM cell.
5. The programmable logic device according to claim 1, comprising an operational amplifier that outputs a RAM cell drive voltage, and a CR circuit that is connected to the input side of the operational amplifier and that includes a resistance element and a capacitor. 6. A path for supplying an SRAM cell drive voltage to the SRAM type memory cell as a supply path of an externally supplied power supply voltage, and a power supply voltage drop is detected by the power supply voltage detection circuit. 3. The smoothing capacitor is connected only to the path on the side that supplies the SRAM cell drive voltage.
Alternatively, the programmable logic device described in 4 above. 7. A ferroelectric capacitor is connected to each of the output nodes of a pair of inverters connected so that one output becomes the other input, and the dielectric polarization of the ferroelectric capacitor is utilized. A non-volatile memory that retains data even after power-off, wherein the inverter includes an n-channel transistor and a resistance element connected between a drain terminal of the n-channel transistor and a power supply line. A non-volatile memory characterized by the above. 8. A ferroelectric capacitor is connected to each of the output nodes of a pair of inverters connected so that one output becomes the other input, and the dielectric polarization of the ferroelectric capacitor is utilized. A non-volatile memory that retains data even after power-off, wherein the inverter is composed of a p-channel transistor and an n-channel transistor whose drain terminals are connected to the output node, and the size of the p-channel transistor is the above-mentioned. A nonvolatile memory having the same size as the n-channel transistor or smaller than the size of the n-channel transistor. 9. One ferroelectric capacitor is connected to each output node of a pair of inverters connected so that one output becomes the other input, and the dielectric polarization of the ferroelectric capacitor is utilized. When the nonvolatile memory that retains data even after the power is turned off is turned on, a pair of bit signal lines connected to the output nodes via the switches are precharged, and then the switches are turned on for a short time. Characteristic non-volatile memory data reproduction method.