JP2003258088A - Semiconductor device, and method and apparatus for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration in electromigration resistance and to reduce via resistance while making good use of characteristics of a barrier metal needed when, for example, Cu is used as a wiring material. <P>SOLUTION: The method for manufacturing a semiconductor device 1 having a multi-layered wiring structure includes a barrier metal filming process of forming a 2nd inter-layer insulating film 8 on a 1st wiring layer 4 formed by burying the wiring material in a 1st inter-layer insulating film 7, forming a recess of a trench and a via hole in the 2nd inter-layer insulating film 8, and forming the barrier metal 13 in the recess and a barrier metal removing process of removing the barrier metal 13 at the via hole bottom by etching; and the barrier metal 13 at the bottom of the 2nd wiring trench is left in the barrier metal removing process. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure and a method of manufacturing the same, and a manufacturing device of the semiconductor device, and more particularly, a semiconductor device having a multilayer wiring structure containing Cu, a method of manufacturing the same, and a semiconductor device. Manufacturing equipment.

[0002]

2. Description of the Related Art With the recent high integration of LSIs, there is a growing demand for wiring materials that can achieve higher speed and higher reliability. Therefore, Cu, which has an electric resistance of about two-thirds as compared with the conventional Al alloy wiring, and is expected to have higher electromigration (EM) resistance.
The practical application of wiring is emphasized.

In the wiring formation using Cu, the so-called damascene method is used because dry etching of Cu is generally not easy. This is because, for example, a predetermined groove is formed in advance in an interlayer insulating film made of silicon oxide, a wiring material (Cu) is embedded in the groove, and then surplus wiring material is subjected to chemical mechanical polishing (Chemical Mechanical P
polishing: Hereinafter referred to as CMP. ), And a wiring is formed. Further, in forming a second or more upper layer wiring in a multilayer wiring structure having a plurality of wiring layers, a connection hole (Via) and a wiring groove (Tre) are formed.
nch) is formed, and then a dual damascene method of embedding a wiring material in a lump and removing excess wiring material by CMP may be adopted. Here, FIG. 35 shows an example of a two-layer wiring semiconductor device manufactured by a dual damascene method.

In this semiconductor device 101, a lower wiring layer 104 and an upper wiring layer 105 are formed on a substrate 102, on which devices such as transistors (not shown) are manufactured in advance, with an etch stopper film 103 interposed therebetween. The lower wiring layer 104 and the upper wiring layer 105 are electrically connected via the via 106. The lower wiring layer 104, the upper wiring layer 105, and the via 106 are respectively formed of an interlayer insulating film 107,
It is embedded in 108 and 109. The lower wiring layer 104, the upper wiring layer 105, and the sidewalls and bottoms of the vias 106 are covered with a barrier metal 110 having a Cu diffusion preventing function in order to prevent Cu from diffusing into the interlayer insulating films 107, 108, and 109. Has been done.

The barrier metal 110 has the functions of suppressing the diffusion of Cu atoms into the interlayer insulating film, improving the adhesion between the interlayer insulating film and Cu wiring, and improving the burying property of Cu.
Is an essential layer in the usual forming method.

[0006]

By the way, in the conventional semiconductor device manufactured by the dual damascene method, the lower layer wiring 104 and the upper layer wiring 105 are provided at the bottom of the via 106 via the barrier metal 110 which is a dissimilar metal. To be joined. Therefore, the flow of Cu atoms due to electromigration when a current is applied is discontinuous because it is blocked by the barrier metal 110. As a result, as shown in FIG. 35, for example, when the electrons e ⁻ flow out from the upper layer wiring 105 to the lower layer wiring 104 through the via 106, in the lower layer wiring 104, under the interface with the barrier metal 110 at the bottom of the via 106. It is known that defects (voids) 111 are generated due to excessive movement of Cu atoms. The void 111 causes a problem of lowering electromigration resistance in Cu wiring.

Further, since a metal usually used as a barrier metal has a higher resistance than Cu, the barrier metal 110 separates the lower layer wiring 104 and the via 106, thereby increasing the via resistance and the effective wiring resistance. This is a big problem in further miniaturization of LSI.

Therefore, the present invention was devised to solve the above-mentioned conventional problems, and while utilizing the characteristics of the barrier metal required when using, for example, Cu as the wiring material, it is resistant to electromigration. It is an object of the present invention to provide a semiconductor device, a method of manufacturing the same, and a device for manufacturing a semiconductor device, which can suppress the deterioration of the semiconductor device and reduce the via resistance.

[0009]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring structure, in which a first interlayer insulating film is formed. A second interlayer insulating film is formed on the first wiring layer in which the wiring material is embedded, a concave portion including a trench and a via hole is formed in the second interlayer insulating film, and a barrier metal is formed in the concave portion. A barrier metal film forming step for forming a film,
A barrier metal removing step of removing at least the barrier metal at the bottom of the via hole by etching, wherein the barrier metal at the bottom of the second wiring trench is left in the barrier metal removing step. .

In the method of manufacturing a semiconductor device configured as described above, the barrier metal formed on the bottom of the via hole is preferentially removed in the barrier metal removing step to leave the barrier metal on the bottom of the trench. Since the barrier metal does not exist between the first wiring layer and the via without impairing the characteristics of the barrier metal, the flow of wiring material atoms due to electromigration becomes continuous, and the resistance of the via is reduced. It does not cause an increase.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring structure, in which a wiring material is embedded in a first interlayer insulating film on a first wiring layer. Then, a second interlayer insulating film, an insulating film having a wiring material diffusion preventing function, and a third interlayer insulating film are formed in this order to form a concave portion including a trench and a via hole, and a barrier metal is formed in the concave portion. And a barrier metal removing step of removing at least the barrier metal at the bottom of the via hole by etching. In the barrier metal removing step, the wiring material diffusion prevention is performed at the bottom of the trench. It is characterized in that an insulating film having a function is left.

In the method of manufacturing a semiconductor device configured as described above, since the barrier metal is formed with the insulating film having the wiring material diffusion preventing function remaining at the bottom of the trench, the barrier metal is removed in the barrier metal removing step. Even when the barrier metal at the bottom of the trench is completely removed, like the barrier metal at the bottom of the via hole, diffusion of the wiring material into the interlayer insulating film can be prevented. Therefore, since the barrier metal does not exist between the first wiring layer and the via without impairing the characteristics of the barrier metal, the flow of wiring material atoms due to electromigration becomes continuous, and It does not cause an increase in via resistance.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring structure, in which a wiring material is embedded in a first interlayer insulating film on a first wiring layer. Then, an insulating film having a wiring material diffusion preventing function and a second interlayer insulating film are formed in this order, and the insulating film having the wiring material diffusion preventing function and the second interlayer insulating film are formed of trenches and via holes. A recess forming step of forming a recess; a barrier metal film forming step of forming a barrier metal in the recess so as not to cover the insulating film having the wiring material diffusion preventing function at the bottom of the via hole; And an insulating film removing step of removing the insulating film having a wiring material diffusion preventing function by etching.

In the method of manufacturing a semiconductor device configured as described above, the barrier metal is formed on the insulating film having the wiring material diffusion preventing function at the bottom of the via hole, with the insulating film having the wiring material diffusion preventing function remaining. A barrier metal film is formed while controlling the conditions so that the first wiring layer is not deposited. Then, the insulating film having the wiring material diffusion preventing function at the bottom of the via hole is removed by etching to expose the first wiring layer. Therefore, without impairing the characteristics of the barrier metal,
Since the barrier metal is not present between the first wiring layer and the via, the flow of wiring material atoms due to electromigration is continuous, and the via resistance is not increased.

Further, the semiconductor device according to the present invention is a semiconductor device having a multi-layer wiring structure, in which a wiring material is embedded in a laminated film of a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function. A first wiring layer, a second wiring layer disposed above the first wiring layer, and a via electrically connecting the first wiring layer and the second wiring layer. And the second wiring layer and the via are embedded in the second interlayer insulating film via a barrier metal.

In the semiconductor device having the above-described structure, the atoms of the wiring material can move between the via and the first wiring layer, so that when the current flows, the via and the first wiring are electromigrated. It is possible to suppress the generation of voids that occur at the interface with the layer, and improve electromigration resistance. Also,
In the semiconductor device in which the barrier metal between the via and the first wiring layer is removed, the wiring material of the via may be diffused into the first interlayer insulating film when misalignment occurs between layers. In the semiconductor device having the above-described structure, since the film made of the insulating material having the wiring material diffusion preventing function is added to the surface of the first interlayer insulating film, even if misalignment occurs between layers. , Diffusion of wiring material into the first interlayer insulating film is prevented.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a multilayer wiring structure, in which a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function are provided in this order. A first wiring layer forming step of forming a laminated film by forming a wiring material in the laminated film to form a first wiring layer, and forming a second interlayer insulating film on the first wiring layer. And a barrier metal film forming step of forming a concave portion including a trench and a via hole in the second interlayer insulating film and forming a barrier metal in the concave portion, and at least removing the barrier metal at the bottom of the via hole by etching. And a barrier metal removing step.

In the method of manufacturing a semiconductor device having the above-described structure, the via is formed so that the wiring material can move between the via and the first wiring layer. In addition, it is possible to suppress the generation of voids that occur at the interface between the via and the first wiring layer due to electromigration, and it is possible to improve the resistance to electromigration. Further, in the above-described method for manufacturing a semiconductor device, a laminated film of a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function is formed, and a wiring material is embedded therein to form a first wiring layer. Since the via and the second wiring layer are formed after forming the via, it is possible to ensure the diffusion of the wiring material into the first interlayer insulating film even when the interlayer displacement occurs between the via and the first wiring layer. Therefore, it is possible to manufacture a semiconductor device which can be prevented.

Further, in the semiconductor device manufacturing apparatus according to the present invention, the atom of the wiring material can be moved between the via and the wiring layer existing thereunder, and the wiring material is a barrier metal. A manufacturing apparatus for a semiconductor device having a multilayer wiring structure embedded in an interlayer insulating film via a physical etching chamber for removing a natural oxide film on the wiring layer, and a film for forming the barrier metal. For forming a barrier metal film, a dry etching chamber for removing the barrier metal, a Cu seed layer film forming chamber for forming a Cu seed layer, and an object to be processed without exposing each chamber to the atmosphere. And a core chamber capable of continuously processing

The semiconductor device manufacturing apparatus as described above is an apparatus for manufacturing a semiconductor device having a multilayer wiring in which atoms of a wiring material are movable between a via and a wiring layer existing thereunder. is there. After the wiring layer is formed, the object to be processed can be carried in and out without exposing each chamber to the atmosphere until the Cu seed layer is formed, and continuous processing is realized.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device to which the present invention is applied, a method for manufacturing the same, and an apparatus for manufacturing a semiconductor device will be described in detail with reference to the drawings.

In the semiconductor device targeted by the present invention, as will be described later, the barrier metal at the bottom of the via is removed, whereby atoms of the wiring material move between the via and the wiring layer below the via. A multilayer wiring structure that is made possible is a basic component.

First, a first example of a semiconductor device having such a structure and using Cu as a wiring material is shown in FIG.
Will be explained. In this semiconductor device 1, a lower wiring layer 4 is formed on a substrate 2 on which devices such as transistors (not shown) are manufactured in advance with an etch stopper film 3 interposed therebetween.
And an upper wiring layer 5 are formed, and the lower wiring layer 4 and the upper wiring layer 5 are electrically connected via a via 6. The lower wiring layer 4, the via 6 and the upper wiring layer 5 are respectively
Embedded in the inter-layer insulating film 7, the second inter-layer insulating film 8 and the third inter-layer insulating film 9. A cap film 10 for preventing Cu from diffusing from the lower wiring layer 4 to the second interlayer insulating film 8 is formed on the upper surfaces of the lower wiring layer 4 and the first interlayer insulating film 7. . The upper wiring layer 5 and the third wiring layer
Similarly, a cap film 11 is formed on the upper surface of the interlayer insulating film 9. A Cu diffusion prevention insulating film 12 is formed on the bottom of the upper wiring layer 5.

Further, in order to prevent Cu, which is a wiring material, from diffusing into the interlayer insulating film, the bottoms and side walls of the lower wiring layer 4 and the upper wiring layer 5 and the side wall of the via 6 have a Cu diffusion preventing function. It is covered with a barrier metal 13.

In the semiconductor device 1 of the present invention, Cu, which is a wiring material, can be moved between the via 6 and the lower wiring layer 4, as described above. That is, unlike the conventional semiconductor device having a multilayer wiring structure in which the via and the lower wiring layer are bonded via a different metal such as a barrier metal, the semiconductor device 1 of the present invention has the barrier metal 13 at the bottom of the via 6.
Is not present, the via 6 and the lower wiring layer 4 are directly joined.

Here, it is preferable that the via 6 and the lower wiring layer 4 are joined without the barrier metal 13 at all, but if the wiring material Cu can be moved. Any condition, via 6 C
The barrier metal 1 is partially provided between the lower wiring layer 4 and the via 6 so that u and Cu of the lower wiring layer 4 are partially joined.
The barrier metal 13 may remain in the interface between the via 6 and the lower wiring layer 4, and the barrier metal 13 may remain extremely thin.

Since Cu can be moved between the via 6 and the lower wiring layer 4, the discontinuity of the flow of Cu atoms from the via 6 to the lower wiring layer 4 is eliminated and the electromigration resistance is improved. To do. Considering the case where electrons e ⁻ flow out from the upper wiring layer 5 through the via 6 to the lower wiring layer 4 as shown by the arrow in FIG. 1, the flow of Cu atoms is continuous even at the bottom of the via 6. Therefore, voids are less likely to be generated.

Further, in this semiconductor device 1, is it possible to move Cu between the via 6 and the lower wiring layer 4 so that there is no barrier metal 13 between the via 6 and the lower wiring layer 4. , Because the amount is extremely reduced, C
It is also possible to obtain an effect that an increase in via resistance caused by the barrier metal 13 having a higher resistance than that of u can be suppressed.

As described above, the semiconductor device 1 of the present invention is
By improving the electromigration resistance, it is possible to exhibit high reliability and, at the same time, reduce the wiring resistance.

Next, a method of manufacturing the semiconductor device 1 of the first example shown in FIG. 1 by the dual damascene method will be described with reference to FIGS.

First, a dual damascene structure is formed as shown in FIG. That is, the etch stopper film 3 is laminated on the substrate 2, the first interlayer insulating film 7 is formed thereon, and then Cu is buried by, for example, a damascene method to form the lower wiring layer 4. Next, a cap film 10, a second interlayer insulating film 8, a Cu diffusion preventing insulating film 12, and a third interlayer insulating film 9 are formed in this order on the upper surface of the lower wiring layer 4, and a photoresist and Via hole 14 by dry etching
And the trench 15 is formed. At this time, beer hole 1
The surface of the lower wiring layer 4 is exposed at the bottom of the trench 4 and the trench 1
The Cu diffusion prevention insulating film 12 is exposed at the bottom of the film 5. As an example, the first interlayer insulating film 7, the second interlayer insulating film 8, and the third interlayer insulating film 9 are formed of SiOC, and the cap film 10 is formed of SiC.

The first interlayer insulating film 7, the second interlayer insulating film 8 and the third interlayer insulating film 9 are not limited to SiOC, but other low-level materials such as SiO ₂ , SiOF and organic compounds can be used. It may be a k (low dielectric constant) material.

Next, as shown in FIG. 3, in order to prevent Cu from diffusing into the interlayer insulating film, the barrier metal 13 is PVd.
D (Physical Vapor Deposition) method and CVD (Chemica
l Vapor Deposition) method is used to form a film. At this time,
When the film thickness of the barrier metal 13 formed on the bottom of the trench 15 is a and the film thickness of the barrier metal 13 formed on the bottom of the via hole 14 is b, this film thickness ratio (b /
The film formation is controlled so that a) is 60% or less. In order to set the film thickness ratio (b / a) to 60% or less, some device such as optimizing the distance between the target and the substrate is required. As an example, a barrier metal 1 made of TaN
3 was formed into a film having a thickness of 30 nm by the PVD method. The film forming conditions are shown below.

Barrier metal film forming conditions DC power: 15 kW Process pressure: 0.1 Pa Process gas: Ar = 10 sccm, N ₂ = 20 scc
m Substrate heating temperature: 200 ℃

As the barrier metal 13, TaN is used.
Besides, a material having an excellent barrier property against Cu such as Ta, W, WN, Ti, TiN, and TiSiN can be used.

Next, without exposing the substrate 2 to the atmosphere, the film formation of the barrier metal 13 is continued, and the inductively coupled plasma (Indu
ctively Coupled Plasma (ICP), Electron Cyclotron Resonance (ECR) and Reactive Ion Etching (Magnetically Enh)
low-pressure dry etching using high-density plasma such as anced Reactive Ion etching (MERIE),
As shown in FIG. 4, the barrier metal 13 at the bottom of the via hole 14 is completely removed or made extremely thin. At this time,
Etching is performed so that the etching rate ratio between the bottom of the via hole 14 and the bottom of the trench 15 is 80% or more. As the etching gas, a fluorine-based gas such as NF ₃ or SF ₃ can be used.

In order to set the etching rate ratio between the bottom of the via hole 14 and the bottom of the trench 15 to 80% or more, the bias applied to the substrate is controlled to control the directivity of ions and / or radicals contributing to etching. Therefore, it is necessary to take some measures such as changing the pressure in the process chamber.

At this time, in order to remove the barrier metal 13 at the bottom of the via hole 14 preferentially without removing the barrier metal 13 on the sidewalls of the via hole 14 and the trench 15 as much as possible, as shown in FIG. A high frequency power is applied to 2 to generate a bias, and anisotropic etching is performed in which ions in the plasma are drawn vertically to the substrate 2. In FIG. 5, the case where NF ₃ is used as an etching gas is taken as an example, and the substrate 2 is omitted. As an example, conditions of low pressure dry etching using inductively coupled plasma of the barrier metal 13 are shown below.

[0039]Dry etching conditions Etching gas: NF_Three Process pressure: 1.0Pa ICP power: 400W ICP frequency: 13.56MHz Substrate bias power: 300W Substrate bias frequency: 4MHz

In this dry etching, the via hole 1
The barrier metal 13 on the bottom of the trench 4 is etched at the same time as the barrier metal 13 on the bottom of the trench 15 is etched at the same time. However, when the barrier metal 13 is formed in the previous step, the barrier metal 13 is formed on the bottom of the trench 15. The ratio (b / a) between the film thickness of the barrier metal 13 to be formed and the film thickness of the barrier metal 13 formed at the bottom of the via hole 14 is set to 60% or less, and the barrier at the bottom of the via hole 14 is set. Since the etching is performed so that the ratio of the etching rate of the metal 13 to the etching rate of the barrier metal 13 at the bottom of the trench 15 is 80% or more, the barrier metal 13 at the bottom of the via hole 14 is removed preferentially. , Barrier metal 1 at the bottom of trench 15
3 remains in a film thickness necessary to prevent Cu diffusion, and trench 15
There is no risk of Cu diffusing from the bottom of the second interlayer insulating film 8. The film thickness of the barrier metal 13 and the via hole 14 formed on the bottom of the trench 15 when the barrier metal 13 is formed.
Of the barrier metal 13 formed on the bottom of the film (b
/ A) is 60% or less, and barrier metal 13
The ratio of the etching rate of the barrier metal 13 at the bottom of the via hole 14 to the etching rate of the barrier metal 13 at the bottom of the trench 15 during etching is 80.
%, The barrier metal 13 at the bottom of the trench 15 is completely removed, or a thin film is formed such that sufficient barrier properties cannot be obtained, resulting in Cu interlayer insulation. May allow diffusion into the membrane.

Next, without exposing the substrate 2 to the atmosphere, the barrier metal 13 is continuously etched, and as shown in FIG.
The u seed layer 16 is formed. As an example, the Cu seed layer 16 was formed in a film thickness of 150 nm by the PVD method. The film forming conditions are shown below.

[0042]Cu seed layer deposition conditions DC power: 12kW Pressure: 0.1Pa Film formation temperature: -20 ° C

Next, as shown in FIG. 7, Cu 17 is buried in the via hole 14 and the trench 15 by electrolytic plating. As an example, Cu17 was deposited with a deposition amount of 1.5 μm. The film forming conditions are shown below.

[0044]Electrolytic plating conditions Plating solution: Copper sulfate-based Cu electrolytic plating solution (Microfa
b Cu 2000 series, manufactured by EEJA) Plating current value: 2.83A Plating time: 4 minutes 30 seconds (1.0 μm) Plating solution temperature: 18 ℃

Next, as shown in FIG.
And Cu is left only in the trench 15 and the via 6 and the upper wiring layer 5 are formed. Generally applied technology is C
Polishing by MP. In this process, the via hole 14
It is necessary to finish polishing on the surface of the third interlayer insulating film 9 so that the wiring material is left only in the trenches 15 and the Cu 17 and the barrier metal 13 are not left on the third interlayer insulating film 9. It is preferable to control the polishing.
In the polishing process by CMP, two or more kinds of materials, Cu 17 and barrier metal 13, must be removed by polishing, so it is necessary to control the polishing liquid (slurry), polishing conditions, etc. depending on the material to be polished. Therefore, polishing in multiple steps may be necessary. Excess Cu as an example
CMP was performed under the following conditions.

[0046]CMP conditions Polishing pressure: 100g / cm^Two Rotation speed: 30 rpm Rotating pad: Lamination of non-woven fabric and independent foam Slurry: H_TwoO_TwoAddition (alumina-containing slurry) Flow rate: 100 cc / min Temperature: 25-30 ° C

Finally, a cap film 11 made of, for example, SiC is formed on the entire surfaces of the upper wiring layer 5 and the third interlayer insulating film 9 by the CVD method to form a semiconductor having a two-layer wiring as shown in FIG. The device 1 is obtained. The film thickness of the cap film 11 can be set to 50 nm, for example.

In the method of manufacturing the semiconductor device 1 of the first example as described above, the trench 15 is formed when the multilayer wiring in which the Cu atoms can be moved between the via 6 and the lower wiring layer 4 is manufactured. The barrier metal 13 at the bottom of is left. Specifically, the barrier metal 1 between the bottom of the via hole 14 and the bottom of the trench 15 at the time of forming the barrier metal 13 is formed.
3 of the film thickness ratio, and the bottom of the via hole 14,
The ratio of the etching rate with the bottom of the trench 15 is defined. As a result, even when the barrier metal 13 at the bottom of the via hole 14 is completely removed by etching,
It is possible to prevent Cu from diffusing into the second interlayer insulating film 8.

Next, a second example of the semiconductor device having a multilayer wiring in which the atoms of the wiring material can be moved between the via and the wiring layer existing thereunder will be described with reference to FIG. To do. In the following description, the same members as those of the semiconductor device 1 shown in FIG. 1 described above are designated by the same reference numerals, and detailed description thereof may be omitted.

This semiconductor device 21 has a substrate 2 on which devices such as transistors (not shown) are prepared in advance.
A lower wiring layer 4 and an upper wiring layer 5 are formed on the upper surface of the lower wiring layer 4 and the upper wiring layer 5 via the etch stopper film 3.
And are electrically connected via the via 6. The lower wiring layer 4, the via 6 and the upper wiring layer 5 are respectively provided with a first interlayer insulating film 7, a second interlayer insulating film 8 and a third interlayer insulating film 9.
Embedded in. Further, on the upper surfaces of the lower wiring layer 4 and the first interlayer insulating film 7, a cap film 10 for preventing diffusion of Cu from the lower wiring layer 4 to the second interlayer insulating film 8.
Is deposited. A cap film 11 is similarly formed on the upper surfaces of the upper wiring layer 5 and the third interlayer insulating film 9. A Cu diffusion prevention insulating film 12 is formed on the bottom of the upper wiring layer 5.

In order to prevent Cu, which is a wiring material, from diffusing into the interlayer insulating film, the bottom and side walls of the lower wiring layer 4, the vias 6 and the side walls of the upper wiring layer 5 have a Cu diffusion preventing function. It is covered with a barrier metal 13.

In the semiconductor device 21 of the present invention, as described above, the wiring material Cu is formed between the via 6 and the lower wiring layer 4.
Are in a movable state. That is, unlike the conventional semiconductor device having a multi-layer wiring structure in which the via and the lower wiring layer are bonded via a different metal such as a barrier metal, the semiconductor device 21 of the present invention has the barrier metal 13 at the bottom of the via 6. Is not present, the via 6 and the lower wiring layer 4 are directly joined.

Since Cu can be moved between the via 6 and the lower wiring layer 4, the discontinuity of the flow of Cu atoms from the via 6 to the lower wiring layer 4 is eliminated, and the electromigration resistance is improved. To do.

In this semiconductor device 21, the barrier metal 13 between the via 6 and the lower wiring layer 4 does not exist at all, or the amount thereof is extremely reduced, so that the barrier metal 13 has a larger resistance than Cu. It is also possible to obtain the effect of suppressing an increase in via resistance due to the metal 13.

As described above, the semiconductor device 21 of the present invention
Shows high reliability due to improved electromigration resistance, and at the same time realizes reduction of wiring resistance.

Further, the semiconductor device 21 of the second example of the present invention
At the bottom of the upper wiring layer 5, since the Cu diffusion preventing insulating film 12 having a high barrier property against Cu remains without being removed, diffusion of Cu to the second interlayer insulating film 8 thereunder is prevented. it can. At the bottom of the upper wiring layer 5, the barrier metal 13 is removed or C
The Cu diffusion prevention insulating film 12 may be made thin enough to prevent the diffusion of u and may contact the upper wiring layer 5.

As the Cu diffusion prevention insulating film 12,
A material having a high barrier property against Cu, which is a wiring material, and an insulating property can be used. Specifically, SiC, SiN, or the like can be used.

Next, a method of manufacturing the semiconductor device 21 of the second example shown in FIG. 9 by the dual damascene method will be described with reference to FIGS. 10 to 15.

First, similarly to the semiconductor device of the first example described above, a dual damascene structure as shown in FIG. 10 is formed. That is, the etch stopper film 3 is formed on the substrate 2.
Are laminated and a first interlayer insulating film 7 is formed thereon, and then Cu is embedded by, for example, a damascene method to form a lower wiring layer 4. Next, the cap film 10 is formed on the upper surface of the lower wiring layer 4.
A second interlayer insulating film 8 and a Cu diffusion prevention insulating film 12
And a third interlayer insulating film 9 are formed in this order, and a via hole 14 and a trench 15 are formed by photoresist and dry etching. At this time, the surface of the lower wiring layer 4 is exposed at the bottom of the via hole 14, and the Cu diffusion prevention insulating film 12 is exposed at the bottom of the trench 15. As an example, the first interlayer insulating film 7, the second interlayer insulating film 8, and the third interlayer insulating film 9 are formed of SiOC, the cap film 10 is formed of SiC, and the Cu diffusion prevention insulating film 12 is formed of SiC. Formed by.

Next, as shown in FIG. 11, in order to prevent Cu from diffusing into the interlayer insulating film, the barrier metal 13 is doped with P.
The film is formed by the VD method or the CVD method. As an example, Ta
The barrier metal 13 made of N is formed into a film thickness 30 by the PVD method
The film was formed at a thickness of nm. The film forming conditions are shown below.

[0061]Barrier metal deposition conditions DC power: 15kW Process pressure: 0.1Pa Process gas: Ar = 10 sccm, N_Two= 20 scc
m Substrate heating temperature: 200 ° C

Next, without exposing the substrate 2 to the atmosphere, film formation of the barrier metal 13 is continued, followed by inductively coupled plasma, EC.
Low pressure dry etching using high density plasma such as R or MERIE is performed to completely remove the barrier metal 13 at the bottom of the via hole 14 as shown in FIG.
Make it extremely thin. The etching gas is NF ₃ , S
Fluorine-based gas such as F ₃ can be used.

At this time, the barrier metal 13 on the sidewalls of the via hole 14 and the trench 15 is not removed as much as possible, and the barrier metal 13 at the bottom of the via hole 14 is removed preferentially, which is described above with reference to FIG. As described above, anisotropic etching is performed in which high-frequency power is applied to the substrate 2 to generate a bias, and ions in the plasma are drawn vertically to the substrate 2. As an example, the conditions for low pressure dry etching of the barrier metal 13 using inductively coupled plasma are shown below.

[0064]Dry etching conditions Etching gas: NF_Three Process pressure: 1.0Pa ICP power: 400W ICP frequency: 13.56MHz Substrate bias power: 300W Substrate bias frequency: 4MHz

In this dry etching, the via hole 1
At the same time that the barrier metal 13 at the bottom of No. 4 is etched, the barrier metal 13 at the bottom of the trench 15 is also etched at the same time and is completely removed or thinned so that sufficient Cu barrier property cannot be obtained. Since the Cu diffusion prevention insulating film 12 having a high barrier property against Cu remains at the bottom of the trench 15, the second portion is formed from the bottom of the trench 15.
There is no possibility that Cu will diffuse into the interlayer insulating film 8 of FIG.

Next, without exposing the substrate 2 to the atmosphere, the barrier metal 13 is continuously etched, as shown in FIG.
The Cu seed layer 16 is formed. As an example, the Cu seed layer 16 was formed in a film thickness of 150 nm by the PVD method. The film forming conditions were the same as the Cu seed layer film forming conditions described in the first example.

Next, as shown in FIG. 14, Cu 17 is buried in the via hole 14 and the trench 15 by electrolytic plating. As an example, Cu17 was deposited with a deposition amount of 1.5 μm. The film forming conditions were the same as the electrolytic plating conditions of the first example described above.

Next, as shown in FIG. 15, CMP is performed to leave Cu only in the via holes 14 and trenches 15,
The via 6 and the upper wiring layer 5 are formed. The CMP conditions were the same as in the first example described above.

Finally, a cap film 11 made of, for example, SiC is formed on the entire surfaces of the upper wiring layer 5 and the third interlayer insulating film 9 by a CVD method to form a semiconductor having a two-layer wiring as shown in FIG. The device 21 is obtained. Cap film 11
The film thickness of can be, for example, 50 nm.

In the method of manufacturing the semiconductor device 21 of the second example as described above, when manufacturing the multilayer wiring in which Cu atoms can move between the via 6 and the lower wiring layer 4,
Since the Cu diffusion prevention insulating film 12 having a high barrier property against Cu is left at the bottom of the trench 15, the barrier metal 13 at the bottom of the via hole 14 is removed at the same time as the barrier metal 13 at the bottom of the trench 15 is removed. Even in this case, Cu can be prevented from diffusing from the bottom of the trench 15 into the second interlayer insulating film 8.

Next, a third example of the semiconductor device having a multilayer wiring in which the atoms of the wiring material can be moved between the via and the wiring layer existing thereunder will be described with reference to FIG. To do.

This semiconductor device 31 has a substrate 2 on which devices such as transistors (not shown) are manufactured in advance.
A lower wiring layer 4 and an upper wiring layer 5 are formed on the upper surface of the lower wiring layer 4 and the upper wiring layer 5 via the etch stopper film 3.
And are electrically connected via the via 6. The lower wiring layer 4, the via 6 and the upper wiring layer 5 are embedded in a first interlayer insulating film 7 and a second interlayer insulating film 8, respectively. Further, on the upper surfaces of the lower wiring layer 4 and the first interlayer insulating film 7,
A cap film 10 for preventing diffusion of Cu from the lower wiring layer 4 to the second interlayer insulating film 8 is formed. In addition, on the upper surfaces of the upper wiring layer 5 and the second interlayer insulating film 8,
Similarly, the cap film 11 is formed.

In order to prevent Cu, which is a wiring material, from diffusing into the interlayer insulating film, the bottom and side walls of the lower wiring layer 4, the vias 6 and the side walls of the upper wiring layer 5 have a Cu diffusion preventing function. It is covered with a barrier metal 13.

In the semiconductor device 31 of the present invention, as described above, the wiring material Cu is formed between the via 6 and the lower wiring layer 4.
Are in a movable state. That is, unlike the conventional semiconductor device having a multilayer wiring structure in which the via and the lower wiring layer are bonded via a different metal such as a barrier metal, the semiconductor device 31 of the present invention has the barrier metal 13 at the bottom of the via 6. Is not present, the via 6 and the lower wiring layer 4 are directly joined.

Since Cu can be moved between the via 6 and the lower wiring layer 4, the discontinuity of the flow of Cu atoms from the via 6 to the lower wiring layer 4 is eliminated and the electromigration resistance is improved. To do.

Further, in this semiconductor device 31, since the barrier metal 13 between the via 6 and the lower wiring layer 4 does not exist at all or the amount thereof is extremely reduced, the barrier having a higher resistance than Cu. It is also possible to obtain the effect of suppressing an increase in via resistance due to the metal 13.

As described above, the semiconductor device 31 of the present invention
Shows high reliability due to improved electromigration resistance, and at the same time realizes reduction of wiring resistance.

In the semiconductor device 31 shown in FIG.
Although the interlayer insulating film filling the via 6 and the upper wiring layer 5 has a single-layer structure of the second interlayer insulating film 8, like the semiconductor device 1 of the first example and the semiconductor device 21 of the second example. It may have a laminated structure.

Next, a method of manufacturing the semiconductor device 31 of the third example shown in FIG. 16 described above by the dual damascene method will be described with reference to FIGS.

First, similarly to the semiconductor device of the first example described above, a dual damascene structure as shown in FIG. 17 is formed. That is, the etch stopper film 3 is formed on the substrate 2.
Are laminated and a first interlayer insulating film 7 is formed thereon, and then Cu is embedded by, for example, a damascene method to form a lower wiring layer 4. Next, the cap film 10 is formed on the upper surface of the lower wiring layer 4.
Then, the second interlayer insulating film 8 is formed, and the via hole 14 and the trench 1 are formed by photoresist and dry etching.
5 is formed. At this time, the cap film 10 is exposed at the bottom of the via hole 14. As an example, the first
The inter-layer insulating film 7 and the second inter-layer insulating film 8 were formed of SiOC, and the cap film 10 was formed of SiC.

Next, in order to prevent Cu from diffusing into the interlayer insulating film, a barrier metal 13 is formed by a PVD method, a CVD method or the like. At this time, the cap film 10, that is, SiC is exposed at the bottom of the via hole 14, and the second interlayer insulating film 8, that is, SiOC is exposed at the other portions.

Here, by utilizing the difference in the gas adsorption and dissociation probabilities in the initial stage of the barrier metal 13 between the cap film 10 and the second interlayer insulating film 8, the formation of the barrier metal 13 on the entire surface of the cap film 10 is started. Film formation is performed under a condition that the time (t1) until the formation of the barrier metal 13 on the entire surface of the second interlayer insulating film 8 is started (t2). Specifically, by the time t1 the second interlayer insulating film 8
It is assumed that the barrier metal 13 is formed to a thickness of 3 nm on the upper side. As a result, as shown in FIG. 18, the via hole 1
The barrier metal 13 can be formed on the other second interlayer insulating film 8 while suppressing the formation of the barrier metal 13 on the cap film 10 at the bottom of No. 4.

When the cap film 10 is made of SiC and the second interlayer insulating film 8 is made of SiOC, as an example,
A barrier metal 13 made of WN was formed by the CVD method. The film forming conditions at this time are shown below.

[0084]Barrier metal deposition conditions Process pressure: 40Pa Process gas: WF₆= 7 sccm, SiH_Four= 40s
ccm, NH_Three= 11 sccm, Ar = 100 sccm Substrate heating temperature: 380 ° C Film thickness: 10 nm

As the barrier metal 13 to be formed, in addition to WN, Ta, TaN, W, WSiN, Ti,
Materials having excellent barrier properties against Cu such as TiN and TiSiN can be used.

Next, the cap film 10 exposed at the bottom of the via hole 14 is removed by dry etching, as shown in FIG.
The lower wiring layer 4 is exposed as shown in FIG. At this time, W
SiC without etching the barrier metal 13 made of N
The conditions are selected so that only the cap film 10 made of is etched. An example of etching conditions is shown below.

[0087]Etching conditions Process pressure: 20mTorr Process gas: CH_TwoF_Two= 20 sccm, O_Two= 20
sccm, CF_Four= 20 sccm, Ar = 200 scc
m Power: 1000 / 100W Electrode temperature: 30 ℃

Next, a Cu seed layer (not shown) is formed by, eg, PVD method. The film forming conditions were the same as the Cu seed film forming conditions of the first example described above.

Next, as shown in FIG. 20, Cu 17 is buried in the via hole 14 and the trench 15 by electrolytic plating. As an example, Cu17 was deposited with a deposition amount of 1.5 μm. The conditions of electrolytic plating were the same as those of the first example described above.

Next, as shown in FIG. 21, CMP is performed to leave Cu only in the via holes 14 and trenches 15,
The via 6 and the upper wiring layer 5 are formed. The CMP conditions were the same as in the first example described above.

Finally, a cap film 11 made of, for example, SiC is formed on the entire surfaces of the upper wiring layer 5 and the third interlayer insulating film 9 by a CVD method to form a semiconductor having a two-layer wiring as shown in FIG. The device 31 is obtained. Cap film 1
The film thickness of 1 can be 50 nm, for example.

In the method of manufacturing the semiconductor device 31 as described above, when a multilayer wiring in which Cu atoms can be moved between the via 6 and the lower wiring layer 4 is manufactured, an insulating film is formed on the bottom of the via hole 14. The barrier metal 13 is formed while leaving the cap film 10 as described above. Beer hall 1
Since different types of insulating films are used for the cap film 10 at the bottom of 4 and other portions such as the second interlayer insulating film 8,
Since the gas adsorption and dissociation probabilities at the initial stage of film formation of the barrier metal 13 are different, the barrier metal 13 is formed at other places without forming a film on the bottom of the via hole 14. Therefore, when the lower wiring layer 4 is exposed in the next step, only the cap film 10 at the bottom of the via hole 14 needs to be etched for connection with the lower wiring layer 4, and the step of etching the barrier metal 13 is unnecessary. Becomes

By the way, in a semiconductor device having a multi-layer wiring structure, a pattern forming process for forming a groove structure is performed for each layer, but a slight misalignment may occur at that time. In the semiconductor device 41 having a multilayer wiring structure in which Cu atoms are movable between the via 6 and the lower wiring layer 4 as in the first example, the second example and the third example described above. A case where the positional displacement occurs will be described with reference to FIG.

As apparent from FIG. 22, when the semiconductor device 41 of the present invention is displaced, the Cu of the via 6 is changed.
2 and the first interlayer insulating film 7 filling the lower wiring layer 4 are shown in FIG.
2 There is a possibility of causing a serious problem such as direct contact in a region D surrounded by a middle dotted line and diffusion of Cu from the via 6 to the first interlayer insulating film 7 to cause a short circuit between wirings.

The diffusion of Cu due to this displacement cannot occur in a semiconductor device having a structure in which a barrier metal exists at the bottom of a via as in the conventional case. As shown in FIG. 23, in the case of a conventional semiconductor device 51 having a multi-layered wiring structure in which a positional deviation has occurred, since the barrier metal 113 is present at the bottom of the via 106, this occurs when the positional deviation occurs. This is because the barrier metal 113 avoids direct contact between Cu of the via 106 and the first interlayer insulating film 117 that fills the lower wiring layer 104.

Therefore, C is provided between the via 6 and the lower wiring layer 4.
A semiconductor device of a fourth example, which solves the above-mentioned problem of Cu diffusion due to the positional deviation while utilizing the advantage of the present invention in which the u atom can be moved, will be described with reference to FIG.

This semiconductor device 61 is a substrate 2 in which devices such as transistors (not shown) are prepared in advance.
A lower wiring layer 4 and an upper wiring layer 5 are formed on the upper surface of the lower wiring layer 4 and the upper wiring layer 5 via the etch stopper film 3.
And are electrically connected via the via 6. The lower wiring layer 4, the via 6 and the upper wiring layer 5 are respectively provided with a first interlayer insulating film 7, a second interlayer insulating film 8 and a third interlayer insulating film 9.
Embedded in. Further, on the upper surfaces of the lower wiring layer 4 and the first interlayer insulating film 7, a cap film 10 for preventing diffusion of Cu from the lower wiring layer 4 to the second interlayer insulating film 8.
Is deposited. A cap film 11 is similarly formed on the upper surfaces of the upper wiring layer 5 and the third interlayer insulating film 9. A Cu diffusion prevention insulating film 12 is formed on the bottom of the upper wiring layer 5.

In order to prevent Cu, which is a wiring material, from diffusing into the interlayer insulating film, the bottom and side walls of the lower wiring layer 4, the vias 6 and the side walls of the upper wiring layer 5 have a Cu diffusion preventing function. It is covered with a barrier metal 13.

In the semiconductor device 61 of the present invention, as described above, the wiring material Cu is formed between the via 6 and the lower wiring layer 4.
Are in a movable state. That is, unlike the conventional semiconductor device having a multilayer wiring structure in which the via and the lower wiring layer are joined via a different metal such as a barrier metal, the semiconductor device 61 of the present invention has the barrier metal 13 at the bottom of the via 6. Is not present, the via 6 and the lower wiring layer 4 are directly joined.

Furthermore, in the semiconductor device 61 of the fourth example,
C is formed on the surface of the first interlayer insulating film 7 in which the lower wiring layer 4 is embedded.
The u diffusion prevention insulating film 18 is added. That is, the Cu diffusion prevention insulating film 18 is always interposed between the first interlayer insulating film 7 and the second interlayer insulating film 8, and this prevents the diffusion of Cu from the via 6.

By allowing Cu to move between the via 6 and the lower wiring layer 4, the discontinuity of the flow of Cu atoms from the via 6 to the lower wiring layer 4 is eliminated, and the electromigration resistance is improved. To do.

Further, in this semiconductor device 61, the barrier metal 13 between the via 6 and the lower wiring layer 4 does not exist at all, or the amount thereof is extremely reduced, so that the barrier having a larger resistance than Cu. It is also possible to obtain the effect of suppressing an increase in via resistance due to the metal 13.

As described above, the semiconductor device 61 of the present invention.
Shows high reliability due to improved electromigration resistance, and at the same time realizes reduction of wiring resistance.

Further, in the semiconductor device 61, the Cu diffusion preventing insulating film 18 avoids the direct contact between the via 6 and the first interlayer insulating film 7 even if the interlayer displacement occurs. , Cu of the via 6 can be surely prevented from diffusing into the first interlayer insulating film 7.

As the Cu diffusion prevention insulating film 18, SiC is used.
An insulating material having a high barrier property against Cu, such as SiN or SiN, can be used.

Next, a method for manufacturing the semiconductor device 61 of the fourth example shown in FIG. 24 described above by the dual damascene method will be described with reference to FIGS.

First, as shown in FIG. 25, the etch stopper film 3 is formed on the substrate 2 by, eg, CVD method.
As an example, the etch stopper film 3 made of SiC was formed to a film thickness of 50 nm.

Next, as shown in FIG. 26, the first interlayer insulating film 7 and the Cu diffusion preventing insulating film 18 are formed in this order in succession to the formation of the etch stopper film 3 without exposing to the atmosphere. . When forming the first interlayer insulating film 7, CVD is used.
Method, trimethylsilane and N ₂ O were used as source gases, and SiOC was deposited to a thickness of 450 nm. When forming the Cu diffusion prevention insulating film 18, trimethylsilane and NH ₃ are used as source gases by the CVD method, and SiC is used.
Was deposited to a thickness of 50 nm.

Next, as shown in FIG. 27, Cu is buried in the first interlayer insulating film 7 and the Cu diffusion preventing insulating film 18 by, for example, the damascene method to form the lower wiring layer 4.

Specifically, first, a trench for forming the lower wiring layer 4 is patterned by photolithography and dry etching.

Next, in order to prevent Cu from diffusing into the first interlayer insulating film 7, the barrier metal 13 is formed by PVD or CV.
A film is formed by the D method or the like. As an example, a barrier metal 13 made of TaN was formed to a thickness of 20 nm by the PVD method. The film forming conditions are shown below.

[0112]Barrier metal deposition conditions DC power: 1 kW Process gas: Ar = 50 sccm AC wafer bias power: 500W

Following the film formation of the barrier metal 13,
A Cu seed layer (not shown) is formed. As an example, the Cu seed layer 16 having a film thickness of 160 n is formed by the PVD method.
The film was formed at m. The film forming conditions are shown below.

[0114]Cu seed layer deposition conditions DC power: 12kW Pressure: 0.1Pa Film formation temperature: -20 ° C

Next, Cu is filled in the trench by electrolytic plating. As an example, Cu was deposited at a deposition amount of 1 μm. The film forming conditions were the same as the electrolytic plating conditions of the first example described above.

Next, CMP is performed to form Cu only in the trench.
And the lower wiring layer 4 is formed. The CMP conditions were the same as in the first example described above.

Finally, the cap film 1 made of, for example, SiC is formed on the surfaces of the lower wiring layer 4 and the Cu diffusion prevention insulating film 18.
By depositing 0 by the CVD method, the wiring structure of the first layer as shown in FIG. 27 is obtained. The film thickness of the cap film 10 can be set to, for example, 50 nm.

When the same material is used for the Cu diffusion prevention insulating film 18 and the cap film 10, the Cu diffusion prevention insulating film 18 and the cap film 10 are integrated, but in the present invention, Will also be included.

Next, as shown in FIG. 28, the cap film 1
On the upper surface of 0, the second interlayer insulating film 8, the Cu diffusion preventing insulating film 12, the third interlayer insulating film 9, the hard mask for forming the dual damascene structure and the Cu diffusion preventing insulating film 19 are formed.
Are sequentially formed in this order by the CVD method. As an example, the second interlayer insulating film 8 made of SiOC has a film thickness of 450.
nm, Cu diffusion prevention insulating film 12 with a film thickness of 50 nm, SiO
The third interlayer insulating film 9 made of C is formed to have a film thickness of 400 nm and Si
An insulating film 19 made of C was formed to a film thickness of 100 nm.

Next, as shown in FIG. 29, the insulating film 19 is patterned by photolithography and dry etching to form a hard mask 19a for forming the trench 15 in the upper layer. Here, the uppermost layer of SiC
Was dry-etched by 100 nm.

Next, as shown in FIG. 30, a photoresist is newly patterned to form a resist mask 62 for forming a via hole, and the third interlayer insulating film 19 and the Cu diffusion preventing insulating film 12 are dried. Etching.

Next, the resist mask 62 is removed, and FIG.
As shown in FIG. 1, the second interlayer insulating film 8 is dry-etched using the previously formed hard mask 19a to form the via hole 14 and the trench 15.

Next, as shown in FIG. 32, trench 15
The bottom cap film 10 is removed by dry etching to expose the surface of the lower wiring layer 4.

Next, as shown in FIG. 33, in order to prevent Cu from diffusing into the interlayer insulating film, the barrier metal 13 is doped with P.
The film is formed by the VD method or the CVD method. As an example, Ta
The barrier metal 13 made of N is formed into a film thickness of 20 by the PVD method.
The film was formed at a thickness of nm. The film forming conditions of the barrier metal 13 by the PVD method here are different from the film forming conditions of the barrier metal 13 of the lower wiring layer 4 described above, and are set to increase the resputtering component. By this resputtering, the barrier metal 13 at the bottom of the via hole 14 is removed and reattached to the side wall, thereby creating a state in which the barrier metal 13 is not formed only on the bottom of the via hole 14 as shown in FIG.

Next, a Cu seed layer (not shown) for electrolytic plating was formed to a film thickness of 150 nm by the PVD method, for example.

Next, Cu is embedded in the via hole 14 and the trench 15 by electrolytic plating, and the excess Cu and the barrier metal 13 are removed by CMP to form the via 6 and the upper wiring layer 5. Finally, a cap film 11 made of, for example, SiC is formed on the entire surfaces of the upper wiring layer 5 and the third interlayer insulating film 9 by the CVD method, so that the semiconductor device 61 having the two-layer wiring as shown in FIG. can get. The film thickness of the cap film 11 can be set to 50 nm, for example.

According to the method of manufacturing the semiconductor device 61 as described above, the first interlayer insulating film 7 is used when manufacturing the multilayer wiring in which the Cu atoms can move between the via 6 and the lower wiring layer 4. Since the Cu diffusion preventing insulating film 18 is formed on the upper layer and the lower wiring layer 4 is embedded thereafter, the Cu diffusion preventing insulating film 18 is not separated from the via 6 and the first interlayer insulating layer even when the interlayer position shift occurs. By avoiding direct contact with the film 7, it is possible to manufacture the semiconductor device 61 that can reliably prevent Cu from diffusing from the via 6 to the first interlayer insulating film 7.

Next, a manufacturing apparatus for manufacturing a semiconductor device having a multi-layer wiring structure in which atoms of a wiring material can be moved between the via and the wiring layer existing therebelow as described above , FIG. 34 will be described in detail.

In this semiconductor manufacturing apparatus 70, a physical etching chamber 72, a barrier metal film forming chamber 73, a low pressure dry etching chamber 74, and a Cu seed layer film forming chamber 75 are arranged around a core chamber 71. Has been done. Further, the semiconductor manufacturing apparatus 70 is provided with a first load lock chamber 76 and a second load lock chamber 77 around the core chamber 71 for loading / unloading and degassing a wafer to be processed. There is. Since the semiconductor manufacturing apparatus 70 is provided with each chamber in the same apparatus, it is possible to carry in and carry in a wafer, which is an object to be processed, and perform continuous processing without opening to the atmosphere.

The core chamber 71 is equipped with a transfer device (not shown) capable of carrying the wafer in and out of each chamber.

The physical etching chamber 72 is a chamber for removing a natural oxide film formed on the surface of the lower wiring layer using Cu as a wiring material, and is an etching chamber using ICP or the like.

The barrier metal film forming chamber 73 is made of Ta,
Cu such as TaN, W, WN, Ti, TiN, TiSiN
It is a chamber for forming a metal thin film having a high barrier property against. The barrier metal film forming chamber 73 is, for example, a sputtering chamber or a CVD chamber.

The low pressure dry etching chamber 74 is
This is a chamber for removing the barrier metal at the bottom of the via hole by etching using high-density plasma such as ICP, ECR, and MERIE. In the low pressure dry etching chamber 74, NF ₃ as an etching gas,
Fluorine-based gas such as SF ₃ can be used. When the low-pressure dry etching chamber 74 is an etching chamber using ICP, as shown in FIG. 5, a substrate holder 78 for holding a wafer in the chamber (not shown), and high frequency power is supplied to the substrate holder 78. It is preferable to provide a high frequency power supply 79 for applying the voltage. With such a structure, anisotropic etching can be performed in which high-frequency power is applied to the wafer to generate a bias and the ions in the plasma are vertically attracted to the wafer.

The Cu seed layer deposition chamber 75 is a chamber for depositing a Cu seed layer, and is a sputtering chamber or a CVD chamber.

First load lock chamber 76 and second
The load lock chamber 77 is a preliminary vacuum chamber for loading / unloading the wafer to / from the semiconductor manufacturing apparatus 70 without returning the chambers such as the core chamber 71 to the atmospheric pressure. Also,
The first load lock chamber 76 and the second load lock chamber 77 have an exhaust function and a degas function for removing the gas adsorbed on the wafer.

A method of actually manufacturing the semiconductor device 21 of the second example shown in FIG. 9 using the semiconductor manufacturing apparatus 70 having the above-described structure will be described with reference to FIGS. 10 to 15. In addition, the following series of steps shall be continuously performed without exposing each chamber to the atmosphere.

First, the substrate 2 (hereinafter referred to as a wafer) having a dual damascene structure as shown in FIG. 10 is introduced into the first load lock chamber 76 and exhausted to bring it into a predetermined depressurized state. At the same time, degassing for removing gas such as moisture adsorbed on the wafer is performed. The degas conditions were 350 ° C. and 60 seconds.

Next, the degassed wafer is carried from the first load lock chamber 76 and carried into the physical etching chamber 72 via the core chamber 71. The physical etching chamber 72 is, for example, an ICP sputtering chamber. Here, the Cu natural oxide film formed on the surface of the lower wiring layer 4 exposed at the bottom of the via hole 14 is removed. The etching amount required to remove the natural oxide film is about 5 μm to 10 μm.

Next, the wafer is transferred from the first load lock chamber 76 and loaded into the barrier metal film forming chamber 73 via the core chamber 71. The barrier metal film forming chamber 73 is, for example, a PVD chamber. By depositing the barrier metal 13 under the same conditions as when manufacturing the semiconductor device 21 of the second example, the wafer in the state shown in FIG. 11 is obtained.

Next, the wafer is carried from the barrier metal film forming chamber 73 and carried into the low pressure dry etching chamber 74 via the core chamber 71. The low-pressure dry etching chamber 74 is a low-pressure dry etching chamber using ICP, for example. By performing etching in the low pressure dry etching chamber 74 under the same conditions as those for manufacturing the semiconductor device 21 of the second example,
As shown in FIG. 12, the barrier metal 13 at the bottom of the via hole 14 is removed.

Next, the wafer is transferred from the low-pressure dry etching chamber 74 and passed through the core chamber 71 to the C
It is carried into the u seed layer film forming chamber 75. The Cu seed layer deposition chamber 75 is, for example, a PVD chamber. C under the same conditions as those for manufacturing the semiconductor device 21 of the second example.
By forming the u seed layer 16, a wafer as shown in FIG. 13 is obtained.

The wafer on which the Cu seed layer 16 is formed is C
It is carried out from the u seed layer film forming chamber 75 and then carried into the second load lock chamber 77 via the core chamber 71. After returning the load lock chamber 77 to the atmospheric pressure, the wafer is taken out, and the processing in the semiconductor manufacturing apparatus 70 is completed. After that, a Cu embedding step, a CMP step, a cap film forming step, and the like are performed to complete the semiconductor device 21 of the second example of the present invention as shown in FIG.

By using the semiconductor manufacturing apparatus 70 as described above, a semiconductor device having a multilayer wiring in which atoms of the wiring material are made movable between the via and the wiring layer existing thereunder is manufactured. At this time, it is possible to continuously perform processing from the step of removing the natural oxide film of the lower wiring layer to the step of forming the Cu seed layer without returning to atmospheric pressure in one device.
Therefore, it becomes possible to form a Cu seed layer having good adhesion, and the reliability of the semiconductor device can be improved.

In the above description, the case where the semiconductor device 21 of the second example is manufactured has been described as an example, but the present invention is not limited to this. It is possible to manufacture all kinds of semiconductor devices having multi-layer wiring in which atoms of the wiring material can be moved between the wiring layer and the wiring layer existing in.

[0145]

As is apparent from the above description, in the method of manufacturing the semiconductor device according to the first example of the present invention, the barrier metal formed on the bottom of the via hole is preferentially formed in the barrier metal removing step. Since the barrier metal at the bottom of the trench is removed and remains, the characteristics of the barrier metal are not impaired, and the barrier metal does not exist between the first wiring layer and the via. The atomic flow becomes continuous,
It does not cause an increase in via resistance. Therefore,
According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that realizes higher speed and higher reliability.

In the method of manufacturing a semiconductor device according to the second example of the present invention, the barrier metal is formed while the insulating film having the wiring material diffusion preventing function is left at the bottom of the trench. Even if the barrier metal at the bottom of the trench is completely removed in the same manner as the barrier metal at the bottom of the via hole in the metal removing step, diffusion of the wiring material into the interlayer insulating film can be prevented. Therefore, since the barrier metal does not exist between the first wiring layer and the via without impairing the characteristics of the barrier metal, the flow of wiring material atoms due to electromigration becomes continuous, and It does not cause an increase in via resistance. Therefore, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that realizes higher speed and higher reliability.

In the method of manufacturing a semiconductor device according to the third example of the present invention, the insulating film having the wiring material diffusion preventing function is left at the bottom of the via hole while the insulating film having the wiring material diffusion preventing function is left. The barrier metal film is formed while controlling the conditions so that the barrier metal does not accumulate on top.
After that, the insulating film having a wiring material diffusion preventing function at the bottom of the via hole is removed by etching to expose the first wiring layer. Therefore, since the barrier metal does not exist between the first wiring layer and the via without impairing the characteristics of the barrier metal, the flow of wiring material atoms due to electromigration becomes continuous, and It does not cause an increase in via resistance. Therefore, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that realizes higher speed and higher reliability.

Further, in the semiconductor device and the manufacturing method thereof according to the fourth example of the present invention, since the via is formed so that the wiring material can be moved between the via and the first wiring layer, It is possible to suppress the generation of voids that occur at the interface between the via and the first wiring layer due to electromigration when a current is applied, and it is possible to improve electromigration resistance. Furthermore, a laminated film of a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function is formed, and a wiring material is embedded therein to form a first wiring layer, and then a via and a second wiring layer. Therefore, it is possible to manufacture the semiconductor device capable of reliably preventing the diffusion of the wiring material into the first interlayer insulating film even when the interlayer displacement occurs between the via and the first wiring layer. Therefore, according to the present invention, it is possible to provide a semiconductor device that achieves higher speed and higher reliability. Further, even when an interlayer displacement occurs in the wiring structure in which the wiring material is movable between the bottom of the via and the first wiring layer, the diffusion of the wiring material into the first interlayer insulating film is ensured. It can be prevented.

Further, in the semiconductor device manufacturing apparatus according to the present invention, after the first wiring layer is formed, the object to be processed can be carried in and out without exposing each chamber to the atmosphere until the Cu seed layer is formed. To be realized. Therefore, according to the present invention, it is possible to provide a semiconductor manufacturing apparatus capable of forming a Cu seed layer having good adhesion and capable of manufacturing a highly reliable semiconductor device.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a first example of a semiconductor device to which the present invention is applied.

FIG. 2 is a schematic cross-sectional view showing a dual damascene structure forming step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 3 is a schematic cross-sectional view showing a barrier metal film forming step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 4 is a schematic cross-sectional view showing a barrier metal removing step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 5 is a schematic view showing anisotropic etching for removing a barrier metal.

FIG. 6 is a schematic cross-sectional view showing a Cu seed layer forming step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 7 is a schematic cross-sectional view showing a Cu filling step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 8 is a schematic cross-sectional view showing a CMP polishing step, which is a wiring forming process in the semiconductor device of the first example.

FIG. 9 is a schematic sectional view showing a second example of a semiconductor device to which the invention is applied.

FIG. 10 is a schematic cross-sectional view showing a wiring forming process in the semiconductor device of the second example, showing a dual damascene structure forming step.

FIG. 11 is a schematic cross-sectional view showing a barrier metal film forming step, which is a wiring forming process in the semiconductor device of the second example.

FIG. 12 is a schematic cross-sectional view showing a barrier metal removing step, which is a wiring forming process in the semiconductor device of the second example.

FIG. 13 is a schematic cross-sectional view showing a wiring forming process in the semiconductor device of the second example, which shows a Cu seed layer forming step.

FIG. 14 is a schematic cross-sectional view showing a Cu filling step, which is a wiring forming process in the semiconductor device of the second example.

FIG. 15 is a schematic cross-sectional view showing a CMP polishing step, which is a wiring forming process in the semiconductor device of the second example.

FIG. 16 is a schematic sectional view showing a third example of a semiconductor device to which the invention is applied.

FIG. 17 is a schematic cross-sectional view showing a wiring forming process in the semiconductor device of the third example, showing a dual damascene structure forming step.

FIG. 18 is a schematic cross-sectional view showing a barrier metal film forming step, which is a wiring forming process in the semiconductor device of the third example.

FIG. 19 is a schematic cross-sectional view showing the cap film removing step in the wiring forming process in the semiconductor device of the third example.

FIG. 20 is a schematic cross-sectional view showing a Cu filling step, which is a wiring forming process in the semiconductor device of the third example.

FIG. 21 is a schematic cross-sectional view showing a CMP polishing step, which is a wiring forming process in the semiconductor device of the third example.

FIG. 22 is a schematic cross-sectional view showing a case where interlayer misalignment occurs in the semiconductor device to which the present invention is applied.

FIG. 23 is a schematic cross-sectional view showing a case where an interlayer displacement occurs in a conventional semiconductor device.

FIG. 24 is a schematic sectional view showing a fourth example of a semiconductor device to which the present invention has been applied.

FIG. 25 is a schematic cross-sectional view showing an etch stopper film forming step, which is a wiring forming process in the semiconductor device of the fourth example.

FIG. 26 is a schematic cross-sectional view showing the wiring forming process in the semiconductor device of the fourth example, showing the interlayer insulating film forming step for the lower wiring layer.

FIG. 27 is a schematic cross-sectional view showing the lower wiring layer forming step in the wiring forming process in the semiconductor device of the fourth example.

FIG. 28 is a schematic cross-sectional view showing the wiring forming process in the semiconductor device of the fourth example, showing the step of forming the via and the interlayer insulating film for the upper wiring.

FIG. 29 is a schematic cross-sectional view showing a hard mask forming step, which is a wiring forming process in the semiconductor device of the fourth example.

FIG. 30 is a schematic cross-sectional view showing a resist mask forming step which is a wiring forming process in the semiconductor device of the fourth example.

FIG. 31 is a schematic cross-sectional view showing a step of forming a via hole and a trench, which is a wiring forming process in the semiconductor device of the fourth example.

FIG. 32 is a schematic cross-sectional view showing the cap film removing step in the wiring forming process in the semiconductor device of the fourth example.

FIG. 33 is a schematic cross-sectional view showing a barrier metal film forming step, which is a wiring forming process in the semiconductor device of the fourth example.

FIG. 34 is a plan view showing a semiconductor manufacturing apparatus of the present invention.

FIG. 35 is a schematic cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

1,21,31,41,51,61 Semiconductor device 2 substrates 3 Etch stopper film 4 Lower wiring layer 5 Upper wiring layer 6 beer 7 First interlayer insulating film 8 Second interlayer insulating film 9 Third interlayer insulating film 10 Cap film 11 Cap film 12 Cu diffusion prevention insulating film 13 Barrier metal 14 beer hall 15 trench 16 Cu seed layer 18 Cu diffusion prevention insulating film 70 Semiconductor manufacturing equipment 71 Core chamber 72 Physical Etching Chamber 73 Barrier metal deposition chamber 74 Low Pressure Dry Etching Chamber 75 Cu seed layer deposition chamber 76 First Load Lock Chamber 77 Second Load Lock Chamber

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kaori Tai             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Takeshi Nogami             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Hiroshi Horikoshi             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Naoki Komai             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 5F033 HH11 HH18 HH19 HH21 HH27                       HH32 HH33 HH34 JJ01 JJ11                       JJ18 JJ19 JJ21 JJ27 JJ32                       JJ33 JJ34 KK11 KK18 KK19                       KK21 KK27 KK32 KK33 KK34                       MM01 MM02 MM12 MM13 NN05                       NN06 NN07 PP06 PP14 PP27                       QQ09 QQ10 QQ11 QQ12 QQ13                       QQ25 QQ28 QQ35 QQ37 QQ48                       QQ50 QQ98 RR01 RR04 RR06                       RR11 RR21 SS03 SS11 TT02                       TT04 WW00 XX05 XX09 XX10                       XX15 XX23 XX28

Claims (51)

[Claims] 1. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising forming a second interlayer insulating film on a first wiring layer in which a wiring material is embedded in the first interlayer insulating film. A barrier metal film forming step of forming a concave portion including a trench and a via hole in the second interlayer insulating film and forming a barrier metal film in the concave portion; and a barrier metal removing at least the barrier metal at the bottom of the via hole by etching. A removing step, wherein the barrier metal at the bottom of the second wiring trench is left in the barrier metal removing step. 2. In the barrier metal deposition step, the thickness of the barrier metal deposited on the bottom of the via hole is 60% or less of the thickness of the barrier metal deposited on the bottom of the trench, and 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the barrier metal removing step, the ratio of the etching rate at the bottom of the via hole to the etching rate at the bottom of the trench is set to 80% or more. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the wiring material contains Cu. 4. The barrier metal does not exist between the first wiring layer and the via.
A method for manufacturing a semiconductor device as described above. 5. The barrier metal is Ta, TaN,
The method for manufacturing a semiconductor device according to claim 1, wherein the method is at least one selected from W, WN, Ti, TiN, and TiSiN. 6. The method of manufacturing a semiconductor device according to claim 1, wherein low pressure dry etching using high density plasma is performed in the barrier metal removing step. 7. The semiconductor according to claim 6, wherein in the barrier metal removing step, any one of inductively coupled plasma etching, electron cyclotron resonance etching, and reactive ion etching to which a magnetic field is applied is performed. Device manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 6, wherein a fluorine-based gas is used as an etching gas in the barrier metal removing step. 9. The semiconductor according to claim 6, wherein in the barrier metal removing step, high frequency power is applied to the object to be processed to generate a bias, ions in the plasma are controlled, and anisotropic etching is performed. Device manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 1, further comprising a Cu seed layer forming step of forming a Cu seed layer in the recess after the barrier metal removing step. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the barrier metal film forming step, the barrier metal removing step, and the Cu seed layer film forming step are successively performed without exposing to the atmosphere. Method. 12. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising: a second interlayer insulating film and a wiring on a first wiring layer in which a wiring material is embedded in the first interlayer insulating film. An insulating film having a material diffusion preventing function and a third interlayer insulating film are formed in this order to form a concave portion including a trench and a via hole,
There is a barrier metal film forming step of forming a barrier metal film in the concave portion and a barrier metal removing step of removing at least the barrier metal at the bottom of the via hole by etching, and in the barrier metal removing step, at the bottom of the trench. A method of manufacturing a semiconductor device, characterized in that the insulating film having a wiring material diffusion preventing function is left. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the insulating film having a wiring material diffusion preventing function is made of SiC or SiN. 14. The method of manufacturing a semiconductor device according to claim 12, wherein the wiring material contains Cu. 15. The method of manufacturing a semiconductor device according to claim 12, wherein the barrier metal does not exist between the first wiring layer and the via. 16. The barrier metal is Ta, TaN,
13. The method for manufacturing a semiconductor device according to claim 12, wherein the method is at least one selected from W, WN, Ti, TiN, and TiSiN. 17. In the barrier metal removing step,
13. The method of manufacturing a semiconductor device according to claim 12, wherein low-pressure dry etching using high-density plasma is performed. 18. In the barrier metal removing step,
18. The method of manufacturing a semiconductor device according to claim 17, wherein any one of inductively coupled plasma etching, electron cyclotron resonance etching, and reactive ion etching applied with a magnetic field is performed. 19. In the barrier metal removing step,
18. The method of manufacturing a semiconductor device according to claim 17, wherein a fluorine-based gas is used as the etching gas. 20. In the barrier metal removing step,
18. The method of manufacturing a semiconductor device according to claim 17, wherein a high frequency power is applied to the object to be processed to generate a bias, and ions in the plasma are controlled to perform anisotropic etching. 21. The method of manufacturing a semiconductor device according to claim 12, further comprising a Cu seed layer forming step of forming a Cu seed layer in the recess after the barrier metal removing step. 22. The manufacturing of a semiconductor device according to claim 21, wherein the barrier metal film forming step, the barrier metal removing step, and the Cu seed layer film forming step are successively performed without exposing to the atmosphere. Method. 23. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising: an insulating film having a wiring material diffusion preventing function on a first wiring layer in which a wiring material is embedded in a first interlayer insulating film. And a second interlayer insulating film in this order, and a recess forming step of forming a recess composed of a trench and a via hole in the insulating film having the wiring material diffusion preventing function and the second interlayer insulating film, and the via hole A barrier metal film forming step of forming a barrier metal in the recess so that the insulating film having the wiring material diffusion preventing function at the bottom is not covered, and the insulating film having the wiring material diffusion preventing function at the bottom of the via hole is etched. And a step of removing the insulating film by means of the method described above. 24. In the barrier metal film forming step,
Before the barrier metal film formation is started on the insulating film having the wiring material diffusion preventing function exposed at the bottom of the via hole, the thickness of the barrier metal film on the second interlayer insulating film is set to 3 nm. The method of manufacturing a semiconductor device according to claim 23, wherein 25. The method of manufacturing a semiconductor device according to claim 23, wherein the insulating film having a wiring material diffusion preventing function is SiC or SiN. 26. The method of manufacturing a semiconductor device according to claim 23, wherein the second interlayer insulating film is made of SiO ₂ or SiOC. 27. The method of manufacturing a semiconductor device according to claim 23, wherein the wiring material contains Cu. 28. The barrier metal is not present between the first wiring layer and the via.
A method for manufacturing a semiconductor device as described above. 29. The barrier metal is Ta, TaN,
24. The method of manufacturing a semiconductor device according to claim 23, which is at least one selected from W, WN, Ti, TiN, and TiSiN. 30. A semiconductor device having a multilayer wiring structure, comprising: a first wiring layer in which a wiring material is embedded in a laminated film of a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function. A second wiring layer disposed above the first wiring layer, and a via electrically connecting the first wiring layer and the second wiring layer to each other, A semiconductor device, wherein the wiring layer and the via are embedded in a second interlayer insulating film via a barrier metal. 31. The semiconductor device according to claim 30, wherein the insulating film having a wiring material diffusion preventing function is SiC or SiN. 32. The semiconductor device according to claim 30, wherein the wiring material contains Cu. 33. The semiconductor device according to claim 30, wherein the barrier metal does not exist between the first wiring layer and the via. 34. The barrier metal is Ta, TaN,
31. The semiconductor device according to claim 30, wherein the semiconductor device is at least one selected from W, WN, Ti, TiN, and TiSiN. 35. A method of manufacturing a semiconductor device having a multi-layer wiring structure, comprising: forming a laminated film by forming a first interlayer insulating film and an insulating film having a wiring material diffusion preventing function in this order; A first wiring layer forming step of forming a first wiring layer by embedding a wiring material in the laminated film; and forming a second interlayer insulating film on the first wiring layer, and forming a second interlayer insulating film on the second interlayer insulating film. A barrier metal film forming step of forming a concave portion including a trench and a via hole, and forming a barrier metal film in the concave portion; and a barrier metal removing step of removing at least the barrier metal at the bottom of the via hole by etching. Of manufacturing a semiconductor device. 36. The method of manufacturing a semiconductor device according to claim 35, wherein the insulating film having a wiring material diffusion preventing function is SiC or SiN. 37. The method of manufacturing a semiconductor device according to claim 35, wherein the wiring material contains Cu. 38. The method of manufacturing a semiconductor device according to claim 35, wherein the barrier metal does not exist between the first wiring layer and the via. 39. The barrier metal is Ta, TaN,
36. The method for manufacturing a semiconductor device according to claim 35, wherein the method is at least one selected from W, WN, Ti, TiN, and TiSiN. 40. A multi-layer structure in which atoms of a wiring material are made movable between the via and a wiring layer existing thereunder, and the wiring material is embedded in an interlayer insulating film through a barrier metal. A manufacturing apparatus of a semiconductor device having a wiring structure, comprising: a physical etching chamber for removing a natural oxide film on the wiring layer; a barrier metal deposition chamber for depositing the barrier metal; A dry etching chamber for removing metal, a Cu seed layer deposition chamber for depositing a Cu seed layer, and a core chamber capable of continuously treating a target object without exposing each chamber to the atmosphere An apparatus for manufacturing a semiconductor device. 41. The semiconductor device manufacturing apparatus according to claim 40, wherein the physical etching chamber performs inductively coupled plasma etching. 42. The semiconductor device manufacturing apparatus according to claim 40, wherein the barrier metal film forming chamber performs sputtering or chemical vapor deposition. 43. The barrier metal film forming chamber comprises Ta, TaN, W, WN, Ti as the barrier metal.
The device for manufacturing a semiconductor device according to claim 40, wherein at least one selected from TiN and TiSiN is formed on the object to be processed. 44. The semiconductor device manufacturing apparatus according to claim 40, wherein the dry etching chamber performs low pressure dry etching using high density plasma. 45. The semiconductor device according to claim 44, wherein the dry etching chamber performs any one of inductively coupled plasma etching, electron cyclotron resonance etching, and reactive ion etching in which a magnetic field is applied. Manufacturing equipment. 46. The dry etching chamber can use a fluorine-based gas.
0. A semiconductor device manufacturing apparatus according to item 0. 47. The fluorine-based gas is NF ₃ or SF
47. The semiconductor device manufacturing apparatus according to claim 46, which is at least one of the _three . 48. The apparatus for manufacturing a semiconductor device according to claim 40, wherein the dry etching chamber comprises a substrate holder for holding an object to be processed, and a high frequency power source for applying high frequency power to the substrate holder. . 49. The semiconductor device manufacturing apparatus according to claim 40, wherein the Cu seed layer deposition chamber performs sputtering or chemical vapor deposition. 50. The semiconductor device manufacturing apparatus according to claim 40, further comprising a load lock chamber capable of loading and unloading an object to be processed into the core chamber without returning to atmospheric pressure. 51. The semiconductor device manufacturing apparatus according to claim 50, wherein the load lock chamber has a degassing function capable of removing an adsorbed gas on the object to be processed.