JP2003257198A - Semiconductor memory defect analysis display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate defect analysis of a semiconductor memory by performing a probe test for wafer and a chip test for single chip. <P>SOLUTION: A semiconductor memory defect analysis display system is provided with a semiconductor memory test device 140 in which a probe test device 140 performing a test at a wafer level or a chip test device 150 performing a test at a chip level can be selected, and a semiconductor memory defect analysis device 100 having a function 101 recognizing the semiconductor memory test device performing a test selected by the semiconductor memory test device, a function 102 taking in test result data from the semiconductor memory test device, a function 104 performing elimination of defective information from the test result data, and a function 106 preparing display information for editing defective information. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory failure analysis display system.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing the configuration of a conventional semiconductor memory failure analysis display system. In FIG. 2, the semiconductor memory failure analysis display system includes a memory failure analysis apparatus 200, a probe test apparatus 240, and a probe test apparatus 2.
Database 25 of test result data output from 40
A file server 210 storing 0, a display terminal device 22
0, a network 230 connecting them.

The memory failure analysis apparatus 200 has a function 201 of taking in probing test result data of a semiconductor memory completed on a semiconductor wafer, a function 202 of cutting out failure information from the test result data, and a function of memory cell. It has a function 203 of converting defect information into two-dimensional address information according to a display program to create a fail bitmap image file, and a function 204 of creating a display control command for displaying this image file as a character file.

[0004]

However, in the above-mentioned conventional semiconductor memory failure analysis display system, only the probe test for testing the wafer is targeted, and the chip inspection for testing the single chip after the burn-in inspection cannot be carried out. Therefore, failure analysis of a single chip cannot be performed.

Further, the representation of the test result data differs depending on the test method and the memory test circuit used, and therefore the failure analysis apparatus must be prepared for each test apparatus or each test method. There is a risk that the number of man-hours will increase in order to support a wide variety of test equipment that is expected to increase in the future.

Further, the test result data in which all the bits are defective is collected and analyzed as data in the defect analysis despite the cause of the contact failure or the failure of other functions, so that the failure occurs. The data that should show the tendency of will become unclear and hinder accurate judgment. Further, if such defective data is stored in the database, there is a problem that the capacity of the database is wasted as the number of samples increases.

The present invention has been made in order to solve the above-mentioned conventional problems, and can be applied not only to a probe test for testing a wafer but also to a chip test for testing a single chip. The purpose is to provide a system.

Another object of the present invention is to provide a method for unifying test result data of different formats depending on the test apparatus or test method. A further object of the present invention is to provide a method for excluding test result data in which all bits are defective from the database.

[0009]

In order to solve this problem, a semiconductor memory failure analysis display system according to claim 1 of the present invention comprises at least one semiconductor memory test device,
Semiconductor memory failure analysis apparatus (memory failure analysis apparatus 10
0), test result file device (file server 110)
A semiconductor memory failure analysis display system having a display device (display terminal device 120), the semiconductor memory test device including a probe test (probe test device 140) for performing a test at a wafer level and a chip for performing a test at a chip level. A test (chip test apparatus 150) can be selected, and the semiconductor memory failure analysis apparatus recognizes the test selected by the semiconductor memory test apparatus and the semiconductor memory test apparatus that executes the selected test (10
1), a function (102) for taking in the test result data from the semiconductor memory test device, a function (104) for cutting out defect information from the test result data, and a function for editing the defect information to the display device. And a function (106) for creating display information for display.

According to the above configuration, the probe test for testing the wafer and the chip test for testing the single chip can be selected, so that the test can be performed not only on the wafer but also on the single chip. Also, since it has a function of recognizing the selected test or the semiconductor memory test device that selected the test, depending on the semiconductor memory test device used,
In addition, depending on whether the test to be performed is at the wafer level or the chip level, the test result data is appropriately processed to create a fail bit map, and by displaying this, the failure tendency can be efficiently judged. it can.

A semiconductor memory failure analysis display system according to a second aspect of the present invention is the semiconductor memory failure analysis display system according to the first aspect, wherein the semiconductor memory failure analysis apparatus uses a test method executed by a semiconductor memory test apparatus. It has a recognition function.

According to the above configuration, in addition to the function of recognizing the selected test or the selected semiconductor memory test device, various different test methods can be identified by the program and the memory test circuit used in the test device. By providing the recognition function, it is possible to appropriately process the test result data output in different formats depending on the respective test devices and test methods to create the fail bit map.

The semiconductor memory failure analysis display system according to claim 3 of the present invention is the semiconductor memory failure analysis display system according to claim 1 or 2, wherein the semiconductor memory failure analysis device is selected by the semiconductor memory test device. It is equipped with a filter program that converts test result data in a format unique to the conducted test into data in a unified format.

According to the above configuration, the test result data output in different formats by the respective test devices and test methods can be converted into the unified format data by the filter program, so that the subsequent processing can be unified. Therefore, it is not necessary to prepare a failure analysis means for each test device or test method.

A semiconductor memory failure analysis display system according to claim 4 of the present invention is the semiconductor memory failure analysis display system according to any one of claims 1 to 3, wherein the semiconductor memory failure analysis device is provided with test result data. It has a function of determining and separating data due to a specific cause of failure from.

According to the above configuration, from the test result data,
By determining and separating data caused by a specific failure cause such as contact failure, leak failure, function failure other than memory, etc., test result data in which all bits are defective can be excluded from the test result database. In addition, data that hinders accurate judgment in failure analysis can be excluded to prevent an unnecessary increase in database capacity.

A semiconductor memory failure analysis display system according to claim 5 of the present invention is the semiconductor memory failure analysis display system according to any one of claims 1 to 4, wherein a semiconductor memory test device, a semiconductor memory failure analysis device, The test result file device and the display device are connected by a wireless communication network.

According to the above configuration, by configuring the system by the wireless communication network, it becomes easy to frequently change the selection of the semiconductor memory test device and deal with a large number of users, and the semiconductor memory failure analysis display system. The usability of can be further improved.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of a semiconductor memory failure analysis display system according to an embodiment of the present invention. In FIG. 1, a semiconductor memory failure analysis display system includes a memory failure analysis apparatus 100 and a probe test apparatus 1 for testing a semiconductor memory on a semiconductor wafer 170.
40, a chip test device 150 for testing a semiconductor memory on a single chip 180, a probe test device 140 or a file server 110 for storing a database 160 of test result data output from the chip test device 150, a display terminal device 120, Network 13 to connect
It consists of zero.

The memory failure analysis device 100 has a function 101 for recognizing whether the selected semiconductor memory test device is a probe test device or a chip test device and a test method to be executed, and a test by the semiconductor memory test device 140. A function 102 for fetching result data, a function 103 for determining and separating data due to a specific failure cause from the test result data, a function 104 for cutting out failure information from the test result data, and a two-dimensional display of failure information of memory cells according to a display program. It has a function 105 of converting the address information into a fail bit map image file and a function 106 of creating a display control command for displaying the image file as a character file.

Further, the memory failure analysis apparatus 100 is equipped with a filter program for converting the test result data in a format unique to each test output from the probe test apparatus or the chip test apparatus into unified format data.

The operation of the semiconductor memory failure analysis display system configured as above will be described below. For example, when the chip test is selected, the chip test apparatus 150 performs the chip test of the semiconductor memory on the single chip 180, and the output test result data is the file server 11.
0 is stored in the test result database 160.

Similarly, when the probe test is selected, the probe test apparatus 140 performs the probe test of the semiconductor memory on the semiconductor wafer 170, and the output test result data is stored in the test result database 160 on the file server 110. Is stored.

In the memory failure analysis device 100, the function 10
It is recognized by 1 whether the probe test apparatus or the chip test apparatus is selected, the test result data is fetched by the function 102, and the data is judged and separated by the function 103 due to a specific cause of failure.

The function 103 is a function for excluding test result data in which all bits are defective as a factor that interferes with an accurate judgment in the failure analysis, and is caused by a contact failure, a leak failure, a function failure other than the memory, or the like. The cause of failure of the test result data is determined and these data are excluded from the test result database. By doing so, it is possible to prevent an unnecessary increase in the database capacity.

Next, the function 104 cuts out defect information from the test result data. At that time, based on the selection information of the test apparatus and the test method recognized by the function 101, the test result data in the format unique to each test output by the probe test apparatus or the chip test apparatus is unified by the filter program. Convert to.

In the recognition of the test method by the function 101, the program used in the selected test device is analyzed to determine the memory test circuit to be used, so that the output test result data in the proper format is correctly grasped. can do. As a result, even test result data output in different formats depending on the test apparatus and the memory test circuit used can be converted into unified format data.

With respect to the test result data converted into the unified format data by the above processing, the function 105 converts the defect information of the memory cell into the two-dimensional address information to create the fail bit map image file.
6 creates a display control file for displaying this.

In this way, according to the present embodiment,
Not only the probe test for testing a semiconductor wafer but also the chip test for testing a single chip can be targeted.
The semiconductor memory failure analysis can be performed regardless of the wafer level or the chip level, and regardless of the model of the semiconductor memory test apparatus or the memory test circuit used.

In the embodiment of FIG. 1, the semiconductor memory test apparatus is configured so that a probe test apparatus for testing a semiconductor memory on a semiconductor wafer and a chip test apparatus for testing a semiconductor memory on a single chip can be selected. However, instead of this, even if a single semiconductor memory test apparatus capable of selecting a probe test for testing a wafer and a chip test for testing a single chip is used, An equivalent semiconductor memory failure analysis display system can be configured.

In order to further improve the usability of the semiconductor memory failure analysis display system described above, a wireless communication network can be used as a network for connecting the devices constituting the system. By mounting an interface circuit capable of wireless communication on each device and configuring a wireless communication network system, it becomes easy to frequently change the semiconductor memory test device selection and deal with a large number of users.

[0032]

As described above, according to the present invention,
In the semiconductor memory failure analysis, the probe test at the wafer level and the chip test at the chip level can be selected, so that not only the wafer but also the single chip can be tested. By processing the test result data according to the test device and the test method and creating the fail bit map, the failure tendency can be efficiently judged, and the failure analysis of the semiconductor memory can be performed in a short time. That is an excellent effect.

Furthermore, according to the present invention, the test result data output in different formats by the respective test devices and test methods can be converted into the uniform format data by the filter program, so that the subsequent processing is unified. Therefore, it is possible to obtain an excellent effect that it is not necessary to prepare a failure analysis means corresponding to each.

Further, according to the present invention, all the bits are defective by judging and separating from the test result data the data due to a specific defective cause such as a contact defect, a leak defect, a function defect other than the memory, or the like. Since the test result data can be excluded from the database of test results, it is possible to obtain an excellent effect of preventing data that hinders accurate determination in failure analysis and preventing an unnecessary increase in database capacity.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory failure analysis display system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional semiconductor memory failure analysis display system.

[Explanation of symbols]

100, 200 Memory failure analysis apparatus 101 Function for recognizing selected test or test apparatus and test method 102, 201 Function for fetching test result data 103 Function for judging and separating data due to specific failure cause from test result data Function 105 and 203 for cutting out defect information from test result data Function 106 and 204 for creating fail bitmap image file 110 and 210 Function for creating display control file 110 and 210 File server 120 and 220 Display terminal device 130 and 230 Network 140 , 240 Probe test device 150 Chip test device 160, 250 Test result database 170 Semiconductor wafer 180 Single chip

Claims (5)

[Claims] 1. A semiconductor memory failure analysis display system having at least one semiconductor memory test device, semiconductor memory failure analysis device, test result file device, and display device, wherein the semiconductor memory test device performs a test at a wafer level. A probe test to be performed and a chip test to perform a test at a chip level can be selected, and the semiconductor memory failure analysis device recognizes a test selected by the semiconductor memory test device and a semiconductor memory test device that performs the selected test. A function to capture test result data from the semiconductor memory test device, a function to cut out defect information from the test result data, and display information for editing the defect information and displaying it on the display device. And a function for creating a semiconductor memory defect analysis display characterized by having Stem. 2. The semiconductor memory failure analysis display system according to claim 1, wherein the semiconductor memory failure analysis apparatus has a function of recognizing a test method executed by the semiconductor memory test apparatus. 3. The semiconductor memory failure analysis device is equipped with a filter program for converting test result data in a format specific to the selected test output from the semiconductor memory test device into unified data. The semiconductor memory failure analysis display system according to claim 1 or 2. 4. The semiconductor memory failure analysis apparatus according to claim 1, wherein the semiconductor memory failure analysis apparatus has a function of determining and separating data due to a specific failure cause from the test result data. Memory failure analysis display system. 5. The semiconductor memory test device, the semiconductor memory failure analysis device, the test result file device, and the display device are connected by a wireless communication network. The semiconductor memory failure analysis display system described.