JP2003256239A - Method and device for executing operation verification simulation, and its program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high speed and accurate overall and systematic operation verification simulation by preventing malfunction and quickly acquiring processing results. <P>SOLUTION: Object directional structured programming language 'Read() function, Write() function (first function)' is discriminated from 'Monitor<SB>-</SB>Read() function, Monitor<SB>-</SB>Write() function (second function)' to execute simulation. At the time of performing access from a CPU model 101 to a hardware model 107, the first function stored in the hardware model 107 is called. At the time of performing access from a monitor 102 to the hardware 107, the number of processing in the function is made smaller than the first function stored in the hardware model 107, and any processing including the start or end of the hardware model 107 is not executed, and the second function for executing only the reading processing is called. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention verifies the operation of an electronic device in which a control system executes a firmware program to control hardware on a computer or a dedicated device.
The present invention relates to an operation verification simulation execution method, a simulation execution device, and a program.

[0002]

2. Description of the Related Art Conventionally, in electronic devices (for example, printers and facsimiles), control systems (for example, CPU,
A microcomputer, if appropriate, is represented by only a CPU) executes control corresponding to various functions of this electronic device. The CPU executes a firmware program stored in the electronic device and controls it. At the development stage of this type of firmware program, simulation is repeatedly performed in order to confirm the normality of control by this firmware program. This simulation is carried out by a simulator in a computer or a dedicated device (hereinafter, described only as a computer). In this simulator, the CPU and hardware of the electronic device are modeled, the hardware models are combined to create a plurality of states when the actual electronic device operates, and each simulation (appropriately described as partial simulation) Is executed, and an overall and comprehensive operation verification simulation (appropriately described as simulator operation) is performed.

By repeating these simulations, the operation of the electronic device is optimized. In this type of simulation, a trace-type simulator that records execution contents is known. In this trace type simulator, the system clock signal is counted one by one, the simulation progresses while changing the state of each part of the modeled electronic device, and the operation time or the data used during the operation is recorded in a log file. is doing. In addition, by adding a debug function to this simulator, it is possible to set breakpoints in the firmware program that suspend simulator operation on arbitrary firmware program control, and to execute steps in units of the firmware program. It is possible.

Further, when the operation is temporarily stopped, the register information (register value) of each hardware model, the memory model information, and the cache memory information are read and written from the monitor for instructing the operation of the simulator. It can be performed. In this way, the information on the register status of the hardware model, the memory model contents, and the cache memory status at each time can be obtained point by point. That is, the user can know these pieces of information.

The conventional simulator operation will be described below. FIG. 9 is a block diagram showing the configuration of a conventional trace type simulator. In FIG. 9, the trace type simulator includes a CPU model 201 that models a CPU, a monitor 202 that controls the simulator, an address decoder 203, and a cache memory model 204 that models a cache memory inside an electronic device.
A device model unit 20 that models each function of the electronic device
It is composed of 5 and. This device model unit 205
Stores a firmware program executed by the CPU model 201. The device model unit 205 has a memory model 206 that models a memory that is a storage unit of the electronic device, and a plurality of hardware models 207 and 208 that models various functions of the electronic device.

The monitor 202 is a man-machine interface with the user, and has an input operation device, an output device, and a display device (keyboard, printer, CRT / LCD device) to control the simulation execution. This monitor 2
02 executes the following processing. (1) Setting and cancellation of breakpoints in firmware program during simulation execution (2) Start, suspension, end and step execution of simulation (3) Hardware register information, memory model 206, cache memory model 204 and Reading and writing register information (register value) of CPU model 201 (4) Display of assembler code of firmware program executed by CPU model 201

Further, the CPU model 201 and the cache memory model 2 in the trace type simulator shown in FIG.
Each of the simulations from 04 to the hardware models 207 and 208 executes a process described by an object-oriented structured programming language / “C ++” language, and each becomes one “Class”. The models other than the cache memory model 204 and the monitor 202 are connected via the address decoder 203. The cache memory model 204 is
The monitor 202, the CPU model 201, and the cache memory model 204 are directly connected to each other. The hardware models 207 and 208, the memory model 206, and the cache memory model 204 are used for writing these internal memory information and register information, respectively. "Write / Wr
"ite () function" and "read / Read () function" for reading memory information and register information in the model are stored.

FIG. 10 is a flow chart for explaining the conventional simulator operation in FIG. In FIG. 10, when the simulation is started, the hardware models 207, 208, the CPU model 201, etc. are initialized (step S301). After that, the simulator enters a standby state for a user instruction on the monitor 202 (step S302). Next, when the user gives an instruction such as “run (restart)” on the monitor 202,
The simulator is a simulation execution unit (not shown).
(For example, a processing module when a computer is used as a simulator) is called to start (restart) the simulation (step S303).

During the simulation, if the above-mentioned breakpoint is set in the firmware program or the monitor 202 gives an instruction to interrupt the user, the simulation is temporarily interrupted and the monitor 202 waits for an instruction again. . In the monitor 202, the “Write () function” or “Read () function” is called, and in the case of the “Read” instruction, the result is returned to the monitor 202. If the instruction is "end", the simulation ends.

FIG. 11 is a flow chart for explaining the processing contents of the simulation executing section in the simulator shown in FIG. In FIG. 11, the monitor 202
When the simulation execution part is called from, first,
When one system clock signal in the simulator is advanced (step S401), and the CPU model 201 can read an instruction from the memory model 206 (step S402), the CPU model 201 changes to the memory model 2
The instruction to be executed is read from 06 (step S40
3). Next, after interpreting this instruction, the instruction is executed (step S404).

After execution of this instruction, the CPU model 201
External access from hardware model 2
It is checked whether the execution of 07 and 208 is processed (step S
405). If necessary in this examination, the execution of the hardware model 207 or 208 is processed (step S40).
6). Then, it is checked whether a breakpoint is set at the executed instruction position or whether there is a termination or interruption instruction from the monitor 202 (step S407). Depending on the conditions, the simulation executing unit ends the execution and returns to the execution in the monitor 202.

At this time, the register information (not shown) of the CPU model 201, the contents of the memory model 206, and the register information of the hardware models 207 and 208 are held. When the simulation execution unit does not finish its execution, the instructions are read and the simulations are sequentially executed as the system clock signal advances again.

FIG. 12 is a block diagram for explaining another example of the conventional simulator operation. In FIG. 12, this simulator operation shows an access state from the CPU model 201 to the register information of the hardware models 207 and 208 and an access state from the monitor 202 to the register information of the hardware models 207 and 208. In both of these accesses, the device model unit 205 accessed by the address decoder 203
After determining the hardware models 207 and 208 of
The "Read () function" and "Write () function" are called.

FIG. 13 is a diagram for explaining the "Write () function" of the hardware models 207 and 208 in the conventional simulator. In FIG. 13, the hardware models 207 and 208 have a model example of a structure that starts operation only when the register information thereof reaches a certain condition by a “Write () function” for optimization of simulation. . Hardware model 20
When the “Write () function” 7, 208 is called, the address information (address value) is decoded in the function, and after calculating the expected register information, the argument (data) is assigned to the variable corresponding to the address information. ) Is substituted. After that, when certain conditions are satisfied, the hardware models 207 and 208 are activated and terminated. The hardware models 207 and 208 are activated by the CPU model 201.
In order to register that the hardware models 207 and 208 are activated. If certain conditions are met, for example, there are registers that prevent rewriting during operation.

FIG. 14 is a "Read () function" of the hardware models 207 and 208 in the conventional simulator.
It is a figure for explaining an example. In FIG. 14, the hardware models 207 and 208 are accessed by the “Read () function” for optimization of simulation,
In addition, under certain conditions, the register information may not be read and other functions may operate. In the example of FIG. 14, when the interrupt status register data is read, if the value is a logical value "1", the interrupt status is sent (event notification). When the "Read () function" of the hardware model is called, the address information is decoded in the function. After calculating the register information by this decoding, the factor (da
Substitute in ta). Next, the called register information (register value) is checked. If this check satisfies the condition, an interrupt event is sent.

FIG. 15 is a block diagram for explaining still another example of the conventional simulator operation. In FIG. 15, this simulator operation example is a CPU model 201.
From memory to memory model 206 and monitor 2
02 shows the access state of the memory model 206 from 02. For both accesses, the address decoder 20
The same memory model 206 “Read ()
Function "or" Write () function "is called.
When the "Read () function" is called, the address information (address value) given as an argument is decoded in the function, the variable of the corresponding memory model 206 is derived, and the value is given as the argument. To.

On the other hand, when the "Write () function" is called, the address information (address value) given as an argument is decoded in the function to derive the variable of the corresponding memory model 206. In this derivation, the value given as an argument is substituted for the variable. Further, when the “Read () function” and “Write () function” of the memory model 206 are accessed, the information accessed is also transmitted to the cache memory model 204 by the memory model 206 at the same time. Model 2
Reference numeral 04 appropriately changes the cache contents, changes the cache hit / miss hit information, and further returns the cache hit / miss hit information to the memory model 206.

When data is read from the memory model 206, "Cac" of the cache memory model 204 is read.
The “he_Read () function” is called, and the read memory address contents are the cache memory model 204.
Check if it exists inside. At this time, after the address decoder 203 receives a return value indicating whether or not the cache memory model 204 is hit from the memory model 206, the address decoder 203 waits until the CPU model 201 is read into the memory model 206 based on the information. calculate.
At the time when reading is completed, the CPU model 201 gives an instruction to the simulation executing unit so that the next instruction cannot be read.

On the other hand, when data is written in the memory model 206, "C" of the cache memory model 204 is written.
The "ache_Write () function" is called, and the written memory address contents are the cache memory model 2
Check if it exists in 04. If it does not exist, the contents of the cache memory model 204 are rewritten. At this time, the address decoder 203 receives the return value indicating whether the cache memory model 204 is hit from the memory model 206, and thereafter, based on the information, until the CPU model 201 finishes writing to the memory model 206. Then, the CPU model 201 instructs the simulation execution unit so that the next instruction cannot be read.

FIG. 16 is a block diagram for explaining still another example of the conventional simulator operation. In FIG. 16, this simulator operation example is a CPU model 201.
From the monitor 202 to the cache memory model 204 from the monitor 202
Indicates the access status to. Unlike the actual cache memory (not shown), the cache memory model 204 of this simulator does not hold the contents of this cache memory and the address information of the cache memory, but only the address information of the memory (memory model 206). The memory model 206 (not shown) which is held and directly accessed by the memory contents indicated by the address information is directly accessed. That is, when the cache hits, only the information indicating the hit is returned to the address decoder 203. If the cache does not hit, the information in the cache memory is simply rewritten.

The "Read () function" of the same cache memory model 204 when accessing from the CPU model 201 and when accessing from the monitor 202,
The "Write () function" is called. "Read
() Function "is called, the address information (address value) given as an argument in the function is decoded,
It is calculated which part of the cache memory model 204 is shown. Then, it is calculated which part of the entire cache memory the cache memory model 204 shows. Further, the cache memory model 204 substitutes information about which part of the entire cache memory is the cache, that is, address information (address value) into a variable given as an argument.

On the other hand, when the "Write () function" is called, the address information (address value) is decoded in the function to calculate which part of the cache memory model 204 is shown. Then, the value given by the argument is substituted. "Read () function" and "Wr
When the "ite () function" is called, the cache memory model 204 informs the "Cache_Count () function" whether or not the cache is hit, and this "C
The ache_Count () function "is used to create statistical information on the number of cache hits and the number of cache misses. This time informs the monitor 202 of this information if requested by the monitor 202.

[0023]

The above-mentioned conventional example has the following inconveniences, and its improvement is a problem in order to obtain a high-speed and reliable simulator operation (entire and comprehensive operation verification simulation). It was

(1) In order to speed up the simulator, the hardware model starts or ends its operation by the "Write () function" or the "Read () function".
Sends an interrupt by. In this case, there is a problem that the operation cannot be performed by the distinction, and malfunction occurs in the hardware model and the entire simulator. (2) There is a hardware model in which writing to the register is prohibited during operation. Even if the "Read () function" and "Write () function" of such a hardware model are accessed, only the information that the access cannot be executed is given. As a result, there arises a problem that the register information (register value) cannot be read or changed. (3) When reading or writing to the memory model, the cache memory model may be accessed, and when reading or writing to the cache memory model, the number of accesses changes. Occurs.

The present invention has been made by paying attention to the above points. As a first object of the present invention, a malfunction for access to a hardware model does not occur and a simulation execution result can be obtained quickly. As a result, high-speed and reliable simulator operation (overall
(EN) Provided are an execution method of an operation verification simulation, a simulation execution device, and a program that enable comprehensive operation verification simulation).

As a second object of the present invention, it is possible to prevent the cache from being inappropriately changed when accessing the cache memory model, and to obtain the information of the memory model quickly. (EN) Provided are an execution method of a motion verification simulation, a simulation execution device, and a program, which enable an extremely high-speed and reliable simulator operation.

Furthermore, as a third object of the present invention, it is possible to prevent incorrect statistical information from being output and to quickly obtain cache information in the cache memory model, resulting in high speed. Provided are an execution method of a motion verification simulation, a simulation execution device, and a program that enable reliable simulator operation.

[0028]

According to the present invention, a control system model modeling the processing of a control system, a monitor for executing a simulation control by an input operation and an output display, and a model of hardware in a device to be simulated are provided. A method for executing a behavioral verification simulation having a simplified hardware model, the step of calling a first function by accessing the hardware model from the control system model, and the hardware model from the monitor. Access to the second function, and executing a predetermined instruction of the first function with respect to the hardware model based on an instruction of the second function.

Further, the execution method of the operation verification simulation of another invention is a control system model in which the processing of the control system is modeled, a monitor for executing simulation control by input operation and output display, and a simulation target device. And a hardware model modeling hardware to execute an operation verification simulation, and a step of calling a first function by accessing the hardware model from the control system model; Performing a process including starting and ending with respect to the hardware model by a function, and executing a process of writing and reading, and calling a second function by accessing the hardware model from the monitor, The second function is different from the first function. With the number of the process is also reduced, it is characterized by a step of performing only the activation and reading process without performing processing including termination for the hardware model.

In the method of the invention described above, the first function and the second function
Due to the divided processing of functions, malfunctions due to access to the hardware model do not occur, and simulation execution results can be obtained quickly, resulting in fast and reliable simulator operation (overall
Comprehensive operation verification simulation) is possible.

Further, the operation verification simulation execution method of the present invention models a control system model that models the processing of the control system, a monitor for executing simulation control by input operation and output display, and a cache memory. And a cache memory model, a memory model in which the firmware program executed by the control system model is stored and a memory model, and a hardware model in which the hardware of the simulation target device is modeled are verified. And calling a first function by accessing the memory model from the control system model, and executing a process including writing and reading into the cache memory model by the first function. With steps Calling a second function by accessing the memory model from the monitor, and notifying access information from the memory model to the cache memory model to change the contents of the cache memory model by the second function. In addition, the cache hit / miss hit information is changed, and a process of returning the memory model information is executed.

In the method of the invention described above, the first function and the second function
By dividing the functions, it is possible to prevent the cache from being changed illegally when the cache memory model is accessed, and to obtain the information of the memory model quickly, resulting in high speed and high speed. Enables reliable simulator operation.

The operation verification simulation execution method of the present invention comprises: a control system model that models the processing of the control system;
A monitor for executing simulation control by input operation and output display, a memory model storing a firmware program executed by the control system model and modeling a memory, and a cache memory model modeling a cache memory. And executing an operation verification simulation, invoking a first function by accessing the cache memory model from the control system model, and changing the contents of the cache memory model by the first function. And a step of changing the cache hit / miss hit statistical information, and a step of causing the cache memory model to notify the third function of the cache hit / miss hit by calling the first function. When, By creating statistical information by the third function of, and executing a process of notifying the statistical information from the cache memory model in response to a request from the monitor; and accessing the cache memory model from the monitor, Different from the first function, the second function is called, and the second function is different from the first function in that the statistical information is not changed and only the reference is executed without changing the contents of the cache memory model. It is characterized by having.

In the method of the invention described above, the first function and the second function
By the processing divided into functions and the processing by the third function,
It is possible to prevent the output of incorrect statistical information,
The information cached in the cache memory model can be quickly obtained, and as a result, high-speed and reliable simulator operation becomes possible.

The method of the invention is characterized in that the first function, the second function and the third function are object-oriented structured programming languages.

The simulation execution apparatus of the present invention executes a motion verification simulation, and includes a control system model section that models the processing of the control system and a monitor section that executes simulation control by input operation and output display. And a hardware model part that models the hardware in the simulation target device,
The first function called by the access to the hardware model section from the control system model section performs a process including activation and termination of the hardware model section,
Moreover, the number of processes is reduced as compared to the first function by the second function called by the access to the hardware model section from the monitor section by executing the writing and reading processes, and the hardware model section is processed. The feature is that only the reading process is executed without performing the process including the start and the end.

The simulation executing apparatus of the present invention executes an operation verification simulation,
A control system model part modeling the processing of the control system, a monitor part for executing simulation control by input operation and output display, a cache memory model part, and a firmware program executed by the control system model part are stored. The cache memory has a memory model unit and a hardware model unit that models the hardware in the simulation target device, and the first function called by the access from the control system model unit to the memory model unit Access information from the memory model unit to the cache memory model unit is executed by the second function called by executing a process including writing and reading into the model unit and accessing the memory model unit from the monitor unit. Notify the cache memory model Change the contents of the section, and is characterized in that to execute a process to change the cache hit miss information and further returns the information of the memory model unit.

Further, the simulation executing apparatus of the present invention executes the operation verification simulation, and is for executing the simulation control by the control system model part modeling the processing of the control system and the input operation and the output display. A monitor unit, a memory model unit in which a firmware program executed by the control system model unit is stored,
A cache memory model part that models a cache memory, and changes the contents of the cache memory model part by a first function called by the access from the control system model part to the cache memory model part, and a cache hit -A process for changing the statistical information of the mishit is executed, and the cache memory model unit notifies the third function of the cache hit / mishit information to create the statistical information, and the statistical information is provided to the monitor unit. Executes the process to be notified by the request from
Unlike the first function, the second function called by the access from the monitor unit to the cache memory model unit does not change the statistical information and does not change the contents of the cache memory model unit and only refers. It is characterized by executing processing.

In the devices of these inventions, similarly to the inventions of the above-mentioned devices, by the divided processing of the first function and the second function, as a result, a high-speed and reliable simulator operation (entire / total operation verification simulation) is performed. ) Is possible.

In the program of the present invention, the first function called by the access to the hardware model from the control system model performs the processing including the activation and termination of the hardware model, and the writing and reading processing. The second function called by the control and the access to the hardware model from the monitor reduces the number of processes as compared with the first function, and executes only the read process without performing the process including starting and ending the hardware model. The control is substantially executed by a computer.

Further, in the program of the present invention, the first function called by the access to the memory model from the control system model executes the control including the writing and reading in the cache memory model, and the memory from the monitor. The memory model notifies the cache memory model of the access information by the second function called by accessing the model to change the contents of the cache memory model, and changes the cache hit / miss hit information. The substantial computer executes the control for executing the process of returning the information.

Further, in the program of the present invention, the contents of the cache memory model are changed by the first function called by the access to the cache memory model from the control system model, and the statistical information of cache hit / miss hit is changed. The control for executing the processing, the control for executing the processing for the cache memory model to notify the third function of the cache hit / miss hit by the call of the first function, and the statistical information creation by the third function, Unlike the first function, the cache does not change the statistical information by the control that executes the processing of notifying the statistical information from the cache memory model in response to the request from the monitor and the second function called by the access to the cache memory model from the monitor. Memory model contents change In which substantial computer executes a control for executing the processing for reference only without.

With the above-mentioned program of the present invention, the present invention can be provided as an information recording medium, for example, package software, so that the whole / total operation verification simulation of the present invention can be executed by a computer or a dedicated device. Therefore, its versatility is improved.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of an operation verification simulation executing method, a simulation executing apparatus, and a program of the present invention will be described in detail with reference to the drawings. The following description will be given with reference to some of the drawings referred to in the conventional example. (First Embodiment) This first embodiment corresponds to the above-described first purpose (prevention of malfunction due to access from the monitor of the simulator and quick knowledge of the processing result). Figure 1
FIG. 3 is a block diagram showing a configuration of a simulator in the first embodiment. In FIG. 1, the simulator of the first embodiment is a CPU model 101 (corresponding to a control system model portion in claims) which is a model of a CPU (corresponding to a control system in claims) of the electronic device. The same applies to the third embodiment), a monitor 102 for executing simulation control (corresponding to a monitor unit in claims / the same applies to the second and third embodiments below), and an address decoder 103 (address decoder unit in claims). Corresponding to / same as the following second and third embodiments), and a cache memory model 104 modeling a cache memory inside an electronic device (corresponding to the cache memory model in claims / the following second and third embodiments) The same).

Further, this simulator has a device model section 105 (corresponding to the device model section in the claims / the same applies to the second and third embodiments below) that models various functions of the electronic device. Model part 10
5, a firmware program executed by the CPU model 101 is stored, and a memory model 106 that models a memory that is a storage electronic device of the electronic device (corresponds to the memory model portion in the claims / the following second and second Three
The same applies to the embodiment) and a plurality of hardware models 107 and 108 (each corresponding to the hardware model in the claims / the same applies to the second and third embodiments below) that models each function of the electronic device. ing.

The monitor 102 is a man-machine interface with a user who performs a simulation using a simulator. For example, an input operation device, an output device, and a display device (keyboard, printer, CRT / LCD device).
And controls the simulation run. The monitor 102 executes the following processing when the simulation is executed. (1) Setting and canceling a breakpoint in the firmware program (2) Start, suspension, end and step execution of simulation (3) Hardware register information and memory model 1
06, writing and reading register information (register value) to the cache memory model 104 and the CPU model 101 (4) Display of assembler code of firmware program executed by the CPU model 101

Each model in FIG. 1 is described in an object-oriented structured programming language / “C ++” language, and each model is one “Class”. The models other than the cache memory model 104 shown in FIG. 1 and the monitor 102 are connected through an address decoder 103, and the cache memory model 10 is connected.
4 is directly connected to the monitor 102, the CPU model 101, and the memory model 106. Further, the monitor 102 and each of the above-described models in FIG. 1 can access the address information (address value) of the other model by “Read
() Function ”or“ Write () function ”(corresponding to the first function in the claims / the same applies to the second and third embodiments below). Hardware model 107, 10
8, a "Read () function" and a "Write () function" as well as a "Monitor_Read () function" and a "Monitor_Write () function" (corresponding to the second function in the claims / the second and third embodiments below). Is also the same) and.

The simulator operation of the first embodiment (entire / total operation verification simulation) will be described below. First, the basic operation of the simulator of FIG. 1 will be described (FIG. 10 step S301 of the conventional example).
~ S303). When the simulation starts to be executed, the hardware models 107 and 108 and the CPU model 101 in FIG. 1 are initialized according to an instruction from the monitor 102. Next, the standby state for an instruction from the user to the monitor 102 is set. Here, on the monitor 102, "r
When receiving an instruction such as “un (restart)”, the monitor 102 calls a simulation execution unit (not shown in FIG. 1, for example, a processing module when a computer is used as a simulator) to start (restart) the simulation.

During this simulation, the above-mentioned breakpoints are set in the firmware program,
Also, when the user instructs the monitor 102 to suspend, the simulation is temporarily suspended and the monitor 1 is restarted.
It will be in a state of waiting for an instruction from 02. When there is a user instruction of “Read” or “write” on the monitor 102, the “R” of this instruction is given through the address decoder 103.
"ead" and "write" are hardware model 10
In the case of 7,108, the "Monitor_Wr
ite () function "or" Monitor_Read () "
Function ". Other models call the “Read () function” or the “Write () function” through the address decoder 103 or directly, and when the user instruction is “Read”, the result is returned to the monitor 102. If the user instruction is "end", the simulation ends.

Next, the contents of the above-mentioned simulation execution unit will be explained (FIG. 11 step S401 of the conventional example).
Up to S407). When the simulation executing unit is called from the monitor 102 shown in FIG. 1, first, one system clock signal in the simulator is advanced, and C
When the PU model 101 can read an instruction from the memory model 106, the CPU model 101 reads an instruction to be executed from the memory model 106. Then, after interpreting this instruction, the instruction of the interpretation is executed. After execution of this instruction, it is checked whether there is external access from the CPU model 101 or whether the execution of the hardware models 107 and 108 is processed. This check handles the execution of the hardware model 107 or 108 if necessary. Then, it is checked whether a breakpoint is set at the executed instruction position or whether there is a termination or interruption instruction from the monitor 102. Depending on the conditions, the simulation executing unit ends the execution and returns to the execution in the monitor 102.

At this time, the register information (not shown) of the CPU model 101, the contents of the memory model 106, and the register information (register value) of the hardware models 107 and 108 are held. When the simulation execution unit does not finish the execution, it advances the system clock signal again, reads the instruction, and sequentially executes the simulation.

Next, the simulator operation of the present invention based on the above-described simulator basic operation (overall / total operation verification simulation) will be described. FIG. 2 is a block diagram for explaining the simulator operation of the first embodiment. 1 and 2, this simulator operation example shows an access state from the CPU model 101 to the register information of the hardware and an access state from the monitor 102 to the register information of the hardware model in the device model unit 105. When the CPU model 101 accesses the register information of the hardware model in the device model unit 105, the hardware model 10 to be accessed by the address decoder 103.
After selecting and deciding 7,108, "Read () function"
Alternatively, the “Write () function” is called.

On the other hand, when accessing the register information of the hardware model in the device model section 105 from the monitor 102, the hardware models 107 and 108 to be accessed are determined by the address decoder 103, as in the case of the CPU model 101. (select.
The "Monitor_Write () function" or "Monitor_Read () function" of the selected hardware model (107 or 108) is called.

Next, "Monitor_W" in FIG.
The “write () function” will be described. FIG. 3 is a diagram for explaining the “Monitor_Write () function” in FIG. In FIG. 3, the monitor 102 causes the hardware models 107 and 108 to display “Monitor”.
When the "or_Write () function" is called, the address information (address value) in this function is decoded, and after the expected predetermined register information is calculated,
An argument (data) is assigned to the variable corresponding to this address information. This "Monitor_Write () function" is similar to the "Write () function" of the hardware model of the simulator described in the conventional example, as shown in FIG.
No processing such as activating and terminating the internal hardware models 107 and 108 is performed. In other words, the malfunction does not occur as described above. Further, unlike the “Write () function” of the hardware model of the simulator described in the conventional example, writing is not prohibited, so the register information of the hardware models 107 and 108 is written in any state. be able to.

Next, "Monitor_R" in FIG.
The "ead () function" will be described. Figure 4 shows "Moni
is a diagram for explaining a "tor_Read () function". In FIG. 4, the monitor 102 displays the “Monitor_Read” of the hardware models 107 and 108.
When the "() function" is called, the address information (address value) in this function is decoded, the expected predetermined register information (address value) is calculated, and then the argument of the variable of this address information (data) is calculated. Is substituted.
The "Monitor_Read () function" does not execute any function other than reading the register information, unlike the "Read () function" of the hardware models 107 and 108 of the conventional simulator. Therefore, malfunction does not occur in the hardware models 107 and 108 and other models shown in FIG.

As described above, in the first embodiment, when the hardware model 107, 108 is accessed from the monitor 102, the "Read () function or Write () function" stored in the hardware model 107, 108 is stored.
"Monitor_Read" for reducing the number of processes in the function, performing no process including activation and termination of the hardware models 107 and 108, prohibiting writing, and executing only read process.
() Function or Monitor_Write () function "is called.

As a result, through the processing in which these two functions are divided, a malfunction due to an access from the monitor 102 does not occur, and the processing result can be obtained quickly, resulting in a fast and reliable simulator operation ( Overall / total operation verification simulation) becomes possible.

(Second Embodiment) This second embodiment has the above-mentioned second purpose (prevention of alteration of the cache memory model when accessing from the monitor of the simulator and quick acquisition of memory model information). Corresponding to. FIG. 5 is a block diagram showing the simulator configuration of the second embodiment. 5, the second embodiment is similar to the first embodiment in a CPU model 501, a monitor 502, an address decoder 503, and a cache memory model 504.
And a device model section 505. The device model section 505 is provided with a memory model 506 and a plurality of hardware models 507 and 508.

The monitor 502 is a man-machine interface similar to that of the first embodiment, and executes the following processing when executing the simulation. (1) Setting and canceling a breakpoint in the firmware program (2) Start, suspension, end and step execution of simulation (3) Hardware register information and memory model 5
Writing and reading register information (register value) to 06 (4) Display of assembler code of firmware program executed by CPU model 501

Further, each model in FIG.
Similar to the embodiment, it is described in the “C ++” language, and each has one “Class”. Models other than the cache memory model 504 and the monitor 502 in FIG.
The cache memory model 504 is connected through the address decoder 503, and the cache memory model 504 includes a monitor 502 and a CPU model 5.
01 and the memory model 506 are directly connected. In addition, the monitor 502 and each model in FIG. 9 can access the address information of other models by "Read ()".
Function "or" Write () function ". The hardware models 507 and 508 include “Read ()
"Function" and "Write () function" together with "Moni
tor_Read () function "and" Monitor_Wr
"ite () function" is prepared.

The simulator operation of the second embodiment (entire / total operation verification simulation) will be described below. First, the basic operation of the simulator of FIG. 5 will be described (FIG. 10, steps S301 to S30).
3). The basic operation of this simulator is similar to that of the first embodiment, and will be summarized here. After the simulation starts to be executed, the monitor 502 initializes each unit and enters a standby state. Here, when a user instruction such as “run (restart)” is given to the monitor 502, the simulation execution unit is called to start (restart) the simulation.

When a breakpoint is designated during this simulation or a user instruction for suspension is given, the simulation is temporarily suspended and the instruction waiting state is resumed. When there is a user instruction of “Read” or “write” on the monitor 502, the “Read” or “write” of this instruction is made through the address decoder 503.
te ”is for the hardware models 507 and 508, the“ Monitor_Write () function ”or the“ Monitor_Read () function ”is called,
Other models in FIG. 5 call the “Read () function” or the “Write () function” through the address decoder 503 or directly. If the user instruction is “Read”, the result is monitored by the monitor 5.
If the user instruction is “end”, the simulation ends.

Next, the contents of the above-mentioned simulation executing section will be described (FIG. 11, steps S401 to S40).
7). The basic operation of this simulator is similar to that of the first embodiment, and will be summarized here. When the simulation execution unit is called from the monitor 502, one system clock signal is advanced and the CPU
The model 501 reads an instruction to be executed from the memory model 506, and the hardware model 50 based on this instruction is read.
7 or 508 execution.

Then, it is checked whether a breakpoint is set at the executed instruction position or whether there is a termination or interruption instruction from the monitor 502. The simulation execution unit ends the execution and returns to the execution in the monitor 502. At this time, the register information (not shown) of the CPU model 501, the contents of the memory model 506 and the register information (register value) of the hardware models 507 and 508 are held, and the simulation executing unit advances the system clock signal again to execute the instruction. Is read and the simulation of the instruction is sequentially executed.

FIG. 6 is a block diagram for explaining the simulator operation of the second embodiment. In FIG. 6, this simulator operation example shows an access state from the CPU model 501 to hardware register information and a monitor 502.
Show access states to the register information of the hardware models 507 and 508. When accessing the memory model 506 from the CPU model 501, the “Rea” of the memory model 506 is accessed through the address decoder 503.
Call the "d () function" or "Write () function".

When this call is the "Read () function", the address information (address value) given as an argument
Of the corresponding memory model 506
Derive the variable and assign the variable value to the variable given as an argument. On the other hand, when the "Write () function" is called, the address information (address value) given as an argument is decoded in the function, a variable of the corresponding memory model 506 is derived, and the variable is given to that variable as an argument. Substitute the value

Further, the "Read () function" or "Write ()" of the CPU model 501 to the memory model 506 is used.
When the “function” is accessed, the information indicating that the cache memory model 504 has been accessed is also notified by the memory model 506 at the same time, and the cache memory model 504 appropriately changes the cache contents and cache hit / miss hit information. Or to return cache hit / miss hit information to the memory model 506. When data is read from the memory model 506, “Cache_R” of the cache memory model 504 is read.
The "ead () function" is called to check whether the read memory model 506 contents exist in the cache memory model 504.

At this time, the address decoder receives, from the memory model 506, a return value indicating whether or not the cache memory model 504 is hit, and thereafter, based on this information, the CPU model 501 is read into the memory model 506 until the end. Calculate time. Until the end of reading, the simulation model is instructed so that the CPU model 501 cannot read the next instruction. On the other hand, when data is written in the memory model 506, “Cac of the cache memory model 504 is
The "he_Write () function" is called to check whether the contents of the written memory address information exist in the cache memory model 504.

If the contents of the memory address information do not exist in this check, the contents of the cache memory model 504 are rewritten. At this time, the address decoder receives from the memory model 506 a return value indicating whether or not the cache memory model 504 is hit. Based on the information of the received value, the CPU model 501 makes the memory model 506
Calculate the time until writing is completed. Until this writing ends, the simulation execution unit is instructed so that the CPU model 501 cannot read the next instruction.

Next, the monitor 502 is the memory model 50.
6 is accessed through the address decoder 503, “Monitor_Read” of the memory model 506.
() Function "or" Monitor_Write () function "is called. "Monitor_Rea
When the "d () function" is called, the address information given as an argument is decoded in the function, a variable of the corresponding memory model 506 is derived, and this variable value is substituted for the variable given as an argument.

"Monitor_Write () function"
Is called, the address information (address value) given as an argument is decoded in the function, a variable of the corresponding memory model 506 is derived, and this variable value is substituted for the variable given as an argument. When the “Monitor_Read () function” and the “Monitor_Write () function” of the memory model 506 are called from the monitor 502, the CPU model 501 displays “Rea
Unlike when the "d () function" and the "Write () function" are called, the cache memory model 504 is not accessed when the functions are called.

As described above, in the second embodiment, the CP
Access information is notified when the U model 501 accesses the memory model 506, the cache contents are changed, and the cache hit / miss hit information is changed.
Returns memory model information. Also, unlike the case where the "Read () function" or "Write () function" is called, the "Monitor_Read () function" or "Mo" that does not access the cache memory model 504 is executed.
"nitor_Write () function" is called.

As a result, when access is made from the monitor 502 through the processing in which both functions are divided, it is possible to prevent the contents of the cache memory model 504 from being unduly changed, and the information in the memory model 506 is It can be obtained quickly, and as a result, high-speed and reliable simulator operation becomes possible.

(Third Embodiment) This third embodiment corresponds to the above-described third purpose (blocking output of erroneous statistical information and quick acquisition of cache information). FIG. 7 is a block diagram showing the simulator configuration of the third embodiment. In FIG. 7, the simulator of the third embodiment has a CPU model 601 having the same function as that of the first embodiment and a monitor 602.
An address decoder 603, a cache memory model 604, and a device model unit 605. The device model unit 605 has a memory model 606 and a plurality of hardware models 607 and 608.

The monitor 602 executes the following processing when the simulation is executed. (1) Setting and canceling a breakpoint in a firmware program (2) Start, suspension, end and step execution of simulation (3) Hardware register model information, memory model 606, cache memory model 604 and CPU
Writing and reading register information of model 601 (4) Display of assembler code of firmware program executed by CPU model 601

Each model shown in FIG. 7 is described in the “C ++” language as in the first embodiment, and each model is one “Class”. A model other than the cache memory model 604 and the monitor 602 shown in FIG.
Are connected through the address decoder 603, and the cache memory model 604 is directly connected to the monitor 602, the CPU model 601, and the memory model 606.
In addition, the monitor 602 and each model shown in FIG.
For access to address information of other models, use "Rea
d () function "or" Write () function ". The hardware models 607 and 608, the memory model 606, and the cache memory model 604 include “Re
"Monitor function" and "Write () function" together with "Monitor_Read () function" and "Monitor
"or_Write () function" is prepared.

The simulator operation of the third embodiment (entire / total operation verification simulation) will be described below. The basic operation of this simulator is similar to that of the first embodiment, and will be summarized here. First, the basic operation of the simulator in FIG. 7 will be described (see steps S301 to S303 in FIG. 10). When the simulation starts to be executed, the hardware models 607 and 608, the CPU model 601 and the like are initialized to be in a standby state. The user can run "run (re
"Start"), the monitor 602 calls the simulation execution unit to start (restart) the simulation.

During this simulation, the above-mentioned breakpoints are set in the firmware program,
Alternatively, when there is a user instruction for suspension from the monitor 602, the simulation is temporarily suspended and the instruction waiting state is entered. On the monitor 602, “Read” and “write” are displayed.
"e" is for the hardware models 607 and 608, the "Monitor_Write () function" or "Monitor_Read () function" is called, and in each of the other models, the address decoder 60 is used.
3 or directly, "Read () function" or "Wr
call the "ite () function". In addition, the user instruction is "R
In the case of “ead”, the result is returned to the monitor 602,
In the case of "end", the simulation ends.

Next, the contents of the simulation executing section will be described (steps S401 to S40 in FIG. 11).
7). The basic operation of this simulator is similar to that of the first embodiment, and will be summarized here. When the simulation execution unit is called from the monitor 602, one system clock signal is advanced and the CPU
The model 601 executes the instruction after reading and interpreting the instruction from the memory model 606. After that, it is checked whether there is external access from the CPU model 601 or whether the execution of the hardware model 607 or 608 is processed, and the execution of the hardware model 607 or 608 is processed.

Then, it is checked whether a breakpoint is set at the executed instruction position or whether there is a termination or interruption instruction from the monitor 602. Depending on the conditions, the simulation executing unit may terminate the execution and then monitor 602.
Return to execution in. At this time, the register information (not shown) of the CPU model 601, the contents of the memory model 606, and the register information (register value) of the hardware models 607 and 608 are held. When the simulation execution unit does not finish the execution, it advances the system clock signal again to read the instruction, and sequentially executes the simulation.

FIG. 8 is a block diagram for explaining the simulator operation of the third embodiment. In FIG. 8, this simulator operation is performed by the access state from the CPU model 601 to the cache memory model 604 and the monitor 602.
To the cache memory model 604 are shown. Unlike the actual cache memory, the cache memory model 604 of this simulator does not hold the cache memory contents and its memory address information, but only the address information. The memory model 606 is directly accessed according to the content indicated by the address information. That is, when the cache hits, this hit information is returned to the address decoder,
If the cache does not hit, the information in the cache memory model 604 is simply rewritten.

When the cache memory model 604 is accessed from the CPU model 601, the "Read () function" or the "Write" of the cache memory model 604 is used.
e () function "is called. This call is "Re
In the case of the “ad () function”, the address information (address value) given as an argument in the function is decoded, and which part of the cache memory model 604 is shown is calculated. Then, the address information (address value) indicating which part of the cache memory model is cached by the cache memory model 604 is substituted into the variable given as an argument.

On the other hand, the call is the "Write () function".
In the case of, the address information (address value) is decoded in the function, and which part of the cache memory model 604 is shown is calculated. Then, the value given by the argument is substituted. "Read () function" and "Writ
When the "e () function" is called, the cache memory model 604 determines whether the cache is hit by "C".
The "ache_Count () function" is also notified. This "Cache_Count () function" creates statistical information of cache hit / miss hit information (number of times). This statistical information notifies the monitor 602 of the information in response to a request from the monitor 602.

On the other hand, when accessing the cache memory model 604 from the monitor 602, the “Monitor_Read () function” or the “Monitor_Write () function” of the cache memory model 604 is called. In this call, "Monitor_R
When the "ead () function" is called, the address information (address value) given as an argument in the function is decoded, and which part of the cache memory model 604 is shown is calculated. Then, the cache memory model 604 substitutes information (address information) indicating which address information of the entire cache memory is cached into a variable given as an argument.

In addition, the above-mentioned call is "Monito
In the case of the “r_Write () function”, the address information (address value) is decoded in the function to calculate which part of the cache memory model 604 is shown. Then, the value given by the argument is substituted. In this cache memory model 604, "Monitor_Re
The “ad () function” and the “Monitor_Write () function” change the contents of the cache memory model 604,
Alternatively, it only refers to the cache hit count or the miss hit count, and does not change the statistical information.

As described above, in the third embodiment, "R
At the time of calling the "ead () function" or the "Write () function", the cache memory model 604 notifies the "Cache_Count () function" of the cache hit / miss hit, and here, the statistics of the cache hit count and the cache miss hit count. Create information and notify. When accessing the cache memory model 604 from the monitor 602, the “Read () function” or the “Write”
Unlike the case of calling the "e () function", only the reference is made without changing the cache contents, and the "Moni" for not changing the cache hit / miss hit statistical information.
"tor_Write () function" or "Monitor_
The "Read () function" is called.

As a result, erroneous statistical information can be prevented from being output through the processing in which these two functions are divided, and the information cached in the cache memory model 604 can be quickly obtained. As a result, high-speed and reliable simulator operation becomes possible.

[0088]

As is apparent from the above description, according to the present invention, it is possible to prevent a malfunction due to access to a hardware model and to quickly obtain a simulation execution result. This has the effect of enabling high-speed and reliable simulator operation (overall and comprehensive operation verification simulation).

Further, according to the present invention, when the cache memory model is accessed, it is possible to prevent the cache from being changed inappropriately, and it becomes possible to quickly obtain the information of the memory model. It has the effect that the simulator operation can be performed at high speed and reliably.

Further, according to the present invention, it is possible to prevent incorrect statistical information from being output and to quickly obtain information cached in the cache memory model, resulting in high speed and reliability. This has the effect of enabling various simulator operations.

[Brief description of drawings]

FIG. 1 is a block diagram showing a simulator configuration in a first embodiment of the present invention.

FIG. 2 is a block diagram for explaining a simulator operation of the first embodiment.

FIG. 3 is a diagram for explaining a function in the first embodiment.

FIG. 4 is a diagram for explaining another function in the first embodiment.

FIG. 5 is a block diagram showing a simulator configuration of a second embodiment.

FIG. 6 is a block diagram for explaining a simulator operation of the second embodiment.

FIG. 7 is a block diagram showing a simulation configuration of a third embodiment.

FIG. 8 is a block diagram for explaining a simulator operation according to the third embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional trace type simulator.

FIG. 10 is a flowchart for explaining a conventional simulator operation.

FIG. 11 is a flowchart for explaining processing contents of a simulation executing unit in FIG.

FIG. 12 is a block diagram for explaining another example of the conventional simulator operation.

FIG. 13 is a diagram for explaining a function in a conventional simulator.

FIG. 14 is a diagram for explaining another function in the conventional simulator.

FIG. 15 is a block diagram for explaining still another example of the conventional simulator operation.

FIG. 16 is a block diagram for explaining still another example of the conventional simulator operation.

[Explanation of symbols]

101, 501, 601 CPU model 102, 502, 602 Monitor 103, 503, 603 Address decoder 104, 504, 604 Cache memory model 105, 505, 605 Device model section 106, 506, 606 Memory model 107, 108, 507, 508 , 607, 608 Hardware model

Claims (12)

[Claims] 1. A control system model for modeling processing of a control system, a monitor for executing simulation control by input operation and output display, and a hardware model for modeling hardware in a simulation target device are provided. In the method for executing the operation verification simulation, the step of calling the first function by the access to the hardware model from the control system model, and the second function by the access to the hardware model from the monitor And a step of executing a predetermined instruction of the first function with respect to the hardware model based on an instruction of the second function. 2. A control system model that models the processing of the control system, a monitor that executes simulation control by input operation and output display, and a hardware model that models the hardware in the simulation target device. In the method for executing a behavioral verification simulation, a step of calling a first function by accessing the hardware model from the control system model, and a process including activation and termination of the hardware model by the first function And executing a writing and reading process, calling a second function by accessing the hardware model from the monitor, and processing a number of processes by the second function more than the first function. Of the hardware How to perform operation verification simulation, characterized in that it comprises a step of executing only the starting and reading process without performing processing including termination for Le, a. 3. A control system model that models processing of a control system, a monitor for executing simulation control by input operation and output display, a cache memory model that models a cache memory, and the control system model A method for executing an operation verification simulation having a memory model in which a firmware program to be executed is stored and a memory modeled, and a hardware model in which a hardware in a simulation target device is modeled, wherein: Accessing the memory model to call a first function; executing a process including writing and reading to the cache memory model by the first function; and accessing the memory model from the monitor. By access And calling the second function, the second function notifies the cache memory model of access information to change the contents of the cache memory model, and the cache hit / miss hit information. And a step of performing a process of returning the memory model information, and a method of executing an operation verification simulation, comprising: 4. A control system model modeling the processing of the control system, a monitor for executing simulation control by input operation and output display, a firmware program executed by the control system model, and a memory. A method for executing a behavioral verification simulation having a modeled memory model and a cache memory model that models a cache memory, wherein a first function is called by accessing the cache memory model from the control system model. A step of changing the contents of the cache memory model by the first function and a process of changing the statistical information of cache hit / miss hit; and a step of calling the first function, whereby the cache memory model is Cache hit A step of executing a process of notifying the third function of a mishit, and a process of creating statistical information by the third function and notifying the statistical information from the cache memory model in response to a request from the monitor And a step of calling a second function by accessing the cache memory model from the monitor, wherein statistical information is not changed by the second function unlike the first function, and the cache memory model of the cache memory model is changed. And a step of performing a process of only referring to the content without changing the content, and a method of executing an operation verification simulation, comprising: 5. The method according to claim 1, 2, or 3, wherein the first function and the second function are object-oriented structured programming languages. 6. The third function is an object-oriented structured programming language.
How to execute the described operation verification simulation. 7. A simulation execution device for executing a motion verification simulation, a control system model part modeling a process of a control system, a monitor part for executing simulation control by input operation and output display, and a device to be simulated. A hardware model part that models the hardware in the above, and a process including activation and termination for the hardware model part by the first function called by the access from the control system model part to the hardware model part. And then
Moreover, the number of processes is reduced as compared to the first function by the second function called by the access to the hardware model section from the monitor section by executing the writing and reading processes, and A simulation execution device, which executes only a read process without performing a process including start-up and end. 8. A simulation execution device for executing a motion verification simulation, a control system model part modeling a control system process, a monitor part for executing simulation control by input operation and output display, and a cache memory model. Unit, a memory model unit in which a firmware program executed by the control system model unit is stored, and a hardware model unit that models the hardware in the simulation target device, and the memory model from the control system model unit The first function called by accessing the memory model unit to execute processing including writing and reading to the cache memory model unit, and by the second function called by accessing the memory model unit from the monitor unit. , The memory model section From the above to the cache memory model section to notify the access information to change the contents of the cache memory model section, change the cache hit / miss hit information, and return the information of the memory model section. A simulation execution device characterized by executing. 9. A simulation execution device for executing a motion verification simulation, a control system model part for modeling processing of a control system, a monitor part for executing simulation control by input operation and output display, and a control system model. A first function called by the access from the control system model unit to the cache memory model unit, the memory model unit storing a firmware program to be executed by the unit, and a cache memory model unit modeling a cache memory. Performs the processing of changing the cache hit / miss hit statistical information while changing the contents of the cache memory model portion, and the cache memory model portion notifies the third function of the cache hit / miss hit information. And create statistical information Is executed in response to a request from the monitor unit, and the second function called by the monitor unit to access the cache memory model unit changes statistical information unlike the first function. A simulation executing device, characterized in that it executes a process of referring only without changing the contents of the cache memory model part. 10. A control for executing processing including start and end for the hardware model by a first function called by access to the hardware model from the control system model, and executing writing and reading processing, and a monitor. The second function called by accessing the hardware model from the above reduces the number of processes as compared with the first function, and controls to execute only the reading process without performing processes including starting and ending of the hardware model. A program that is essentially executed by a computer. 11. A control for executing a process including writing and reading to and from a cache memory model by a first function called by an access to a memory model from a control system model, and a call to access the memory model from a monitor. The second function is to notify the access information from the memory model to the cache memory model, change the contents of the cache memory model, change the cache hit / miss hit information, and return the memory model information. A control that is executed and a program that is executed by a substantial computer. 12. The contents of the cache memory model are changed by the first function called by accessing the cache memory model from the control system model,
Control for executing processing for changing statistical information of cache hit / miss hit; control for causing the cache memory model to notify processing of cache hit / miss hit to the third function by calling the first function; The statistical information is created by the three functions, and the first function is executed by the control that executes the process of notifying the statistical information from the cache memory model by the request from the monitor and the second function called by the access to the cache memory model from the monitor. Unlike a function, it is a program that causes a computer to execute the control that executes the processing that does not change the statistical information and does not change the contents of the cache memory model, and only performs the reference.