JP2003256199A - バンドルの命令を処理する方法 - Google Patents

バンドルの命令を処理する方法

Info

Publication number
JP2003256199A
JP2003256199A JP2003026816A JP2003026816A JP2003256199A JP 2003256199 A JP2003256199 A JP 2003256199A JP 2003026816 A JP2003026816 A JP 2003026816A JP 2003026816 A JP2003026816 A JP 2003026816A JP 2003256199 A JP2003256199 A JP 2003256199A
Authority
JP
Japan
Prior art keywords
instructions
cluster
instruction
processing
thread
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003026816A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003256199A5 (enExample
Inventor
Eric Delano
エリック・ディラーノ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003256199A publication Critical patent/JP2003256199A/ja
Publication of JP2003256199A5 publication Critical patent/JP2003256199A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
JP2003026816A 2002-02-27 2003-02-04 バンドルの命令を処理する方法 Pending JP2003256199A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/083,872 2002-02-27
US10/083,872 US7398374B2 (en) 2002-02-27 2002-02-27 Multi-cluster processor for processing instructions of one or more instruction threads

Publications (2)

Publication Number Publication Date
JP2003256199A true JP2003256199A (ja) 2003-09-10
JP2003256199A5 JP2003256199A5 (enExample) 2006-03-23

Family

ID=27753373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003026816A Pending JP2003256199A (ja) 2002-02-27 2003-02-04 バンドルの命令を処理する方法

Country Status (2)

Country Link
US (1) US7398374B2 (enExample)
JP (1) JP2003256199A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507034A (ja) * 2004-07-13 2008-03-06 エヌヴィディア コーポレイション 下位ポートカウントメモリーを用いたマルチポートメモリーのシミュレート

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9189230B2 (en) 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US7278014B2 (en) * 2004-12-02 2007-10-02 International Business Machines Corporation System and method for simulating hardware interrupts
CA2610084A1 (en) * 2005-06-16 2006-12-28 Laurence Kaiser Method of operating a satellite radio system
TWI334990B (en) * 2006-12-28 2010-12-21 Ind Tech Res Inst Virtual cluster architecture and method
US20090109996A1 (en) * 2007-10-29 2009-04-30 Hoover Russell D Network on Chip
US20090125706A1 (en) * 2007-11-08 2009-05-14 Hoover Russell D Software Pipelining on a Network on Chip
US20090125703A1 (en) * 2007-11-09 2009-05-14 Mejdrich Eric O Context Switching on a Network On Chip
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8526422B2 (en) * 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US7917703B2 (en) * 2007-12-13 2011-03-29 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8473667B2 (en) * 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8010750B2 (en) * 2008-01-17 2011-08-30 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8018466B2 (en) * 2008-02-12 2011-09-13 International Business Machines Corporation Graphics rendering on a network on chip
US8490110B2 (en) * 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US7913010B2 (en) * 2008-02-15 2011-03-22 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090245257A1 (en) * 2008-04-01 2009-10-01 International Business Machines Corporation Network On Chip
US20090260013A1 (en) * 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US20090271172A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Emulating A Computer Run Time Environment
US8078850B2 (en) * 2008-04-24 2011-12-13 International Business Machines Corporation Branch prediction technique using instruction for resetting result table pointer
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US20090282211A1 (en) * 2008-05-09 2009-11-12 International Business Machines Network On Chip With Partitions
US8214845B2 (en) * 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US7861065B2 (en) * 2008-05-09 2010-12-28 International Business Machines Corporation Preferential dispatching of computer program instructions
US8020168B2 (en) * 2008-05-09 2011-09-13 International Business Machines Corporation Dynamic virtual software pipelining on a network on chip
US8392664B2 (en) * 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US7958340B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Monitoring software pipeline performance on a network on chip
US8494833B2 (en) * 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US7991978B2 (en) * 2008-05-09 2011-08-02 International Business Machines Corporation Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor
US20090282419A1 (en) * 2008-05-09 2009-11-12 International Business Machines Corporation Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip
US8040799B2 (en) * 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels
US8230179B2 (en) * 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) * 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) * 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
US8595468B2 (en) * 2009-12-17 2013-11-26 International Business Machines Corporation Reverse simultaneous multi-threading
US8677371B2 (en) * 2009-12-31 2014-03-18 International Business Machines Corporation Mixed operating performance modes including a shared cache mode
US8510749B2 (en) 2010-05-27 2013-08-13 International Business Machines Corporation Framework for scheduling multicore processors
CN104011705A (zh) * 2011-12-01 2014-08-27 新加坡国立大学 多形异构性多核架构
US9672043B2 (en) 2014-05-12 2017-06-06 International Business Machines Corporation Processing of multiple instruction streams in a parallel slice processor
US9720696B2 (en) 2014-09-30 2017-08-01 International Business Machines Corporation Independent mapping of threads
US9977678B2 (en) * 2015-01-12 2018-05-22 International Business Machines Corporation Reconfigurable parallel execution and load-store slice processor
US10133576B2 (en) 2015-01-13 2018-11-20 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
US10133581B2 (en) 2015-01-13 2018-11-20 International Business Machines Corporation Linkable issue queue parallel execution slice for a processor
GB2539041B (en) * 2015-06-05 2019-10-02 Advanced Risc Mach Ltd Mode switching in dependence upon a number of active threads
US9983875B2 (en) 2016-03-04 2018-05-29 International Business Machines Corporation Operation of a multi-slice processor preventing early dependent instruction wakeup
US10037211B2 (en) 2016-03-22 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor with an expanded merge fetching queue
US10346174B2 (en) 2016-03-24 2019-07-09 International Business Machines Corporation Operation of a multi-slice processor with dynamic canceling of partial loads
US9977677B2 (en) * 2016-04-07 2018-05-22 International Business Machines Corporation Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
US10761854B2 (en) 2016-04-19 2020-09-01 International Business Machines Corporation Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor
US10037229B2 (en) 2016-05-11 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
US9934033B2 (en) 2016-06-13 2018-04-03 International Business Machines Corporation Operation of a multi-slice processor implementing simultaneous two-target loads and stores
US10042647B2 (en) 2016-06-27 2018-08-07 International Business Machines Corporation Managing a divided load reorder queue
US10318419B2 (en) 2016-08-08 2019-06-11 International Business Machines Corporation Flush avoidance in a load store unit
JP6996099B2 (ja) * 2017-03-24 2022-01-17 日本電気株式会社 データ処理システム及びデータ処理方法
US10521880B2 (en) * 2017-04-17 2019-12-31 Intel Corporation Adaptive compute size per workload
US10705847B2 (en) * 2017-08-01 2020-07-07 International Business Machines Corporation Wide vector execution in single thread mode for an out-of-order processor
US12254319B2 (en) * 2021-09-24 2025-03-18 Intel Corporation Scalable toggle point control circuitry for a clustered decode pipeline
WO2024205185A1 (ko) * 2023-03-27 2024-10-03 삼성전자주식회사 적어도 하나의 클러스터를 통해, 복수의 스레드들 각각을 실행하기 위한 전자 장치, 방법, 및 컴퓨터 판독 가능 저장 매체

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2665081B2 (ja) * 1991-07-08 1997-10-22 三菱電機株式会社 マイクロコンピュータのレジスタ間データ転送方式
JP3160149B2 (ja) * 1994-05-13 2001-04-23 株式会社日立製作所 ディスク制御装置の無停止プログラム変更方法およびディスク制御装置
US5689677A (en) * 1995-06-05 1997-11-18 Macmillan; David C. Circuit for enhancing performance of a computer for personal use
US5903771A (en) * 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
US6098165A (en) * 1997-06-25 2000-08-01 Sun Microsystems, Inc. Fetching and handling a bundle of instructions comprising instructions and non-complex instructions
US6151668A (en) * 1997-11-07 2000-11-21 Billions Of Operations Per Second, Inc. Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6272616B1 (en) * 1998-06-17 2001-08-07 Agere Systems Guardian Corp. Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths
US6269437B1 (en) * 1999-03-22 2001-07-31 Agere Systems Guardian Corp. Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor
US6629232B1 (en) * 1999-11-05 2003-09-30 Intel Corporation Copied register files for data processors having many execution units
US7320065B2 (en) * 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US6954846B2 (en) * 2001-08-07 2005-10-11 Sun Microsystems, Inc. Microprocessor and method for giving each thread exclusive access to one register file in a multi-threading mode and for giving an active thread access to multiple register files in a single thread mode
US7500240B2 (en) * 2002-01-15 2009-03-03 Intel Corporation Apparatus and method for scheduling threads in multi-threading processors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008507034A (ja) * 2004-07-13 2008-03-06 エヌヴィディア コーポレイション 下位ポートカウントメモリーを用いたマルチポートメモリーのシミュレート
US7834881B2 (en) 2004-07-13 2010-11-16 Nvidia Corporation Operand collector architecture

Also Published As

Publication number Publication date
US20030163669A1 (en) 2003-08-28
US7398374B2 (en) 2008-07-08

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