JP2003252215A - Current value detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current value detection device capable of always supplying correct detection values to a plurality of control devices through only a peak hold circuit. <P>SOLUTION: This current value detection device comprises an assist motor 8 for generating an assist torque for supplementing a steering torque, the peak hold circuit 24 for holding, as a maximum peak value, the maximum value of a current flowing through the motor 8, and a main microcomputer 30M and a sub microcomputer 30S reading the current peak values held in the peak hold circuit 24. The main microcomputer 30M comprises a function to output the reading instruction signals for the current peak values of the peak hold circuit to the sub microcomputer 30S and a function to output the clear signals of the current peak values to the peak hold circuit 24 after a time for the sub microcomputer 30S to read the current peak values is passed after the reading instruction signals are outputted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current value detecting device having a peak hold circuit for holding the maximum value of a motor drive current as a current peak value, and more particularly to a steering assist force for a steering system of a vehicle. The present invention relates to a current value detection device for an electric power steering device having an assist motor that is generated.

[0002]

2. Description of the Related Art Generally, an electric power steering apparatus is constructed as shown in FIG. In FIG. 7, the steering wheel 1 is a first steering shaft 2a.
And is connected to the second steering shaft 2b via the universal joint 3.

The second steering shaft 2b is
It is connected to a tie rod 6 of a steering wheel via a pinion 4 and a rack 5. Second steering shaft 2
A torque sensor 7 for detecting the steering torque of the steering wheel 1 is provided at b, and an assist motor 8 for assisting the steering force of the steering wheel 1 is coupled to the second steering shaft 2b via a reduction gear 9.
Reference numeral 10 denotes a vehicle state detection device that detects a running state of the vehicle such as engine speed, vehicle speed, and steering wheel load by a sensor.

Reference numeral 11 denotes a motor drive current (target current command value) from the detection output of the vehicle state detection device 10, the detection torque of the torque sensor 7, the detection current obtained from a current detector (not shown), a voltage detector, detection voltage, etc. ) Is obtained and the current supplied to the assist motor 8 is controlled based on the target current command value, and is composed of, for example, a microcomputer.

Reference numeral 12 is a relay which is turned on by turning on a key switch of an ignition key and is turned off, for example, in case of a malfunction. The controller 11 and the assist motor 8 are driven by the power source of the battery 13 supplied via the relay 12.

In the apparatus constructed as described above, the motor drive control section of the controller 11 drives the assist motor 8 to add the assist torque to the steering torque to improve the operability of the steering wheel 1.

In order to detect the motor drive current of the electric power steering apparatus constructed as described above, the peak current value of the motor drive current is converted into a voltage as disclosed in, for example, Japanese Patent Application Laid-Open No. 8-9681. The value was detected by the peak hold circuit and returned to the CPU (control device). In many cases, a plurality of CPUs, such as a main CPU and a sub CPU, are provided due to a fail-safe relationship, and it is necessary to feed back the peak current value to each of the main CPU and the sub CPU.

[0008]

However, when a plurality of peak hold circuits are provided for main and sub,
There is a problem that the circuit becomes complicated and the cost increases.

On the other hand, when the peak current value is fed back from the same peak hold circuit to each of the main CPU and the sub CPU, for example, during the period in which the peak current value clear signal is output from the main CPU to the peak hold circuit, the sub C
When the PU detects the current value of the peak hold circuit, the sub CPU cannot detect the correct peak current value (it detects a low current value after clearing), resulting in an erroneous judgment in fail-safe control or the like. There was a problem.

The present invention has been made in view of the above points, and an object thereof is to provide a current value detection device capable of always supplying correct detection values to a plurality of control devices by a single peak hold circuit. To do.

[0011]

A current value detecting device of the present invention for solving the above problems is a peak hold circuit for holding the maximum value of the current flowing through the circuit as a current peak value, and a peak hold circuit for holding the peak hold circuit. A first control device and a second control device for reading the read current peak value, and a current reading provided in the first control device for outputting the current peak value reading instruction signal to the second control device. The instruction means and the first control device are provided, and after the current reading instruction signal is output by the current reading instruction means, after a time required for reading the current peak value of the second control circuit elapses, A clear signal output means for outputting a clear signal of the current peak value to the peak hold circuit is provided.

The current read instruction means outputs the read instruction signal to the second control device at the same time when the current peak value of the first control device is read.

Further, a peak hold circuit for holding the maximum value of the current flowing through the circuit as a current peak value, a first controller and a second controller for reading the current peak value held in the peak hold circuit, Clear signal output means provided in the first control device for outputting a clear signal of the current peak value to the peak hold circuit;
The second control device is provided in the second control device, and the second signal is output when the clear signal is output by the clear signal output means.
When the control device of (1) reads the current value, the control device is provided with a reset means for reading the current value again after a lapse of a predetermined time.

Further, an assist motor for generating an assist torque for assisting the steering torque is provided, and the peak hold circuit holds the maximum value of the drive current of the assist motor as a current peak value. It is characterized in that it is composed of a main microcomputer, and the second control device is composed of a sub-microcomputer.

[0015]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to the electric power steering apparatus of FIG. 1, the same parts as those in FIG. 7 are indicated by the same reference numerals.

In FIG. 1, the positive side of the battery 13 is connected to the F circuit via the relay circuit 12a and the current detecting resistor 21.
ET (Field Effect Transistor) H1, H2, L1, L2
Is connected to a bridge circuit 22 formed by bridge connection.

An assist motor 8 is connected between the common connection point P ₁ of the FETs H1 and L1 and the common connection point P ₂ of the FETs H2 and L2. FET L1 and L
The common connection point of 2 is grounded (connected to the negative electrode side of the battery 13).

Reference numerals 23a and 23b denote voltage monitor circuits for detecting the voltage at both terminals of the assist motor 8 (the voltage at the common connection points P ₁ and P ₂ ).

Reference numeral 24 is a peak hold circuit for holding the maximum value of the motor drive current converted into a voltage by the current detecting resistor 21 and the operational amplifier 25 as a current peak value.

30 _M calculates the motor drive current (target current command value) from the output of the peak hold circuit 24, the torque detection signal of the torque sensor 7, etc., and the assist motor 8 is operated based on the target current command value. It is a main microcomputer (first control device) that controls the supplied current.

This main microcomputer 30
_M is a function of outputting a reading instruction signal (current signal A / D conversion synchronization signal) of the current peak value of the peak hold circuit 24 to the sub-microcomputer 30 _S (second control device), and the reading instruction signal. After is output,
The sub-microcomputer 30 _S has a function of outputting the current peak value clear signal (current signal peak hold clear signal) to the peak hold circuit 24 after the time required for reading the current peak value has elapsed. .

The sub-microcomputer 30 _S has a function of judging an abnormality of the device based on, for example, the running state of the vehicle detected by the vehicle state detecting device 10 of FIG. 7, and a clearing of the current peak value from the main microcomputer 30 _M. When a signal (current signal peak hold clear signal) is being output, if the sub-microcomputer 30 _S reads the current value, it has a reset function etc. to read the current value again after a lapse of a predetermined time. ing.

26 is a main microcomputer 30 _M
And on the sub-microcomputer 30 _S to the control signal introduced via the AND gate 27a, a relay to turn off the contact point and the contact point or on, the coil as a non-energized by energizing the coil of the relay circuit 12a It is a drive circuit.

A control signal for an enable signal is input to the AND gate 27b from the main microcomputer 30 _M and the sub microcomputer 30 _S , and the gate output (enable signal) of the AND gate 27b is supplied to each of the AND gates 27c and 27d. It is input to one of the input terminals.

The target current command signal from the main microcomputer 30 _M is supplied to the other input terminal of each of the AND gates 27c and 27d, and each output terminal is connected to the predrivers 28a and 28b.

28a, 28b and 28c, 28d
Is the main microcomputer 30 _MGoal calculated by
Pulse with duty ratio determined based on current command value
The width modulation (PWM) signal is fed to the FE of the bridge circuit 22.
The FE is supplied to the gates of TH1, H2, L1 and L2.
It is a pre-driver that controls T on / off.

Signals are exchanged between the main microcomputer 30 _M , the sub microcomputer 30 _S and its peripheral circuits via an interface (not shown).

In the apparatus configured as described above, during normal operation, the main microcomputer 30 _M and the sub microcomputer 30 _S move to the AND gate 27.
For example, a high level signal is supplied to a, the coil of the relay circuit 12a is excited by the relay drive signal output from the relay drive circuit 26, the contact is turned on, and the battery 13 supplies power to the bridge circuit 22. Is being supplied.

A high level signal is supplied from the main microcomputer 30 _M and the sub microcomputer 30 _S to the AND gate 27b, and the AND gates 27c and 27d are output by the output signal (high level enable signal) of the AND gate 27b. A high level signal is input to one of the input gates.

The bridge circuit 22 includes, for example, upper and lower simultaneous P circuits.
In the case of the WM drive system, the FETs H1 and L2 forming one pair are subjected to pulse width modulation control by the predrivers 28a and 28d in the case of the right rotation, and the FETH2 and L1 forming the other pair are in the predriver 28b in the case of the left rotation. , 28c perform pulse width modulation control.

Further, in the case of the method in which the upper (or lower) FET is PWM-driven and the lower (or upper) FET is always on-driven, the pulse width modulation control of the upper FET H1 is performed and the lower FET L2 is performed during right rotation. Is always on-controlled, and in the case of left rotation, the upper FET H2 is subjected to pulse width modulation control and the lower FET L1 is always on.

Therefore, from the battery 13 to the relay circuit 12
bridge circuit 22 via a and the current detection resistor 21.
The current supplied to the FET flows through the path of FET H1 (or H2) → assist motor 8 → FET L2 (or L1) → ground, and the assist motor 8 rotates to the right (or to the left).
As a result, the steering wheel 1 rotates in the direction in which the steering operation is performed, and assists the steering force.

Next, the operation of the current value reading process in this embodiment will be described with reference to FIGS. 2 shows a flow chart for reading the current value of the main microcomputer 30 _M , and FIG. 3 shows the sub-microcomputer 3
FIG. 4 shows a flow chart for reading a current value of 0 _S , FIG. 4 shows a time chart of various control signals output from the main microcomputer 30 _M , and FIG. 5 shows a time chart of FET drive signals, motor current and various control signals of the bridge circuit 22. Is shown.

In the main microcomputer 30 _M , first, as in steps S ₁ and S _{2 in} FIG. 2, the data in the memory is initialized when the ignition key switch is turned on, and then the torsion bar torque ( reading of the output) of the torque sensor 7 (step S _3), calculating the assist torque (step S _4), and calculates the target motor current (step S _5).

Then, in step S ₆ , the current signal A /
The D conversion synchronizing signal is set (time t _{1 in} FIGS. 4 and 5), and the motor current is read in step S ₇ .

Next, in step S ₈ , it is determined whether or not the time T1 has elapsed, and when T1 has elapsed, the current signal A / D conversion synchronization signal is cleared and the current signal peak hold clear signal is set in step S ₉ . (time t ₃ in FIG. 4, the time t ₄ in FIG. 5). This time T1 is
This is a delay margin time for ensuring the time when the current signal A / D conversion of the sub-microcomputer 30 _S can be completed. In the case of FIG. 4, a current signal A / D conversion end interrupt is issued from the sub-microcomputer 30 _S described later. It has secured the time T1 from the time t ₂ to enter.

Further, in FIG. 5, for example, when the FET H1 of the bridge circuit 22 is PWM-controlled and the FET L2 is continuously ON-controlled, the rising edge of the PWM carrier signal is A /
It is used as the D conversion start timing.

That is, an interrupt enable flag is set at time t ₁ when the current signal A / D conversion synchronizing signal is output, and then A / D conversion is started at time t ₂ when the edge of the PWM carrier signal rises, and A / D conversion is started. to clear the interrupt enable flag after the end of conversion (time t _3).

As shown in FIG. 5, by performing A / D conversion using the rising edge of the PWM carrier signal,
A stable current signal can be obtained without noise.

Next, the main microcomputer 30 _M calculates the motor voltage (step S ₁₀ ) and outputs the motor voltage (PWM output) (step S ₁₁ ).

Next, in step S ₁₂ , it is determined whether or not the time T2 has elapsed, and when it has elapsed, the current signal peak hold clear signal is cleared in step S ₁₃ (time t ₄ in FIG. ₄ , time t _{5 in} FIG. ₅ ). .

After that, an abnormality judgment is made (step S
₁₄ , S ₁₅ ), and if there is an abnormality, the apparatus abnormal stop processing is performed in steps S _{16 to} S ₁₉ . That is, the control signal from the main microcomputer 30 _M to the AND gate 27b is inverted to the low level and the output of the AND gate 27b is set to the low level (enable signal OFF output),
As a result, the FET H1 (or H of the bridge circuit 22 is
The PWM control of 2) is turned off, and after a lapse of a specified time, the control signal from the main microcomputer 30 _M to the AND gate 27a is inverted to low level to turn off the drive of the relay drive circuit 26 (turn off the relay circuit 12a). Then, after confirming that the ignition key switch is off, the processing ends.

Further, the step S₁₅Is YES
If there is no abnormality, step S ₂₀At the ignition
It is determined whether the operation key switch is turned off. So
And if the ignition key switch is on
Step S₃~ S₁₅Is repeatedly executed and turned off
If so, the process ends.

To set the times T1 and T2, for example, compare match registers A and B are used as shown in FIG.

In the sub-microcomputer 30 _S , first, in steps S ₃₁ and S ₃₂ of FIG. 3A, the data in the memory is initialized when the ignition key switch is turned on, and then the step S _{At 33} , A / D conversion of various analog signals is executed.

That is, the torsion bar torque from the torque sensor 7 and the motor voltages (+) and (-) from the voltage monitor circuits 23a and 23b are sequentially and repeatedly taken in to A / D.
Convert.

In this embodiment, the A / D conversion counter is defined as 1 when the torsion bar torque is A / D converted, and the motor voltage (+) is A / D converted. Defines the A / D conversion counter as 2, and defines the A / D conversion counter as 3 when the motor voltage (−) is A / D converted.

The current signal will be described later with reference to FIG.
As shown in (b), A / D conversion is performed at another timing by the rising edge of the current signal A / D conversion synchronizing signal (time t _{1 in} FIGS. 4 and 5).

Next, the sub-microcomputer 30 _S
Step S ₃₄ performs abnormality determination at, S _35, if the abnormality is present the abnormality stop processing apparatus in step S ₃₆ to S _39. That is, the sub-microcomputer 30 _S
From the AND gate 27b to a low level to set the output of the AND gate 27b to a low level (enable signal OFF output), thereby turning off the PWM control of the FET H1 (or H2) of the bridge circuit 22, and thereafter. After the stipulated time has elapsed, the control signal from the sub-microcomputer 30 _S to the AND gate 27a is inverted to low level to turn off the drive of the relay drive circuit 26 (turn off the relay circuit 12a), and then confirm that the ignition key switch is off. Ends the process.

Further, the step S₃₅Is YES
If there is no abnormality, step S ₄₀At the ignition
It is determined whether the operation key switch is turned off. So
And if the ignition key switch is on
Step S₃₃~ S₃₅Is repeatedly executed and turned off
If so, the process ends.

[0051] Incidentally, the execution of the A / D conversion in step S _33, A / D conversion completion every interrupt is applied to the analog signal, A / D conversion completion interrupt processing shown in the execution Fig 3 (c) It is what is done.

Further, the interrupt processing by the rising edge of the current signal A / D conversion synchronizing signal is performed when the edge of the current signal A / D conversion synchronizing signal from the main microcomputer 30 _M rises, as shown in FIG. 3B. , In step S ₅₁ , current signal A / D conversion is started.

Then, the current signal A / D conversion flag is set (step S ₅₂ ), A / D conversion end interrupt permission is issued (step S ₅₃ ), and one cycle of processing is ended.

As described above, at the end of A / D conversion (see FIG.
Step S ₃₃ of (a), an interrupt is applied to the step S ₅₃₎ of FIG. 3 (b), the processing shown in FIG. 3 (c) is performed.

First, in step S ₆₁ , the A / D conversion end interrupt is prohibited (to prevent another interrupt from being input immediately after the interrupt), and in step S ₆₂ the current signal A
It is determined whether the / D conversion flag is set.

[0056] Then asserts the determination result is as if a NO is an interrupt by the processing of step S ₃₃ in FIG. 3 (a), the A / D conversion counter in step S ₆₃ 1
Or not.

If the determination result is YES, the A / D conversion value of the torque signal is fetched in step S ₆₄ , and then the A / D conversion counter is incremented in step S ₆₅ .

Further, the determination result of the step S ₆₃ is NO.
If it is, the A / D conversion counter is set to 2 in step S ₆₉ .
If it is 2, the motor voltage (+) A / D value is fetched in step S ₇₀ and then the process proceeds to step S ₆₅ .

Further, the determination result of the step S ₆₉ is NO.
In the case of, the A / D conversion counter is set to 3 in step S ₇₁ .
If it is 3, the motor voltage (-) A / D value is taken in at step S ₇₂ and then the process proceeds to step S ₆₅ .

If the decision result in the step S ₇₁ is NO (when the A / D conversion counter is 0), the process advances to the step S ₆₅ .

Then, in step S ₆₆ , it is determined whether the A / D conversion counter is 4 or more. If it is not 4 or more, the A / D conversion suitable for the A / D conversion counter is performed in step S ₆₈ . Then, the process for one cycle is completed.

[0062] In the case A / D conversion counter is 4 or more processing proceeds to step S ₆₈ after the 0 A / D conversion counter in step S _67.

In step S ₆₂ , the current signal A
/ If D conversion flag is determined to be set, captures the motor current A / D value in step S _73, then in step S ₇₄ to step S ₆₈ after clearing the current signal A / D conversion flag move on.

As described above, the sub-microcomputer 30
_{On the S} side, normally, processing such as fail safe is executed, but an interrupt is issued to capture the current signal A / D conversion and its A / D converted value, and interrupt after the A / D converted value is captured. It is possible to A / D-convert the analog signal that has been A / D-converted immediately before.

That is, for example, the A / D conversion counter is 1
Current signal A during the A / D conversion of the torque signal
When the / D conversion interrupt occurs, steps _S62 , _S73 ,
After capturing the motor current A / D value by S _74, it is possible to perform the A / D converter A / D conversion counter 1 in step S _68.

[0066] Also, when there is no interruption of the current signal A / D converter, a torque signal in step S ₆₂ to S _72, the motor voltage (+), motor voltage (-) can be sequentially performed each A / D conversion of .

As described above, according to the present embodiment, since the clear signal is not output when the sub-microcomputer 30 _S reads the current value, the sub-microcomputer 30 _S can always read the correct current peak value.

[0068] Further, as shown in FIG. 4, by outputting the main microcomputer 30 _M sub microcomputer 30 reading instruction signal to _S at the same time as the current peak value read in, the sub microcomputer 30 _S reads the current peak value Can increase the time available.

Next, when the sub-microcomputer 30 _S reads the current value while the current signal peak hold clear signal is being output, the current value is read again after a lapse of a predetermined time. An example of the (reset means) will be described with reference to the flowchart of FIG.

First, the interruption due to the rising edge of the current signal A / D conversion synchronizing signal is performed in step S of FIG. 6B.
_{As in 101} , this is done by setting the current signal A / D conversion synchronization signal edge detection flag.

Then, in steps S ₈₁ and S ₈₂ of FIG. 6A, when the ignition key switch is turned on, the data in the memory is initialized, and then in step S ₈₃ the current signal A / D conversion is performed. It is determined whether or not the sync signal is cleared.

If the current signal A / D conversion synchronizing signal is cleared, the current signal A / D is determined in step S ₈₄ .
After clearing the D conversion synchronizing signal edge detection flag, the A / D conversion of each analog signal described above is performed (step S ₈₅ ).

Next, in step S ₈₆ , the current signal A / D
It is determined whether or not the conversion sync signal edge detection flag is set, and in the case of YES (that is, while the current signal A / D conversion sync signal is cleared by the main microcomputer 30 _M , the sub-microcomputer 30
_{If S} is carried out to load the current value), Step S _{8 7}
At, the current signal is again A / D converted and the current value is read.

After that, an abnormality judgment is made (steps S ₈₈ and S ₈₉ ), and if there is an abnormality, an abnormal stop process of the apparatus is performed in steps S _{90 to} S ₉₃ . That is, the control signal from the sub-microcomputer 30 _S to the AND gate 27b is inverted to low level, and the output of the AND gate 27b is set to low level (enable signal OFF output),
As a result, the FET H1 (or H of the bridge circuit 22 is
The PWM control of 2) is turned off, and after a stipulated time has elapsed, the sub-microcomputer 30 _S turns the AND gate 2
The control signal to 7a is inverted to the low level to turn off the drive of the relay drive circuit 26 (the relay circuit 12a is turned off), and then it is confirmed that the ignition key switch is off, and the process ends.

Further, the step S₈₉Is YES
If there is no abnormality, step S ₉₄At the ignition
It is determined whether the operation key switch is turned off. So
And if the ignition key switch is on
Step S₈₃~ S₈₉Is repeatedly executed and turned off
If so, the process ends.

As described above, when the sub-microcomputer 30 _S actually reads the current value, since the clear signal is not output, the sub-microcomputer 30 _S does not read the low current value because the voltage drops due to the clear signal. Can always read the peak current value.

When the current value is read by the reset function of this embodiment, the main microcomputer 3
0 _M and the sub-microcomputer 30 _S do not have exactly the same read timing, but since the processing is executed by high-speed synchronization by the computer, the peak-held current signal can be read and there is no problem.

The reading instruction signal (current signal A / D conversion synchronizing signal) output function and the current peak value clear signal (current signal peak hold clear signal) output function, which are executed by the main microcomputer 30 _M, and the sub-microcomputer are also provided. The reset function executed by the computer 30 _S is
The processing is not limited to the flowcharts of FIGS. 2, 3, and 6, and the processing may be performed according to other flowcharts that execute the same function.

Further, the present invention is not limited to being applied to the assist motor of the electric power steering device, but may be applied to other devices having a peak hold circuit, and in that case, the same operation and effect as described above can be obtained. .

[0080]

As described above, according to the present invention as set forth in claims 1 to 4, a single peak hold circuit can always supply a correct detection value to a plurality of control devices. , The current peak value can always be read. (2) According to the present invention as set forth in claim 2, a time during which the second control device can read the current peak value (from the start of reading the current peak value of the first control device to the output of the clear signal) Can be taken for a long time. (3) According to the third aspect of the present invention, since the clear signal is not output when the second control device reads the current value, the second control device can always read the current peak value. (4) According to the present invention described in claim 4, in the electric power steering device, it is possible to perform appropriate current feedback control with a correct current peak value.
Therefore, the steering feeling is improved by the good current feedback control, and erroneous determination does not occur in the fail safe control or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment in which the present invention is applied to an electric power steering device.

FIG. 2 is a flow chart for reading a current value of the main microcomputer according to the embodiment of the present invention.

FIG. 3 is a flow chart for reading a current value of the sub-microcomputer according to the embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the main part of the embodiment of the present invention.

FIG. 5 is a time chart of various signals according to another embodiment of the present invention.

FIG. 6 is a flow chart for reading a current value of the sub-microcomputer according to another embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example of an electric power steering device.

[Explanation of symbols]

1 ... Steering wheel 7 ... Torque sensor 8 ... Assist motor 12a ... Relay circuit 13 ... Battery 21 ... Current detecting resistor 22 ... Bridge circuits 23a, 23b ... Voltage monitor circuit 24 ... Peak hold circuit 25 ... Operational amplifier 26 ... Relay drive circuit 27a ～27D ... aND gates 28a to 28d ... predriver 30 _M ... main microcomputer 30 _S ... sub microcomputer H1, H2, L1, L2 ... FET

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 3D033 CA03 CA16 CA20 CA21 CA27                 5H571 AA03 BB07 CC02 EE02 GG04                       GG05 HA09 HB01 HC02 JJ03                       JJ06 JJ16 JJ17 JJ18 KK06                       LL22 LL23 MM08

Claims (4)

[Claims] 1. A peak hold circuit for holding a maximum value of a current flowing through the circuit as a current peak value, a first control device and a second control device for reading the current peak value held by the peak hold circuit, A current read instruction means provided in the first control device for outputting the current peak value read instruction signal to the second control device; and a current read instruction means provided in the first control device. Clear signal output means for outputting a clear signal of the current peak value to the peak hold circuit after a time required for reading the current peak value of the second control device has elapsed after the current read instruction signal has been output. A current value detection device characterized by being provided. 2. The current read instruction means is the first
At the same time as reading the current peak value of the controller,
The current value detection device according to claim 1, wherein the read instruction signal is output to the control device. 3. A peak hold circuit for holding a maximum value of a current flowing through the circuit as a current peak value, a first control device and a second control device for reading the current peak value held by the peak hold circuit, A clear signal output means provided in the first control device for outputting a clear signal of the current peak value to the peak hold circuit; and a clear signal output means provided in the second control device for providing a clear signal by the clear signal output means. The second when the output is
A current value detecting device, comprising: a reset unit that causes the control device to read the current value again after a predetermined time has elapsed when the control device reads the current value. 4. An assist motor for generating an assist torque for assisting a steering torque is provided, wherein the peak hold circuit holds a maximum value of a drive current of the assist motor as a current peak value, and the first control device comprises: The current value detection device according to claim 1, 2 or 3, wherein the current control device includes a main microcomputer, and the second control device includes a sub-microcomputer.