JP2003249653A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variations in an on-voltage between elements while trade-off between the on-voltage and turn-off loss is ensured excellently. <P>SOLUTION: Peak concentration of activated impurities of a p-collector layer 8 of IGBT is set to be at least 2×10<SP>17</SP>cm<SP>-3</SP>and at most 2×10<SP>18</SP>cm<SP>-3</SP>. As a result, the variations in the on-voltage is reduced between the elements while the trade-off between the on-voltage and the turn-off loss is ensured excellently. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for a power conversion device or the like.

[0002]

2. Description of the Related Art In recent years, IGB withstand voltage of 600 to 1200V
T (Insulated Gate Bipolar T)
In a MOS-controlled power semiconductor device such as a transistor, an FZ (Floating Zone) substrate, which is cheaper than an epitaxial substrate, is used to reduce energy loss during operation and wafer cost.
A technology for manufacturing a device by processing the thickness to about 200 μm for a 1200V product and about 100 μm for a 600V product has been developed.

In this withstand voltage class IGBT, after a gate portion and an emitter portion are formed on the front surface side of an FZ wafer, the back surface side of the wafer is mechanically or chemically removed to obtain an optimum wafer thickness, NPT (Non Punch-Thro) manufactured by performing boron ion implantation on the back surface and then performing activation heat treatment at about 350 ° C. to 450 ° C.
Ugh) type NPT-IGBTs are receiving attention.

FIG. 6 is a cross-sectional view of an essential part of a conventional NPT-IGBT. An FZ substrate is used as the n semiconductor substrate 100, the thickness W thereof is set to about 100 μm, and the impurity peak concentration of the p collector layer 8a is changed to improve the trade-off between the turn-off loss and the on-voltage (VCE (sat)).
It is set to 1 × 10 ¹⁷ cm ⁻³ . In the following description, the impurity peak concentration means the peak value of the activated impurity concentration after performing the activation heat treatment after the ion implantation.
In the figure, 1 is an n drift region, 2 is a p well region, 3
Is an n emitter region, 4 is a gate insulating film, 5 is a gate electrode, 6 is an interlayer insulating film, 7 is an emitter electrode, 9 is a collector electrode, and 10 is a contact hole.

[0005]

However, 1 × 10 ¹⁷ c
At the impurity peak concentration of m ⁻³ , the trade-off between the on-voltage and turn-off loss of the NPT-IGBT can be improved,
There is a problem that variations in on-voltage become large between elements. This is because the contact resistance value between the p collector layer 8a and the collector electrode 9 varies when the impurity concentration of the p collector layer 8a decreases.

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device in which variations in on-voltage between elements are small while ensuring good trade-off between on-voltage and turn-off loss. .

[0007]

[Means for Solving the Problems]
To form a surface layer on the first main surface side of the first conductivity type semiconductor substrate.
First conductivity type having a higher impurity concentration than the semiconductor substrate formed
A first region, and a first electrode formed on the first region,
A second main surface formed on the second main surface side of the semiconductor substrate;
A second region of conductivity type and a second electrode formed on the second region.
A semiconductor device having a pole, the active region of the second region.
Concentrated impurity peak concentration is 2 × 10 ¹⁷cm^-3Above 2
× 10¹⁸cm^-3It should be as follows.

A second conductivity type well region selectively formed in the surface layer of the first major surface of the first conductivity type semiconductor substrate, and a first region selectively formed in the surface layer of the well region. An emitter region of one conductivity type, a gate electrode formed on the well region sandwiched between the emitter region and the semiconductor substrate via a gate insulating film, an emitter electrode formed on the emitter region, In a semiconductor device including a second conductivity type collector region formed in a surface layer of a second main surface of a semiconductor substrate and a collector electrode formed on the collector region, an activated impurity peak of the collector region The concentration is set to 2 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less.

A second conductivity type well region selectively formed in the surface layer of the first major surface of the first conductivity type semiconductor substrate and a trench groove penetrating the well region and reaching the semiconductor substrate. A gate insulating film formed to cover the side wall and the bottom, a gate electrode formed to fill the trench groove, and an emitter region selectively formed on the surface layer of the well region in contact with the trench groove. An emitter electrode formed on the emitter region, and a second conductivity type collector region formed on a surface layer of the second main surface of the semiconductor substrate,
In a semiconductor device having a collector electrode formed on the collector region, the activated impurity peak concentration of the collector region is 2 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸
It should be below cm ^-3 .

The ion species implanted to form the collector region may be boron ions. As described above, the impurity peak concentration of the p-type collector layer is set to 2 × 1.
By setting it to 0 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less, it is possible to significantly reduce the variation in the on-voltage.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In the following description, n is n-type, p is p
Of course, the conductivity type may be reversed. The same parts as those in FIG. 6 are designated by the same reference numerals. Figure 1
1 is a cross-sectional view of essential parts of a semiconductor device of a first embodiment of the present invention. This semiconductor device is a planar type NPT-IGBT. This figure corresponds to FIG.

A p well region 2 is formed on the surface layer of one main surface of the n semiconductor substrate 100, an n emitter region 3 is formed on the surface layer of the p well region 2, and this n emitter region 3 is formed.
A gate electrode 5 is formed on the p well region 2 sandwiched between the n semiconductor substrate 100 and the gate insulating film 4. An interlayer insulating film 6 is covered thereover, and a contact hole 10 is formed in the interlayer insulating film 6 to form an emitter electrode 7 which is in contact with the n emitter region 3.

A p collector layer 8 is formed on the surface layer of the other main surface of the n semiconductor substrate 100, and a collector electrode 9 is formed on the p collector layer 8. In the n semiconductor substrate 100, a portion sandwiched between the p well region 2 and the p collector region 8 is the n drift region 1. The impurity peak concentration of the p collector layer 8 (which is the activated impurity peak concentration) is 2 × 10 ¹⁷ c
It is not less than m ^{−3 and not} more than 2 × 10 ¹⁸ cm ⁻³ . The thickness W of the n semiconductor substrate is about 50 μm to 200 μm depending on the breakdown voltage class.

The p collector layer 8 is formed by ion implantation of boron and heat treatment, and the heat treatment temperature is set to 350 ° C. to 450 ° C. By setting the impurity peak concentration of the p-collector layer 8 to 2 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less, a good trade-off between the on-voltage and the turn-off loss can be obtained, while FIG. As shown in b), it is possible to reduce variations in the on-voltage between the elements.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor device according to the second embodiment of the present invention. This semiconductor device is a trench type NPT-IGBT. A p-well region 2 is formed in a surface layer on one main surface of the n semiconductor substrate 100, and a trench 11 that penetrates the p-well region 2 and reaches the n semiconductor substrate 100 is formed. A gate insulating film 4 is formed, and then the trench 11 is filled with polysilicon to form a gate electrode 5. An n emitter region 3 that contacts the gate oxide film 4 on the sidewall of the trench 11 is formed in the surface layer of the p well region 2, an interlayer insulating film 6 is covered thereover, and a contact hole 10 is formed in the interlayer insulating film 6. An emitter electrode 7 that contacts the n emitter region 3 is formed.

A p collector layer 8 is formed on the surface layer of the other main surface of the n semiconductor substrate 100, and a collector electrode 9 is formed on the p collector layer 8. In the n semiconductor substrate 100, a portion sandwiched between the p well region 2 and the p collector region 8 is the n drift region 1. Similar to FIG. 1, the impurity peak concentration of the p collector layer 8 (the activated impurity peak concentration)
^Is 2 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less. The thickness W of the n semiconductor substrate is about 50 μm to 200 μm depending on the breakdown voltage class.

The p collector layer 8 is formed by ion implantation of boron and heat treatment, and the heat treatment temperature is set to 350 ° C. to 450 ° C. By setting the impurity peak concentration of the p-collector layer 8 to 2 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less, a good trade-off between the on-voltage and the turn-off loss can be obtained, while FIG. As shown in b), it is possible to reduce variations in the on-voltage between the elements.

Similar effects can be expected when the present invention is applied to the p anode layer of a diode. Figure 3
FIG. 2 is an IV curve of the semiconductor device of FIG. 1, where (a) shows the impurity peak concentration of the p collector layer is 1 × 10 ¹⁷ cm ⁻³ , and (b) shows the impurity peak of the p collector layer. This is the case where the concentration is 2 × 10 ¹⁷ cm ⁻³ . The vertical axis shows the current (IC:
Collector current), the horizontal axis is the on-voltage (VCE (sat)
: Saturation voltage between collector and emitter).
All are IV curves obtained by measuring 10 semiconductor devices of 600V class.

In FIG. 3A, the on-voltage at 30 A is
1.95V to 2.18V, which is a variation (maximum value-
The minimum value) is 0.23V. This variation is 0.04 V when expressed as a standard deviation (1σ). In the figure (b),
Similarly, the ON voltage at 30 A is 1.66 V to 1.73 V.
At V, the variation (maximum value-minimum value) is 0.03V. The variation is 0.015 V when expressed as a standard deviation.

From this, the same figure (b) is shown in the same figure (a).
It can be seen that the variation and the standard deviation are smaller than those of. Furthermore, the number of samples to be tested is increased to 40, the on-voltage (VCE (sat)) at 20 A is measured, and the statistical processing is shown in Table 1.

[0021]

[Table 1] From this table, by setting the impurity peak concentration to 2 × 10 ¹⁷ cm ⁻³ , the variation is 0.040 V to 0.017 V while ensuring the on-voltage in the case of 1 × 10 ¹⁷ cm ^−3.
You can see that it has improved to. From this, it is understood that the variation in the on-voltage can be reduced while maintaining the good trade-off between the on-voltage and the turn-off loss.

The same effect can be obtained with the semiconductor device shown in FIG. This is because the present invention relates to the collector layer 8 on the back surface, so that the fact that the gate structure on the front side is a planar type or a trench type does not affect. Further, as described above, the variation in the ON voltage is mainly due to the variation in the contact resistance between the p collector layer 8 and the collector electrode 9, and thus the variation decreases as the impurity peak concentration increases.

The effect of reducing the variation in the on-voltage is obtained regardless of the thickness W of the n semiconductor substrate because it is caused by the variation in the contact resistance. FIG. 4 is a diagram showing the dependence of the turn-off loss ratio and the standard deviation of the on-voltage on the impurity peak concentration. The measured semiconductor device is the case of FIG. 1, and the number thereof is 40. In FIG. 4, the turn-off loss ratio is an average value, and the variation is a standard deviation. The turn-off loss ratio is a value standardized with 2 × 10 ¹⁷ cm ⁻³ as a reference.

From this figure, the impurity peak concentration is 2 × 10.
^If it exceeds 18 cm ^-3 , the turn-off loss becomes too large,
It cannot be put to practical use. On the other hand, the impurity peak concentration is 2 × 10
^When it is less than ¹⁷ cm ⁻³ , the standard deviation of the on-voltage becomes too large. Therefore, the impurity peak concentration is 2 × 10.
^It is preferably ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less. Of course, the same applies to the semiconductor device of FIG.

FIG. 5 is a diagram showing the relationship between the impurity peak concentration and the boron ion implantation amount. Of course, this impurity peak concentration is the activated impurity peak concentration.
The impurity peak concentration is the boron ion implantation amount (dose amount).
And it depends on the activation heat treatment temperature. Impurity peak concentration is 2
The activation heat treatment temperature should be 3 in order to obtain × 10 ¹⁷ cm ^-3.
At 50 ° C., a boron ion implantation amount of 1 × 10 ¹⁵ cm ^-2 or more is required. When the activation heat treatment temperature is raised to 450 ° C., a boron ion implantation amount of 7 × 10 ¹³ cm ^-2 or more is required. Is. Further, when the activation heat treatment temperature is 450 ° C., the boron ion implantation amount is required to be 1 × 10 ¹⁵ cm ⁻² or less in order to set the impurity peak concentration to 2 × 10 ¹⁸ cm ⁻³ or less. That is, the activation heat treatment temperature is set to 350 ° C.
To 450 ° C, the impurity peak concentration should be 2 × 10 ¹⁷
In order to set the cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ , the boron ion implantation amount may be determined using this figure according to the activation heat treatment temperature.

[0026]

According to the present invention, the activated impurity peak concentration of the collector layer is from 2 × 10 ¹⁷ cm ⁻³ to 2 × 10.
^By setting the range to ¹⁸ cm ⁻³ , it is possible to reduce the variation in the on-voltage while maintaining a good trade-off between the turn-off loss and the on-voltage.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a main portion of a semiconductor device according to a second embodiment of the present invention.

3 is an IV curve of the semiconductor device of FIG.
(A) shows that the impurity peak concentration of the p collector layer is 1 × 10 ¹⁷
In the case of cm ⁻³ , (b) is a diagram when the impurity peak concentration of the p collector layer is 2 × 10 ¹⁷ cm ⁻³

FIG. 4 is a diagram showing impurity peak concentration dependence of turn-off loss ratio and standard deviation of on-voltage.

FIG. 5 is a diagram showing a relationship between an impurity peak concentration and a boron ion implantation amount.

FIG. 6 is a sectional view of a main part of a conventional NPT-IGBT.

[Explanation of symbols]

1 n drift region 2p well region 3 n emitter region 4 Gate insulation film 5 Gate electrode 6 Interlayer insulation film 7 Emitter electrode 8,8a collector layer 9 Collector electrode 10 contact holes 11 trench 100 n semiconductor substrate Thickness of W n semiconductor substrate

Claims (4)

[Claims] 1. A first conductive type semiconductor substrate having a higher impurity concentration than the semiconductor substrate formed in a surface layer on the first main surface side.
A first region of conductivity type, a first electrode formed on the first region, a second region of second conductivity type formed in a surface layer on the second main surface side of the semiconductor substrate, In a semiconductor device having a second electrode formed on two regions, the activated impurity peak concentration of the second region is 2 × 1.
A semiconductor device having a size of 0 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁸ cm ^-3 or less. 2. A well region of a second conductivity type selectively formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, and a well region selectively formed in a surface layer of the well region. An emitter region of one conductivity type, a gate electrode formed on the well region sandwiched between the emitter region and the semiconductor substrate via a gate insulating film, an emitter electrode formed on the emitter region, A semiconductor device comprising a second conductivity type collector region formed in a surface layer of a second main surface of a semiconductor substrate, and a collector electrode formed on the collector region, wherein an activated impurity peak of the collector region Concentration is 2
A semiconductor device having a size of not less than × 10 ¹⁷ cm ^{-3 and not} more than 2 × 10 ¹⁸ cm ^-3 . 3. A well region of a second conductivity type selectively formed in a surface layer of a first main surface of a semiconductor substrate of a first conductivity type, and a trench groove penetrating the well region and reaching the semiconductor substrate. A gate insulating film formed to cover the side wall and the bottom, a gate electrode formed to fill the trench groove, and an emitter region selectively formed in contact with the trench groove on the surface layer of the well region. An emitter electrode formed on the emitter region, a second conductivity type collector region formed on the surface layer of the second main surface of the semiconductor substrate, and a collector electrode formed on the collector region. In the semiconductor device, the activated impurity peak concentration of the collector region is 2
A semiconductor device having a size of not less than × 10 ¹⁷ cm ^{-3 and not} more than 2 × 10 ¹⁸ cm ^-3 . 4. The semiconductor device according to claim 1, wherein the ion species implanted to form the second region or the collector region is boron ion.