JP2003249566A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which prevents capacitance electrodes from deforming due to stress and has a high-reliability capacitance element, having stable characteristics. <P>SOLUTION: MOS-type capacitance element 20, having a comparatively large area has a polysilicon layer 23 formed on an N-type lightly-doped region (N-region) 21 via a capacitor insulation film 22 (e.g., oxide film) on a semiconductor substrate 11. The N-region 21 forms one electrode of the capacitance element 20, and the polysilicon layer 23 forms the other electrode thereof. This layer 23 forming the other electrode is the same layer as a polysilicon layer 141 in a MOS transistor 10, hence no silicide layer is selectively formed therefor, via a silicide process is taken to obtain a Ti silicide layer 142. An oxide film 24 is formed as a buffer film on the polysilicon layer 23. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element, especially a MOS, in an integrated circuit using a silicide process.
The present invention relates to a semiconductor device having a capacitive element and a method for manufacturing the same.

[0002]

2. Description of the Related Art Speeding up of operation in a semiconductor integrated circuit,
Along with the decrease in resistance, the gate of the MOS element and the polysilicon wiring member are generally configured such that the upper portions thereof are silicified with a refractory metal. For products with analog circuits using the silicide process, MOS
The configuration of the mold capacitive element is also included.

FIG. 7 is a sectional view showing the structure of a conventional capacitive element provided in a semiconductor integrated circuit. Capacitance element 100
In the above, a polysilicon layer 104 in which a metal silicide layer 105 is formed is formed in a predetermined low concentration impurity region 102 on the semiconductor substrate 101 with a capacitor insulating film 103 (for example, an oxide film) interposed therebetween. Polysilicon layer 1
A spacer 106 is formed on the side wall 04, and a metal silicide layer 105 is also formed on the peripheral exposed portion of the substrate. The low concentration impurity region 102 serves as one capacitor electrode, and the polysilicon layer 104 serves as the other capacitor electrode. Wiring is led out through both the electrodes through the metal silicide layer 105.

According to the capacitive element 100 having the above structure, the polysilicon layer 104 and the metal silicide layer 105 are in the same step as the formation of the gate electrode of the MOS transistor (not shown). Therefore, the metal silicide layer 105 is provided even in a MOS type capacitive element having a relatively large area, for example, a capacitive element whose one side is several hundred μm or more.

[0005]

In the above structure, the silicide layer 10 is used in the capacitive element having a relatively large area.
The presence of a stress of 5 is noticeable to some extent. Depending on the degree, reliability of the capacitor insulating film of the MOS capacitive element may deteriorate.

The present invention has been made in consideration of the above circumstances, and prevents deterioration of reliability of a capacitor insulating film due to stress, and a semiconductor device having a highly reliable capacitive element with stable characteristics and a semiconductor device thereof. It is intended to provide a manufacturing method.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a MOS transistor having a gate electrode containing metal silicide; and an impurity diffusion formed on the same substrate as the MOS transistor. And a capacitor insulating film and a capacitive element including the same layer as the gate electrode on the capacitor insulating film and the other electrode consisting only of a polysilicon layer.

According to the above semiconductor device of the present invention, the capacitive element included in the silicide process constitutes the other electrode of only the polysilicon layer without the silicide layer.
In the case where the capacitor has a large area, the influence of the stress of the silicide layer is eliminated and the reliability is improved.

A method of manufacturing a semiconductor device according to [Claim 2] of the present invention involves manufacturing a MOS type transistor including a metal silicide in a gate electrode on a semiconductor substrate, the method being selective on the semiconductor substrate. A step of forming an impurity diffusion region to be one electrode of the capacitor in the step of forming a capacitor insulating film on the impurity diffusion region,
Forming a polysilicon layer in the same layer as the gate electrode on the capacitor insulating film and patterning the gate electrode of the MOS transistor and the other electrode of the capacitor; and at least on the polysilicon layer on the capacitor insulating film and its A step of selectively forming a buffer film in the vicinity thereof, a step of forming a refractory metal layer by sputtering on at least the polysilicon layer to be the gate electrode, and a step of siliciding the refractory metal layer on the polysilicon layer. And a step of removing the unreacted refractory metal layer in the buffer film.

According to the method for manufacturing a semiconductor device of the present invention, the formation of the capacitive element included in the silicide process prevents the formation of the silicide layer by the buffer film,
The other electrode of only the polysilicon layer without the silicide layer is realized. When it has a large area as a capacitive element,
The influence of the stress of the silicide layer can be eliminated, which contributes to the improvement of reliability.

A semiconductor device according to [Claim 3] of the present invention is a MOS type transistor having a gate electrode containing metal silicide, a one electrode made of an impurity diffusion region formed on the same substrate as the MOS type transistor, and A capacitor insulating film and a capacitive element formed of the other electrode group including a region in which a polysilicon layer containing the same metal silicide as the gate electrode on the capacitor insulating film is divided into a plurality of regions.

According to the above-described semiconductor device of the present invention, in the capacitive element included in the silicide process, the other electrode group is formed by the region in which the polysilicon layer including the silicide layer is divided into a plurality of regions. When a large area is required for the capacitive element, it is divided into a plurality of pieces in order to reduce the influence of the stress of the silicide layer and contributes to the improvement of reliability.

A method of manufacturing a semiconductor device according to [Claim 4] of the present invention involves manufacturing a MOS type transistor having a gate electrode containing a metal silicide on a semiconductor substrate, and the method is selective on the semiconductor substrate. A step of forming an impurity diffusion region to be one electrode of the capacitor in the step of forming a capacitor insulating film on the impurity diffusion region,
Forming a polysilicon layer in the same layer as the gate electrode on the capacitor insulating film and patterning the gate electrode of the MOS transistor and the other electrode group of the capacitor composed of a plurality of divided regions; and the polysilicon layer. The method further comprises: a step of forming a refractory metal layer on the upper surface by sputtering; and a heat treatment step of siliciding the refractory metal layer on the polysilicon layer.

According to the above-described method for manufacturing a semiconductor device of the present invention, a plurality of other electrodes having a silicide layer are realized by forming a capacitive element included in a silicide process. When the capacitor has a large area, the influence of the stress of the silicide layer can be minimized,
Contributes to improved reliability.

In the method of manufacturing a semiconductor device according to the above [claim 2] or [claim 4], the capacitor insulating film is formed in the same step as the gate insulating film of the MOS transistor. And Alternatively,
Part of the capacitor insulating film and the gate insulating film of the MOS transistor are formed in the same process. Alternatively, the capacitor insulating film is formed in a different process from the gate insulating film of the MOS transistor.

[0016]

1 is a cross-sectional view showing the structure of a main part in which a MOS type capacitive element included in a semiconductor device according to a first embodiment of the present invention is arranged. In the element region 12 (121, 122) on the P-type semiconductor substrate 11, the N-channel MOS transistor 10 and the MOS capacitance element 20 are provided. The P-type semiconductor substrate 11 is made of N (not shown).
Various forms such as a P-type well on the mold substrate, an epitaxial P-type layer, and the like are conceivable.

The MOS transistor 10 has a gate electrode 14 in which a Ti silicide layer 142 is formed on a polysilicon layer 141 via a gate oxide film 13, and a spacer 16 is provided. As a result, the LDD is formed on the substrate 11 with the channel region below the gate electrode 14 separated.
Source / drain regions 15 having a (Lightly Doped Drain) structure are formed. A Ti silicide layer 142 is formed on the source / drain region 15 with the spacer 16 therebetween. The Ti silicide layer 142 takes the form of so-called self-aligned silicide.

The MOS type capacitance element 20 is composed of a semiconductor substrate 11
A polysilicon layer 23 is formed in the upper N-type low-concentration impurity region (N ⁻ region) 21 with a capacitor insulating film 22 (for example, an oxide film) interposed therebetween. One electrode of the MOS capacitor element 20 is an N ⁻ region 21, and the other electrode is composed of a polysilicon layer 23. The other electrode of the polysilicon layer 23 is the same layer as the polysilicon layer 141 in the MOS transistor 10, and has a structure in which a silicide process is performed but a silicide layer is not selectively formed. The spacer 1 is formed on the side wall of the polysilicon layer 23 as described above.
6 is formed, and an oxide film 24 as a buffer film described later is formed on the polysilicon layer 23. The oxide film 24 and the spacer 16 are formed around the polysilicon layer 23.
The surface of the N ⁻ region 21 that is not covered with Ti is the Ti silicide layer 14
2 is formed.

2 (a) and 2 (b) are respectively shown in FIG.
3 is a cross-sectional view showing the main part of the structure shown in FIG.
FIG. 3 is a plan view showing a configuration example of a MOS type capacitive element 20. The same parts as those in FIG. 1 are designated by the same reference numerals. Figure 2 (a)
First, on the surface of the element region 121 of the substrate 11, N ⁻
A region 21 is formed. The N ⁻ region 21 has, for example, P (phosphorus) as an impurity, an acceleration voltage of 100 keV, and a dose amount of 3 ×.
It is formed at about 10 ¹³ cm ^-2 . Next, the capacitor insulating film 22 is formed on the N ⁻ region 21. Capacitor insulating film 2
2 may be formed in the same step as the gate oxide film 13, or may be formed by adding a film forming step, or in a completely different step. Here, an oxide film having a thickness of about 8 nm is formed by the same process as the gate oxide film 13 by the thermal oxidation method.

Next, CVD (Chemical Vapor Depositio)
n) method to cover the capacitor insulating film 22 and the gate oxide film 13 with a predetermined thickness (150 to 400 nm).
The polysilicon layer PLY in the range). Next, the polysilicon layer PLY is patterned through a lithography process to become a polysilicon layer 23 on the capacitor insulating film 22 and a polysilicon layer 141 on the gate oxide film 13. Next, source / drain extension regions 151 for forming an LDD structure are formed by ion implantation. Next, for example, an oxide film is deposited to a predetermined thickness by the CVD method, and the spacer 16 is formed through anisotropic etching. Then, the source / drain regions 15 are formed.
Next, the oxide film 24 is formed with a thickness of several tens of nm by the CVD method.
Then, the formed resist RP is used as a mask to etch, and the oxide film 24 is selectively left on the polysilicon layer 23 as a buffer film.

Next, as shown in FIG. 2B, for example, T
i is sputtered. Then, heat treatment for silicidation and chemical removal of unreacted Ti are performed. This allows
Ti on the polysilicon layer 141 and the source / drain region 15 that separates the spacer 41 is silicided to form Ti.
A silicide layer (142) is formed. Ti on the oxide film 24 is not reacted and is removed. As a result, the configuration as shown in FIG. 1 is obtained.

In FIG. 3, the MOS type capacitance element 20 is
One side of the polysilicon layer 23 is several hundred μm or more (for example, 50
0 μm). A plurality of contacts with the one electrode connected to the predetermined high concentration region in the N ⁻ region 21 and the lead wire 3
1 is formed. Further, a contact region 32 for extraction is also formed on the other electrode side of the polysilicon layer 23.

According to the configuration of the above embodiment, in the formation of the capacitive element included in the silicide process, the formation of the silicide layer is eliminated by the oxide film 24 serving as the buffer film, and the other electrode of only the polysilicon layer (23) is realized. To do. As a result, one side of the polysilicon layer 23 has an M of several hundred μm or more.
The OS type capacitive element 20 is formed. It is particularly useful for circuits that do not require high frequency operation. In addition, when the capacitance element has a large area as described above, the influence of the stress of the silicide layer can be eliminated, which contributes to the improvement of reliability.

The P-type semiconductor substrate 11 may be replaced by an N-type semiconductor substrate. The MOS transistor 10 may have a P-channel configuration. Furthermore, M
The one electrode of the OS type capacitance element 20 is not limited to the N ⁻ region 21. A P-type low-concentration region (P ⁻ region) may be considered. The metal forming the silicide layer is not limited to Ti, but Co
And so on. There are various other conceivable examples of the capacitor insulating film 22, and a material exhibiting ferroelectric characteristics may be used.

FIG. 4 is a cross-sectional view showing the configuration of the main part in which the MOS type capacitance element included in the semiconductor device according to the second embodiment of the present invention is arranged. The same parts as those in FIG. 1 are designated by the same reference numerals. The P-type semiconductor substrate 11 has the same structure as that shown in FIG. 1, and various other forms are possible. The N-channel MOS type transistor 10 has the same configuration as that of FIG. 1, and a P-channel MOS type transistor can be considered depending on the substrate (base) or well.

The MOS type capacitance element 60 is formed on the semiconductor substrate 11
The upper N-type low-concentration impurity region (N ⁻ region) 61 is covered with a capacitor insulating film 62 (for example, an oxide film) through,
The polysilicon layer 631 including the silicide layer 632 is divided into a plurality of parts. One electrode of the MOS-type capacitance element 60 is an N ⁻ region 61, the other electrode is divided into a plurality of polysilicon layers 631 and Ti on the upper portion thereof.
It is composed of an electrode group in which the silicide layer 632 is integrated. Spacers 16 are formed on the sidewalls of the polysilicon layer 631 of each electrode group. The other electrode formed of the polysilicon layer 631 and the Ti silicide layer 632 above the polysilicon layer 631 is MO.
It is in the same layer as the gate electrode 14 in the S-type transistor 10 and similarly undergoes a silicide process.

FIGS. 5 (a) and 5 (b) are respectively shown in FIG.
6 is a cross-sectional view showing the main part of the structure shown in FIG.
FIG. 6 is a plan view showing a configuration example of a MOS type capacitive element 60. The same parts as those in FIG. 4 are designated by the same reference numerals. Figure 5 (a)
First, on the surface of the element region 121 of the substrate 11, N ⁻
A region 61 is formed. The N ⁻ region 61 has, for example, P (phosphorus) as an impurity, an acceleration voltage of 100 keV, and a dose of 3 ×
It is formed at about 10 ¹³ cm ^-2 . Next, the capacitor insulating film 62 is formed on the N ⁻ region 61. Capacitor insulating film 6
2 may be formed in the same step as the gate oxide film 13, or may be formed by adding a film forming step, or in a completely different step. Here, an oxide film having a thickness of about 8 nm is formed by the same process as the gate oxide film 13 by the thermal oxidation method.

Next, CVD (Chemical Vapor Depositio)
n) method so as to cover the capacitor insulating film 62 and the gate oxide film 13 with a predetermined thickness (150 to 400 nm).
The polysilicon layer PLY in the range). Next, the polysilicon layer PLY is patterned through a lithography process. As a result, a polysilicon layer 631 is formed on the capacitor insulating film 62, and a polysilicon layer 141 is formed on the gate oxide film 13. Next, source / drain extension regions 151 for forming an LDD structure
Are formed by ion implantation. After that, the ion implantation mask is removed, for example, an oxide film is deposited to a predetermined thickness by the CVD method, and the spacer 16 is formed through anisotropic etching.

Next, as shown in FIG.
After forming the drain region 15, for example, Ti is sputtered. Then, heat treatment for silicidation and chemical removal of unreacted Ti are performed. As a result, Ti on the polysilicon layer 141 and the source / drain region 15 that separates the spacer 41 is silicidized to form a Ti silicide layer (142). In addition, each polysilicon layer 63
Ti on 1 is also silicidized to form a Ti silicide layer (63
2) is formed. As a result, the configuration as shown in FIG. 4 is obtained.

In FIG. 6, the MOS type capacitive element 60 is
Each electrode group composed of the divided polysilicon layer 631 and the Ti silicide layer 632 above it is gathered, and one side of the entire element region 121 is several hundred μm or more (for example, about 500 μm). A plurality of contacts with one electrode connected to the predetermined high concentration region in the N ⁻ region 61 and the lead-out line 81 are formed. The size of the other electrode group having the Ti silicide layer 632 on the top is such that it is hardly affected by stress (in the range of several tens to 100 μm). A contact region 82 for drawing out is formed, and these are collectively connected to the upper conductive layer 83.

According to the semiconductor device of the present invention in the above-described embodiment, the other electrode group composed of a plurality of regions into which the polysilicon layer including the silicide layer is divided is formed in the formation of the capacitive element included in the silicide process. . This allows
As the element region 121, the MOS type capacitive element 60 having one side of several hundred μm or more is formed. As a result, even when a large area is required for the capacitive element, the influence of the stress of the silicide layer can be reduced, and it can be applied to products that require high frequency operation, and the reliability is improved.

It should be noted that the P-type semiconductor substrate 11 may be replaced by an N-type semiconductor substrate as in the first embodiment. The MOS transistor 10 may have a P-channel configuration. Furthermore, the one electrode of the MOS capacitor element 60 is not limited to the N ⁻ region 21. A P-type low-concentration region (P ⁻ region) may be considered. The metal forming the silicide layer is not limited to Ti but may be various metals such as Co. There are various other possibilities for the capacitor insulating film 62, and a material exhibiting ferroelectric characteristics may be used.

[0033]

As described above, according to the present invention, in the capacitive element included in the silicidation process, the other electrode of only the polysilicon layer without the silicide layer is formed.
Alternatively, even if a silicide layer is provided, it is divided to form the other electrode group in which the stress is reduced. As a result,
It is possible to provide a semiconductor device having a highly reliable capacitor element with stable characteristics and a method for manufacturing the same, which prevents deterioration of reliability of the capacitor insulating film due to silicide stress.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a main part in which a MOS capacitor element included in a semiconductor device according to a first embodiment of the present invention is arranged.

2A and 2B are cross-sectional views showing the main part of the structure shown in FIG. 1 during the manufacturing process.

FIG. 3 is a plan view showing a configuration example of the MOS type capacitive element shown in FIG.

FIG. 4 is a cross-sectional view showing a main part configuration in which a MOS type capacitive element included in a semiconductor device according to a second embodiment of the present invention is arranged.

5A and 5B are cross-sectional views showing the main part of the structure shown in FIG. 4 during the manufacturing process.

FIG. 6 is a plan view showing a configuration example of the MOS type capacitive element shown in FIG.

FIG. 7 is a cross-sectional view showing a configuration of a conventional capacitive element provided in a semiconductor integrated circuit.

[Explanation of symbols]

10 ... MOS transistors 11, 101 ... Semiconductor substrate 12 (121, 122) ... Element region 13 ... Gate oxide film 14 ... Gate electrodes 141, 631, 23, PLY, 104 ... Polysilicon layers 142, 632 ... Ti silicide layer 15 Source / drain regions 151 Source / drain extension regions 16, 106 Spacers 20, 60 MOS type capacitive elements 21, 61, 102 Low concentration impurity regions (N ⁻ regions) 22, 62, 103 Capacitor insulating films 24 ... Buffer film (oxide film) 31, 81 ... Contact and lead lines 32, 82 ... Contact region 83 ... Conductive layer RP ... Resist pattern 100 ... Capacitance element 105 ... Metal silicide layer

Claims (7)

[Claims] 1. A MOS transistor having a gate electrode containing metal silicide, a one-side electrode made of an impurity diffusion region formed on the same substrate as the MOS transistor, a capacitor insulating film, and the gate electrode on the same. A semiconductor device comprising: a capacitor element including a layer and the other electrode formed of only a polysilicon layer. 2. A method of manufacturing a MOS transistor including a metal silicide in a gate electrode on a semiconductor substrate, wherein an impurity diffusion region serving as one electrode of a capacitor is selectively formed on the semiconductor substrate. Forming a capacitor insulating film on the impurity diffusion region, forming a polysilicon layer in the same layer as the gate electrode on the capacitor insulating film, and patterning the gate electrode of the MOS transistor and the other electrode of the capacitor A step of selectively forming a buffer film on at least the polysilicon layer on the capacitor insulating film and in the vicinity thereof; and a step of forming a refractory metal layer by sputtering on at least the polysilicon layer to be the gate electrode. And a heat treatment process for siliciding the refractory metal layer on the polysilicon layer. And a step of removing the unreacted refractory metal layer in the buffer film, the method of manufacturing a semiconductor device. 3. A MOS type transistor having a gate electrode containing metal silicide, one electrode made of an impurity diffusion region formed on the same substrate as the MOS type transistor, a capacitor insulating film and the gate electrode on the same. A semiconductor device, comprising: a capacitive element including a second electrode group including a region in which a polysilicon layer containing metal silicide is divided into a plurality of regions. 4. A method of manufacturing a MOS transistor including a metal silicide in a gate electrode on a semiconductor substrate, wherein an impurity diffusion region to be one electrode of a capacitor is selectively formed on the semiconductor substrate. Forming a capacitor insulating film on the impurity diffusion region, forming a polysilicon layer of the same layer as the gate electrode on the capacitor insulating film, and forming a gate electrode of the MOS transistor and a plurality of divided regions. Patterning the other electrode group of the capacitor, a step of forming a refractory metal layer on the polysilicon layer by sputtering, and a heat treatment step for siliciding the refractory metal layer on the polysilicon layer, A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 2, wherein the capacitor insulating film is formed in the same step as the gate insulating film of the MOS transistor. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the capacitor insulating film is partially formed in the same step as the gate insulating film of the MOS transistor. 7. The method of manufacturing a semiconductor device according to claim 2, wherein the capacitor insulating film is formed in a process different from that of the gate insulating film of the MOS transistor.