JP2003249504A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce parasitic capacitance of a bird's beak 4 in a grounded emitter amplifier. <P>SOLUTION: A field oxide film 3 is formed by a PBL method (polysilicon buffered LOCOS method) on an epitaxial layer 2 formed on a semiconductor substrate 1. As a result, sharp bird's beaks 4 are formed the both ends of the field oxide film 3. The parasitic capacitance that generated in reduced owing to the sharp tips of the bird's beaks 4. A base wiring 5 and an interlayer insulating film 6 are coated on each of the field oxide films 3 having the bird's beaks 4. Further, a base region 7 is formed on a region enclosed by the bird's beaks 4, and an emitter region 8 to be embedded in the base region 7 is also formed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for improving high frequency characteristics.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing a conventional NPN type bipolar transistor. N + type semiconductor substrate 10
An N− type epitaxial layer 102 is formed on the first layer 1 by the epitaxial growth method. Field oxide film 1
03 is for separating the elements (isolation),
Alternatively, it is formed by the LOCOS method (local silicon oxidation) in order to reduce the parasitic capacitance. Birds Beak 104
Is located at the end of the field oxide film 103, and is formed in a slender shape like a bird's beak. The base wiring 105 is formed so as to cover the bird's beak 104. The interlayer insulating film 106 covers the base wiring 105. The P type base region 107 is formed so as to partially contact the base wiring 105, and is formed by diffusion from the base wiring 105 to the epitaxial layer 102. The N + type emitter region 108 is buried in the surface of the P + type base region 107 by diffusion. The base electrode 109 and the emitter electrode 110 form a contact hole in the interlayer insulating film 106 and are electrically connected to the base wiring 105 and the emitter region 110, respectively. The collector 111 is connected to the outside from the semiconductor substrate 101.

A grounded-emitter amplifier circuit using a bipolar transistor having the above structure is known. The grounded-emitter amplifier circuit has a feature that the power gain (voltage gain × current gain) can be maximized as compared with the grounded-collector circuit and the grounded-base circuit. Further, it has a feature that the phases of an input signal and an output signal are inverted, and has been mainly used as a transmitter for a mobile phone or the like.

FIG. 5 is a circuit diagram of a grounded-emitter amplifier circuit constructed by using bipolar transistors. 112
Is an NPN transistor, 113 is a base, 114 is a collector, 115 is an emitter, 116 is an input terminal, and 117 is an output terminal. C is a parasitic capacitor existing between the base 113 and the collector 114.

The NPN transistor 112 has a base 113,
It is a bipolar transistor including a collector 114 and an emitter 115. Hereafter, this NPN transistor 112
The operation of will be described. When a high frequency signal is input from the input terminal 116 in the figure, the amplified high frequency signal is output from the output terminal 117. At this time, the phase of the output signal is inverted with respect to the input signal. At this time, most of the input high-frequency signal current is the base 11 of the NPN transistor 112.
Enter 3.

[0006]

However, a part of the current of the input high frequency signal flows into the parasitic capacitor C and is output from the output terminal 117. Therefore, a part of the input high frequency signal is generated by the base 113 of the NPN transistor 112.
The output terminal 1 through the parasitic capacitor C without passing through
Since it is output from 17, there is a loss in amplification of the transistor. As a result, the current gain is lowered and the high frequency characteristics are reduced.

The present invention has been made in view of the above-mentioned drawbacks, and reduces the capacitance of the parasitic capacitor C to increase the input impedance and reduce the amount of current flowing into the parasitic capacitor C. The inventor of the present invention focused on the fact that one of the causes of the increase in the capacitance of the parasitic capacitor C is the thin field oxide film in the bird's beak 104 shown in FIG.

[0008]

The semiconductor device of the present invention comprises:
A semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, and a plurality of bird's beaks having sharp tips on the surface of the epitaxial layer by a polysilicon buffered LOCOS method so that the tips are steeply inclined,
A field oxide film is formed between the field oxide film, a plurality of base wirings formed from the surface of the field oxide film to the epitaxial layer via the tip surface of the bird's beak, and the field oxide film. A base region, an emitter region buried in the base region, an interlayer insulating film covering each of the field oxide film, the base wiring, the base region, and the emitter region, and the above-mentioned base wiring. It is characterized in that it has a base electrode formed on the interlayer insulating film and an emitter electrode similarly formed on the interlayer insulating film above the emitter region.

[0009]

1 is a sectional view showing a conventional grounded-emitter amplifier circuit for a bipolar transistor. N +
On the n-type semiconductor substrate 1 by an epitaxial growth method.
A − type epitaxial layer 2 is formed. The field oxide film 3 is formed by the LOCOS method for separating elements (isolation) or for reducing the parasitic capacitance. In the present embodiment, the N-type semiconductor substrate 1 and the epitaxial layer 2 are exemplified, but the P-type semiconductor substrate and the epitaxial layer may be used. The present invention is characterized in that the bird's beak 4 located at the end of the field oxide film 3 has a steep slope. The base wiring 5 is formed so as to cover the field oxide film 3 and also cover the bird's beak 4 whose tip is steep as described above. The interlayer insulating film 6 covers the base wiring 5. Base area 7
Are formed so as to partially contact the base wiring 5, and are formed by diffusion from the surface of the epitaxial layer 2. The emitter region 8 is buried inside the base region 7 by diffusion. The base electrode 9 and the emitter electrode 10 form contact holes in the interlayer insulating film 6, and the base wiring 5 and
Each of them is electrically connected to the emitter region 10. The collector 11 is connected from the semiconductor substrate 1 to the outside.

Therefore, in the present invention, bird's beak 4
The bird's beak 4
It is possible to reduce the parasitic capacitance C ′ possessed by, especially the parasitic capacitance C ′ at the tip portion. This parasitic capacitance C ′ is deeply related to the thickness of the bird's beak 4 (corresponding to the distance between parallel plates of the capacitor). Generally, the capacitance of a capacitor is inversely proportional to the distance between parallel plates of the capacitor and proportional to its area. Therefore,
In the bird's beak 104 having a slender tip as in the prior art, the distance between the parallel plates becomes smaller and the capacity increases toward the tip. That is, a large amount of electric charge is likely to concentrate on the tip of the bird's beak 104. However, when the tip is steep as in the present invention, the distance between the parallel plates becomes large,
Its parasitic capacitance is reduced.

From the above, the present application has the effect that the parasitic capacitance C'can be reduced by making the tip of the bird's beak 4 steep, that is, by making the tip thick.

Next, with reference to FIGS. 2 to 3, a method of manufacturing the semiconductor device of FIG. 1 will be described in detail. 2 to 3, the same components as those in FIG. 1 are designated by the same reference numerals.

2A will be described. By an epitaxial growth method on the surface of the N + type semiconductor substrate 1,
The N− type epitaxial layer 2 is formed. Then, the silicon oxide film 12 is formed on the surface of the epitaxial layer 2 by the thermal oxidation method or the CVD method. At this time, the film thickness of the silicon oxide film 12 is about 400 ± 40Å. A part of the silicon oxide film 12 forms the field oxide film 3 by the LOCOS method described later.

2B will be described. Figure 2 (A)
A first polysilicon film 13, a silicon nitride film 14, and a resist mask 15 are formed on the surface of the. The first polysilicon film 13 and the silicon nitride film 14 are formed by the thermal CVD method. At this time, the first polysilicon film 13 is about 700 ± 100Å and the silicon nitride film 14 is 1500.
It has a film thickness of about ± 100Å. Next, a photoresist is applied on the surface of the silicon nitride film 14, and a plurality of through holes 16 are formed through mask exposure and development processing, as shown in FIG. At this time, the diameter of the through hole 16 is about 2.2 μm.

2C will be described. Figure 2 (B)
The resist mask 15 on the outermost surface is removed, and the field oxide film 3 is formed by the LOCOS method. The field oxide film 3 is formed by a thermal oxidation method so as to have a film thickness of about 6000 ± 300Å at about 1000 ° C. In addition, a field oxide film 3 with a film thickness of 3000 to 12000Å
May also be formed. However, although an example of the film thickness of the field oxide film 3 is given here, the present application is not limited to these numerical values.

In this embodiment, the silicon nitride film 14 is formed on the first polysilicon film 13 in FIGS. 2A and 2B.
To form. This method is generally called a PBL method (polysilicon buffered LOCOS method).
In the PBL method, the first polysilicon film 13 serves as an etching stopper for the silicon nitride film 14. Also, the first
The first polysilicon film 13 also has a role of relieving the stress between the two by arranging the polysilicon film 13 of 1) between the epitaxial layer 2 and the silicon nitride film 14. Therefore, the first polysilicon film 13 suppresses lateral growth of the tip of the bird's beak 4 by the L OCOS method.
A feature of the present invention is to make the tip of the bird's beak 4 steep by using the PBL method.

Next, FIG. 3A will be described. Figure 2
After the state of (C), the silicon nitride film 14 and the polysilicon 13 are removed. Then, the second polysilicon film 17 is formed on the surface. At this time, the second silicon film 17
Forms about 2000 ± 200Å. Next, boron fluoride (BF ₂ ) is ion-implanted into the second silicon film 17 under the conditions of an ion acceleration of 30 keV and a dose amount of 4.0 × 10 ¹⁵ cm ⁻² . As a result, the second silicon film 17 becomes the base wiring 5.

Next, FIG. 3B will be described. Figure 3
A resist mask (not shown) for forming a contact hole is formed at a desired position on the surface of (A), and the second silicon film 17 is etched to form the base wiring 5. After that, again, a second silicon nitride film 18 for oxidation resistance is applied on the entire surface by 1000 ± 100Å, and TEOS1
9 to 5000 ± 500Å. TEOS (tetra ethyl
ortho silicate) is a kind of liquid source, and is used for depositing a film with good coverage. After that, a photoresist (not shown) is applied from the outermost surface, mask exposure,
Through development processing, through holes are formed at desired positions so as to be arranged between the two field oxide films 3. Then, the TEOS 19 and the second silicon nitride film 18 are etched using the photoresist as a mask. Then, boron fluoride at 30 keV and a dose amount of 1.5 × 10 ¹⁴ c
Ions are implanted under the condition of m ⁻² to form the base region 7.

Next, FIG. 3C will be described. Figure 3
The photoresist is removed from the surface of (B) and arsenic is removed.
(AS) ion acceleration 100 keV, dose 5.0
× 10 ¹⁵cm^-2Under the conditions of
Area 8 is formed.

After that, a through hole is formed above the field oxide film 3 and aluminum is deposited on the entire surface. Etching is performed so that the base electrode 9 is formed above the field oxide film 3 and the emitter electrode 10 is formed above the emitter region 8. As a result, a grounded-emitter bipolar transistor as shown in FIG. 1 is completed.

As described above, in the present invention, the tip of the bird's beak 4 is made steep by the PBL method. This allows
The parasitic capacitance C ′ at the tip of the bird's beak 4 was reduced. Therefore, by using the NPN type bipolar transistor manufactured by the manufacturing method described above in the grounded-emitter amplifier circuit, its high frequency characteristics can be improved.

[0022]

As described above, the present invention employs the PBL method when forming the field oxide film 3 as the element isolation in the manufacturing process of the grounded-emitter bipolar transistor. The tip of the bird's beak 4 has a steep shape, and the parasitic charge capacity at the tip is significantly reduced. As a result,
When a high frequency signal is input to the semiconductor device of the present invention, the current leaking to the parasitic capacitance is reduced and most of the current of the high frequency signal flows to the NPN transistor. Therefore, the amplification factor of the NPN transistor is improved and the current gain is also improved. Along with these, there is also an effect that the high frequency characteristics of the transistor of the present invention are improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a sectional view showing a conventional bipolar transistor.

FIG. 5 is a circuit diagram of FIG.

Claims (2)

[Claims] 1. A semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a field oxide film having a bird's beak having a steep tip by a polysilicon buffered LOCOS method on the surface of the epitaxial layer, and the field oxidation. From the surface of the film, via the bird's beak, the base wiring formed to reach the epitaxial layer, the base region formed between the field oxide film, the emitter region embedded in the base region, An interlayer insulating film covering the field oxide film, the base wiring, the base region, and the emitter region; a base electrode formed on the interlayer insulating film above the base wiring; and an interlayer above the emitter region. An emitter electrode formed on the insulating film, and Semiconductor device. 2. A step of forming an epitaxial layer on a semiconductor substrate, a step of forming a silicon oxide film on the surface of the epitaxial layer, and a step of sequentially forming a silicon film and a silicon nitride film on the surface of the silicon oxide film. A step of forming a through hole in the silicon film and the silicon nitride film, a step of forming a field oxide film in a region of the through hole by a thermal oxidation method, and from a surface of the field oxide film, Forming a base wiring so as to reach the epitaxial layer via the bird's beak; forming a base region between the field oxide films; forming an emitter region on the surface of the base region; A method of manufacturing a semiconductor device, comprising: