JP2003248329A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of a large area, high performance and high productivity and a method of manufacturing the same. <P>SOLUTION: In the method of manufacturing the semiconductor device by performing exposure dividedly to a plurality, the alignment of a plurality of the second and subsequent masks is performed and the divided exposure is performed by using marks for alignment formed by simultaneous exposure with the first sheet of the mask. The marks for alignment are rugged patterns of metallic films as represented by Al, Cr, Al-Nd, and Cu or Si, SiO<SB>2</SB>and SiN films. With the semiconductor device to be subjected to the exposure dividedly to a plurality, the divided exposure is performed by aligning a plurality of the second and subsequent masks using the marks for alignment formed by the simultaneous exposure with the first sheet of the mask. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device represented by a liquid crystal display, a plasma display, a photo detector, a radiation detector and the like.

[0002]

2. Description of the Related Art In recent years, as an exposure method used for manufacturing a semiconductor device represented by a photodetector, a radiation detector, a large-sized liquid crystal display, a plasma display, etc., a pattern is divided into a plurality of masks and a plurality of regions. A stepper (step-and-repeat) method for performing equal-magnification or magnified (1.25-fold) exposure using a lens and a mirror projection method for collectively exposing a pattern at a same magnification using a mirror are generally used.

In particular, the mirror projection method occupies a large share because it can expose a large area at once and has a small exposure intensity distribution.

Further, conventionally, division exposure is used for a large-area semiconductor device that cannot be collectively exposed even by using a mirror projection type exposure apparatus.

FIG. 7 is a schematic plan view of a divided portion of a conventional large-area photodetector substrate produced by divided exposure.

In the large-area photodetector, pixels each having a pair of photodetector 001 and TFT 002 are arranged in a matrix. Reference numeral 003 is a gate line for applying a drive potential of the TFT, 004 is a signal line for sending a signal from the TFT to an amplifier IC (not shown), and 005 is a bias line for applying a common potential to the photodetecting element. Here, the pixel pattern portion on the mask is exposed a plurality of times to form a large-area photodetector.

In the conventional mirror projection type exposure apparatus for a large substrate, the arrangement accuracy between the divided exposure patterns is determined by the mechanical accuracy of the stage and is as large as 3σ ≦ 4.0 μm. Etc. had occurred.

[0008]

The above-mentioned conventional example has the following problems.

That is, in a large-area photodetector using divided exposure on a large-area glass substrate, the arrangement accuracy (3σ ≦ 4.0 um) due to the mechanical precision of the divided portion is compared with the pixel pattern rule (minimum processing size 3 um). Therefore, in the divided portion, there is a yield problem such as wiring deviation like 201 in FIG. 7, wire breaking like 202 in FIG. 8 or short circuit between pixels like 203.

Further, the above-mentioned arrangement accuracy actually obtained by the division exposure is not obtained by one exposure, but the arrangement accuracy of the test substrate once exposed and developed is checked to mechanically determine the stage position. Corrected and exposed several times
It is obtained by developing.

The above-mentioned work is performed until the accuracy is within the above-mentioned range, and the work time for each time varies greatly depending on the optical adjustment state of the exposure apparatus and the stage position. For this reason, yield problems such as disconnection of wiring and short circuit between pixels frequently occur during divided exposure, and this has been a cause of greatly reducing tact.

As described above, in the conventional manufacturing method of the large-area photodetection device which is larger than the collective exposure area of the exposure device and the photomask, the reduction of the yield due to the disconnection of the wiring or the short circuit between pixels and the image defect due to the defect are avoided. I couldn't do it.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having a large area, high performance, and high productivity, and a manufacturing method thereof.

[0014]

In order to achieve the above object, the present invention is a method of manufacturing a semiconductor device in which a plurality of divided exposures are performed. Is used to align the positions of a plurality of masks for the second and subsequent masks, and to perform divided exposure.

Further, according to the present invention, in a semiconductor device in which a plurality of divided masks are exposed, the alignment marks formed on the first mask by collective exposure are used to align the second and subsequent masks. And performing divided exposure.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

<Embodiment 1> As Embodiment 1 of the present invention, the first layer (metal or Si) formed on a glass substrate.
A method for manufacturing a photo-detecting device, in which an alignment mark is formed with a film), and a second layer is used to form the lowermost layer (reference layer) as an element with the alignment mark already formed with good alignment accuracy. explain. (1) Formation of the first layer (positioning mark) As a positioning parent mark, for example, Cr on the glass substrate.
Is formed by sputtering to form a 500 A film, and the photomask of FIG. 1 is used to perform batch exposure and etching to form marks for alignment as shown in FIG. 2 on the large glass substrate 103. (2) Formation of Second Layer (Bottom Layer of Element) FIG. 3 is a schematic plan view of a photomask used for forming the second layer.

In order to form the lowermost layer (reference layer) as an element, for example, Al--Nd is formed by sputtering 1
500A film is formed, TAB connection portion A (FIG. 4A), pixel portion 1
(FIG. 4b), the pixel portion 2 (FIG. 4c), and the TAB connection portion B (FIG. 4d) are subjected to four divided exposures.

There are three large masks (TAB connecting portion A,
The patterns of the pixel portion and the TAB connection portion B) are arranged at intervals of several mm, and unnecessary patterns are mechanically shielded during each divided exposure.

Further, in order to form an element having a larger area than the mask on the glass, in the present embodiment, the pixel portion is formed by connecting two one mask patterns.

The exposure position alignment at each exposure is performed by using the alignment mark formed of Cr by using the batch exposure on the first layer.

Now, the alignment method using the alignment mark will be described with reference to FIG.

FIG. 5a shows the alignment mark formed on the first layer, and FIG. 5b shows the alignment mark arranged on the photomask for the second layer. Here, FIG. 5a is referred to as a parent mark serving as a reference for alignment, and FIG. 5b is referred to as a child mark. For alignment, observe the four parent marks formed on the substrate and the four child marks placed on the mask in an overlapping manner.
Position correction is performed in the offset (X, Y) direction and the rotation direction so that one parent mark is located at the center of each of the two X and Y child marks (see FIG. 5c).

By exposing after dividing into four, a large area device as shown in FIG. 4e is formed on the glass substrate by developing. (3) Formation of Third Layer and Later (Elements) In the second layer, in addition to the alignment mark with the first layer, the alignment (superposition) parent mark of the third and subsequent layers (Fig. 4e, 107) is formed.

Therefore, for the exposure of the third and subsequent layers, the alignment is performed using the parent mark formed on the second layer (reference layer) as in the conventional overlay.

FIG. 6 is a schematic plan view of the connecting portion of the pixels of the photodetector formed as described above. Unlike the conventional example, according to the present embodiment, the arrangement accuracy of the divided parts is improved, and wiring disconnection and short circuit between pixels do not occur.

Here, the pixel portion was exposed twice with the same pattern, but in the case of further increasing the area, the area can be easily increased by increasing the number of exposures 3, 4, 5, ... You can

By the manufacturing method as described above, the pattern arrangement accuracy of wiring or the like is about 3σ ≦ 0.5 um, which is 1 / the conventional level.
It can be improved to 8 or less, and it is possible to increase the area without causing wire breakage, output unevenness, and line defects.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to the drawings.

As a second embodiment of the present invention, a manufacturing of a photodetector for forming a lowermost layer (reference layer) as an element with good alignment accuracy by using a registration mark by a resist image formed by development. The method will be described. (1) Formation of Positioning Marks Using Resist Image In order to form the lowermost layer (reference layer) as an element on the glass substrate, for example, Al—Nd is deposited at 1500 A by a sputtering method. A photoresist is applied, and a batch exposure, development, and post-baking are performed using the photomask of FIG. 1 to form a resist image having an alignment pattern as shown in FIG. 2 on the large glass substrate 103. (2) Formation of First Layer (Bottom Layer of Element) FIG. 3 is a schematic plan view of a photomask used for forming the first layer (bottom layer of element).

In the step (1), Al-Nd is formed into a film, and a registration mark is formed on the Al-Nd film on the substrate.
Apply the resist again.

In order to form the lowermost layer (reference layer) as an element, the alignment mark (resist image) formed by collective exposure in (1) is used, and the TAB connection portion A (FIG. 4a) and the pixel portion 1 ( 4b), the pixel portion 2 (FIG. 4c), and the TAB connection portion B (FIG. 4d) are subjected to four divided exposures.

By exposing the wafer in four divisions and then developing it, a large-area device as shown in FIG. 4e is formed on the glass substrate.

Further, the resist image formed by collective exposure disappears in the subsequent peeling process. (3) Formation of Second Layer and Later (Element) In the first layer, in addition to the child mark for alignment with the resist image parent mark, the parent mark for alignment (overlay) of the second layer and later (Fig. 4e, 107) is formed.

Therefore, in the exposure of the second and subsequent layers, the alignment is performed using the parent mark formed in the first layer, as in the conventional overlay.

FIG. 6 shows a schematic plan view of the connecting portion of the pixels of the photodetector formed as described above. Unlike the conventional example, according to the present embodiment, the arrangement accuracy of the divided parts is improved, and wiring disconnection and short circuit between pixels do not occur.

Here, the pixel portion was exposed twice with the same pattern, but in the case of further increasing the area, the area can be easily increased by increasing the number of exposures 3, 4, 5, ... You can

By the manufacturing method as described above, the pattern arrangement accuracy of the wiring or the like is about 3σ ≦ 0.5 um, which is 1 / the conventional level.
It can be improved to 8 or less, and it is possible to increase the area without causing wire breakage, output unevenness, and line defects.

<Third Embodiment> Next, a third embodiment of the present invention will be described with reference to the drawings.

As a third embodiment of the present invention, manufacturing of a photodetector for forming a lowermost layer (reference layer) as an element with good alignment accuracy by using a positioning mark formed by etching a glass substrate. The method will be described. (1) Formation of Registration Marks by Etching of Glass Substrate A photoresist is applied on the glass substrate, and collective exposure, development, and post-baking are performed using the photomask of FIG.
The glass is etched using RIE to form an alignment pattern as shown in FIG. 2 on the large glass substrate 103. (2) Formation of First Layer (Bottom Layer of Element) FIG. 3 is a schematic plan view of a photomask used for forming the first layer.

In order to form the lowermost layer (reference layer) as an element, for example, Al--Nd is sputtered to form 1
500A film is formed, TAB connection portion A (FIG. 4A), pixel portion 1
(FIG. 4b), the pixel portion 2 (FIG. 4c), and the TAB connection portion B (FIG. 4d) are subjected to four divided exposures.

By exposing after dividing into four parts, a large area element as shown in FIG. 4e is formed on the glass substrate by developing. (3) Formation of Second Layer and Later (Element) In the first layer, in addition to the child mark for the alignment mark formed of glass, the parent mark for alignment (overlay) of the second and subsequent layers (107 in FIG. 4e) is formed.

Therefore, for the exposure of the second and subsequent layers, the alignment is performed using the parent mark formed on the first layer as in the conventional overlay.

FIG. 6 is a schematic plan view of the connecting portion of the pixels of the photo-detecting device formed as described above. Unlike the conventional example, according to the present embodiment, the arrangement accuracy of the divided parts is improved, and wiring disconnection and short circuit between pixels do not occur.

Here, the pixel portion was exposed twice with the same pattern, but in the case of further increasing the area, the area can be easily increased by increasing the number of exposures 3, 4, 5, ... You can

By the manufacturing method as described above, the pattern arrangement accuracy of the wiring or the like is about 3σ ≦ 0.5 um, which is 1 / the conventional level.
It can be improved to 8 or less, and it is possible to increase the area without causing wire breakage, output unevenness, and line defects.

[0047]

As is apparent from the above description, according to the present invention, a manufacturing method for performing divided exposure using a large-area glass substrate larger than the collective exposure area of an exposure apparatus and a photomask is described. The array accuracy is about i / 8, which is 3σ ≦.
It could be 0.5 um.

It is possible to increase the area without causing line breakage, pixel short circuit, output unevenness due to line shift, and the like in the mask connection portion due to the divided exposure without causing line defects.

A stable process tact was obtained and productivity was improved. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a photomask used for forming a first alignment parent mark in the first to third embodiments of the present invention.

FIG. 2 is a schematic layout diagram of an alignment parent mark formed by the photomask of FIG. 1 in Embodiments 1 to 3 of the present invention.

FIG. 3 is a schematic plan view of a photomask used for forming a lowermost layer (reference layer) used as an element in the first to third embodiments of the present invention.

FIG. 4 is a schematic layout diagram of a pattern formed by the photomask of FIG. 3 in Embodiments 1 to 3 of the present invention.

FIG. 5 is a schematic plan view of an alignment mark used in the first to third embodiments of the present invention.

FIG. 6 is a schematic pixel layout diagram of a divided portion of pixels formed according to the first to third embodiments of the present invention.

FIG. 7 is a first schematic plan view of a divided exposure part of a large area photodetector manufactured by conventional divided exposure.

FIG. 8 is a second schematic plan view of a divided exposure part of a large area photodetector manufactured by conventional divided exposure.

[Explanation of symbols]

001 Photodetector 002 TFT 003 Gate line 004 Signal line 005 Bias line 006 Interval 007 Glass substrate 008 Dividing position 101 Positioning parent mark 102 Photomask 103 Large glass substrate 104 TAB connecting portion A 105 Pixel portion 106 TAB connecting portion B 107 Positioning child mark and superimposing parent mark 108 for the next and subsequent layers Positioning child mark 201 Wiring deviation 202 Wiring disconnection 203 Short circuit between pixels

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a plurality of divided masks are exposed by using a positioning mark formed by collective exposure with a first mask in a method for manufacturing a semiconductor device A method for manufacturing a semiconductor device, which comprises performing divided exposure. 2. The alignment mark is made of Al, C
Metal films typified by r, Al-Nd, and Cu, Si, Si
The method of manufacturing a semiconductor device according to claim 1, wherein the method is an uneven pattern of O ₂ and SiN films. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark is an uneven pattern of a resist image. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark is an uneven pattern formed by etching a substrate. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device uses glass as a substrate. 6. In a semiconductor device which performs exposure by dividing into a plurality of portions, the plurality of masks of the second and subsequent sheets are aligned using the alignment marks formed by collective exposure with the first mask, and the divided exposure is performed. A semiconductor device comprising: 7. The alignment mark is made of Al, C
7. The semiconductor device according to claim 6, which is an uneven pattern of a metal film or a Si film typified by r, Al—Nd, and Cu. 8. The semiconductor device according to claim 6, wherein the alignment mark is an uneven pattern of a resist image. 9. The semiconductor device according to claim 6, wherein the alignment mark is an uneven pattern formed by etching a substrate. 10. The semiconductor device according to claim 6, wherein the semiconductor device uses glass as a substrate.