JP2003243799A - Method of manufacturing flexible board - Google Patents

Method of manufacturing flexible board

Info

Publication number
JP2003243799A
JP2003243799A JP2002035326A JP2002035326A JP2003243799A JP 2003243799 A JP2003243799 A JP 2003243799A JP 2002035326 A JP2002035326 A JP 2002035326A JP 2002035326 A JP2002035326 A JP 2002035326A JP 2003243799 A JP2003243799 A JP 2003243799A
Authority
JP
Japan
Prior art keywords
pattern
inspection
voltage
flexible board
pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002035326A
Other languages
Japanese (ja)
Other versions
JP2003243799A5 (en
Inventor
Tsutomu Matsudaira
努 松平
Nobukazu Koizumi
信和 小泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Maruwa Seisakusho KK
Original Assignee
Seiko Instruments Inc
Maruwa Seisakusho KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc, Maruwa Seisakusho KK filed Critical Seiko Instruments Inc
Priority to JP2002035326A priority Critical patent/JP2003243799A/en
Publication of JP2003243799A publication Critical patent/JP2003243799A/en
Publication of JP2003243799A5 publication Critical patent/JP2003243799A5/ja
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To detect a pattern which has a potential disconnection by a stress so as to provide a flexible board that is high and stable in quality. <P>SOLUTION: A voltage is applied between electrodes after patterning, whereby a defective part such as a thinned part of a pattern is broken. Thereafter, an open-short test is carried out for the flexible board. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ファインパターン
(一般に、パターンが100μmピッチ以下をいう)回
路を形成したフィルム基板の製造方法と携帯機器等や、
電子手帳に使用されている表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a film substrate having a fine pattern circuit (generally, a pattern having a pitch of 100 μm or less) and a portable device,
The present invention relates to a display device used in an electronic notebook.

【0002】[0002]

【従来の技術】液晶表示装置には、ドライバIC実装と
コンデンサや抵抗等のチップ部品やパッケージIC等の
電子部品をフィルム基板に混在実装したCOF(Chi
p・On・FPC)を液晶パネルに実装した形態が知ら
れている。従来、このような液晶表示装置に用いられる
フィルム基板は、ポリイミドフィルムにフィルム状の接
着剤をつけ、圧延や電解等の製法のCu箔を貼りつけ、
Cuをパターニングしてパターン形成し、レジストコー
トや表面保護のための電解メッキや無電解メッキをして
いた。このような3層の構成のフィルム基板は、接着剤
が熱や湿度によって変形するため、100μmピッチ以
下のファインパターンには寸法安定性の面で不向きであ
った。
2. Description of the Related Art In a liquid crystal display device, COF (Chi) in which a driver IC is mounted and chip parts such as capacitors and resistors and electronic parts such as package ICs are mixedly mounted on a film substrate.
There is known a mode in which p.On.FPC) is mounted on a liquid crystal panel. Conventionally, a film substrate used for such a liquid crystal display device has a film-shaped adhesive attached to a polyimide film, and a Cu foil produced by a manufacturing method such as rolling or electrolysis.
Cu is patterned to form a pattern, and a resist coat and electrolytic plating or electroless plating for surface protection have been performed. The film substrate having such a three-layer structure is not suitable for a fine pattern having a pitch of 100 μm or less in terms of dimensional stability, because the adhesive is deformed by heat and humidity.

【0003】そのため、この接着剤を取り除いたフィル
ム基板(2層フイルム基板)が開発され、用いられるよ
うになった。このような接着剤層のない2層フイルム基
板には、2つの製法がある。
Therefore, a film substrate (two-layer film substrate) from which this adhesive is removed has been developed and used. There are two manufacturing methods for such a two-layer film substrate having no adhesive layer.

【0004】一つはCu箔にポリアミック酸ワニスを塗
り溶媒を除去した後硬化するキャスティング法とポリイ
ミドフィルムに例えばニクロム合金,モリブデン,チタ
ン,ニッケル,コバルト,クロム,パラジューム,ジル
コニューム,モリブデン,タングステンなどの密着性改
善のため金属薄膜を形成し、スパッタリングもしくは蒸
着よりCu薄膜を形成した後、電解メッキでCuを積層
する蒸着法がある。
One is a casting method in which a Cu foil is coated with a polyamic acid varnish and then the solvent is removed, and then the polyimide film is cured. There is a vapor deposition method in which a metal thin film is formed to improve adhesion, a Cu thin film is formed by sputtering or vapor deposition, and then Cu is laminated by electrolytic plating.

【0005】これら製法のフィルム基板の違いは、Cu
の厚みである。キャスティング法に使われるCuの厚み
は、一般的には35μmや18μmであり、最近では1
2μmが量産化されている。蒸着法ではCuの厚みは、
1μmから18μmまでは量産が可能である。
The difference between the film substrates of these manufacturing methods is that Cu
Is the thickness of. The thickness of Cu used in the casting method is generally 35 μm or 18 μm, and recently 1
2 μm is mass produced. In the vapor deposition method, the thickness of Cu is
Mass production is possible from 1 μm to 18 μm.

【0006】ファインパターンを形成するには、キャス
ティング法は電解Cu箔をハーフエッチングしてからパ
ターニングする方法があるがCu箔の表面粗さが比較的
大きいため、安定した歩留まりを得るのは容易でない。
パターンが100μmピッチ以下では、Cuの厚みが均
一に薄くできる蒸着法のフィルム基板の方が適してい
た。
In order to form a fine pattern, the casting method includes a method of half-etching an electrolytic Cu foil and then patterning it. However, since the surface roughness of the Cu foil is relatively large, it is not easy to obtain a stable yield. .
When the pattern has a pitch of 100 μm or less, the film substrate of the vapor deposition method, which can uniformly reduce the thickness of Cu, was more suitable.

【0007】ICの外部接続電極のバンプピッチは、I
Cのプロセス開発が進み小型化へ進んでいる。そのた
め、ICの外部接続電極のバンプピッチは40μmピッ
チが量産始まり、30μmピッチが開発されている。
The bump pitch of the external connection electrodes of the IC is I
Process development of C is progressing and miniaturization is progressing. Therefore, the bump pitch of the external connection electrodes of the IC has started to be mass-produced at a pitch of 40 μm and a pitch of 30 μm has been developed.

【0008】一方、表示装置はフィルム基板にICを接
続したCOF(Chip On Fpc)を表示パネルに
接続して表示装置を製造していた。COFは駆動ICや
コンデンサや抵抗等のチップ部品更に電源ICやオペア
ンプなどのパッケージを高密度に実装できるため、表示
装置を小型化薄型化に出来る。この表示装置は携帯機器
に多く使用されており、中でも携帯電話やPDAに代表
される携帯情報端末の需要が近年大きく伸びつつある。
On the other hand, in the display device, a COF (Chip On Fpc) in which an IC is connected to a film substrate is connected to a display panel to manufacture the display device. Since the COF can mount a high-density package such as a drive IC, chip parts such as a capacitor and a resistor, and a power supply IC and an operational amplifier, the display device can be miniaturized and thinned. This display device is widely used in mobile devices, and in particular, the demand for mobile information terminals represented by mobile phones and PDAs is growing significantly in recent years.

【0009】[0009]

【発明が解決しようとする課題】30μmピッチの駆動
ICを用いるためには、接続するフィルム基板のパター
ンの幅は10から15μmとなる。パターニングは、ポ
リイミドフィルムの全面に銅を形成した原反にフォトレ
ジストを形成し露光及び現像を行った後にエッチングを
することで形成するが、原反表面やレジスト内及び表
面、また、露光マスクの表面に異物や汚れ,シミなど
や、原反の銅の欠陥によりエッチングの不具合が生ず
る。形成したパターン幅の精度はより高い方が望まれる
が実用的には、フレキシブル基板の屈曲などのストレス
に対し耐えうるパターン幅が必要である。パターンの形
成の検査方法として、プロービングによる導通検査方法
(1)、ビジョン認識によるCADのマスターデータと
照合する検査方法()、パターンの一方の端へプロー
バー等により信号を印加して、他方の端より空気コンデ
ンサの原理により信号を検出する非接触検査方法
(3)、顕微鏡を用いた人による外観検査(4)、等が
ある。しかし(1)プロービング検査方法では、30μ
mピッチではプローブの接続が困難である。プローブの
種類にもよるが、精度のよいバンプ付フレキシブル基板
を用いたとしても、プローブとフレキシブル基板の位置
合わせにアライメント機能を有する検査機でも数秒の時
間がかかるため検査コストが非常に高価になり、かつ、
断線しかかった個所の検出はできない。また、(2)ビ
ジョンを用いた外観検査機では、パターンの状態を正確
に判断するためには、カメラ倍率が高くなければならな
いため、時間がかかることと、パターン上の異物や、基
板の表面状態により誤検出が生ずる。また、(4)は人
による作業のため、不良の流出はゼロにはできない。そ
のため、現状では(3)の非接触検査方法が最も適した
方法である。通常フレキシブル基板をフラットな状態に
して検査を行っている。
In order to use a driving IC having a pitch of 30 μm, the width of the pattern of the film substrate to be connected is 10 to 15 μm. The patterning is performed by forming a photoresist on an original fabric having copper formed on the entire surface of the polyimide film, performing exposure and development, and then performing etching, but the original fabric surface, the inside and the surface of the resist, and the exposure mask Foreign matter, stains, stains, etc. on the surface and defects in the original copper cause etching defects. It is desired that the accuracy of the formed pattern width is higher, but practically, a pattern width that can withstand stress such as bending of the flexible substrate is required. As an inspection method for pattern formation, a continuity inspection method by probing (1), an inspection method by which it is compared with CAD master data by vision recognition (), a signal is applied to one end of the pattern by a prober or the like, and the other end is applied. There are a non-contact inspection method (3) in which a signal is detected by the principle of an air condenser, an external appearance inspection by a person using a microscope (4), and the like. However, in (1) probing inspection method, 30μ
It is difficult to connect the probe at the m pitch. Depending on the type of probe, even if an accurate flexible board with bumps is used, even an inspection machine that has an alignment function for aligning the probe and the flexible board will take several seconds, making the inspection cost very expensive. ,And,
It is not possible to detect where the wire is about to break. (2) In the visual inspection machine using vision, the camera magnification must be high in order to accurately judge the state of the pattern, so it takes time, and foreign matter on the pattern and the surface of the substrate are required. False detection occurs depending on the state. Moreover, in (4), since the work is performed by a person, the outflow of defects cannot be zero. Therefore, at present, the non-contact inspection method (3) is the most suitable method. Usually, the inspection is performed with the flexible substrate in a flat state.

【0010】しかし、微細ピッチのフレキシブル基板に
は、パターンの細りと曲げ等のストレスにより発生する
断線不良モードがあり、それは、局部的に3μm以下で
導通している細りが生じているパターンで発生する。非
接触検査プロービング検査では、この不良を検出するた
めに一方の端にコンタクトするプローバーと検出するセ
ンサーをフレキシブル基板に検査条件を維持したまま、
フレキシブル基板を変形させてストレスを与え検査する
ことは、検査機の機構上及び都度製品のパターンや外形
サイズが変更しても同一条件で行うことが非常に難し
い。
However, a flexible substrate having a fine pitch has a disconnection failure mode caused by stress such as thinning and bending of the pattern, which locally occurs in a pattern of thinness of 3 μm or less in conduction. To do. In the non-contact inspection probing inspection, in order to detect this defect, the prober that contacts one end and the sensor that detects it are maintained on the flexible substrate while maintaining the inspection conditions.
It is very difficult to deform the flexible substrate and apply stress to it for inspection under the same conditions on the mechanism of the inspection machine and even if the product pattern or outer size is changed each time.

【0011】つまり本発明は、パターンの細りと曲げ等
のストレスにより発生する断線不良を確実に検出し、安
定した品質のフレキシブル基板を得ることにある。
That is, the present invention is to reliably detect a disconnection defect caused by stress such as pattern thinning and bending, and obtain a flexible board of stable quality.

【0012】[0012]

【問題が解決するための手段】上述した課題を解決する
ために、パターン形成後に、パターンの欠け等、断線し
かかった部分のパターンを破壊するために、パターンの
両端に電圧を印加することとした。その後、パターン検
査をおこなう工程を設けた。検査前に通常3μm以下の
パターンを電気的に破壊することで、曲げ等により発生
する断線不良は無くなり、非接触検査方法で確実に検査
が行える。
In order to solve the above-mentioned problems, after the pattern is formed, a voltage is applied to both ends of the pattern in order to destroy the pattern in a portion which is about to be broken, such as chipping of the pattern. did. After that, a step of performing a pattern inspection was provided. By electrically destroying the pattern of usually 3 μm or less before the inspection, the disconnection defect caused by bending or the like is eliminated, and the non-contact inspection method can surely perform the inspection.

【0013】また、パターンを破壊する工程において、
一つ一つの電極接続するのでは、効率が非常に悪いた
め、導電ラバー等で複数の電極に一括して電圧を印加す
ることすることで容易にを得る事ができた。
In the process of destroying the pattern,
Since connecting each electrode is very inefficient, it was possible to easily obtain by applying a voltage to a plurality of electrodes at once by using a conductive rubber or the like.

【0014】[0014]

【発明の実施の形態】以下に、本発明の実施例を図面に
基づいて説明する。 (実施例1)本実施例の工程を表わすフローを図1に示
す。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) A flow chart showing the steps of this embodiment is shown in FIG.

【0015】先ず、ポリイミド表面にスパッタリングと
メッキで銅を形成した原反にレジストを形成する。次
に、ガラス表面にCrでパターンを形成したマスクをあ
わせ露光する。アルカリ性の溶液で現像をおこない、酸
性の溶液であるエッチング液に浸し、銅をエッチングす
る。アルカリ性溶液に浸し、エッチングで使用したレジ
ストを除去する。次に、形成したパターン全面に第一の
スズメッキを形成し、ソルダーレジストを形成する。ソ
ルダーレジストは、印刷レジストでもフォトソルダーレ
ジストでもよい。次に、露出した電極部に第二のスズメ
ッキをおこなう。スズメッキ後、ウイスカ防止として加
熱処理をおこなう。次に、パターニングの不具合により
発生した細り部を電圧印加により破壊する。破壊の条件
は30V−0.5秒である。条件は、一定電圧でも一定
の電流でも良い。細りのある部分では抵抗が高くなるた
め、電圧を印加して、電流を流すことで、細りのある部
分でジュール熱が発生し、パターンが断線する。電圧印
加の工程は、エッチング以降であればいつ行ってもかま
わないが、出荷に近い側で行った方が確実である。この
電圧印加により、ストレスにより断線するパターン細り
部を完全に断線することができる。次に非接触検査法に
よるパターン検査を行う。検査は断線とショートが行え
る。次に、補強板を貼りつけ、外形を打ち抜き、外観検
査を行ってフレキシブル基板は完成する。
First, a resist is formed on an original fabric having copper formed on the surface of polyimide by sputtering and plating. Next, a mask having a pattern formed of Cr on the glass surface is also exposed. Development is performed with an alkaline solution, and the copper is etched by immersing in an etching solution which is an acidic solution. Dip in an alkaline solution and remove the resist used for etching. Next, a first tin plating is formed on the entire surface of the formed pattern to form a solder resist. The solder resist may be a printing resist or a photo solder resist. Next, second tin plating is performed on the exposed electrode portion. After tin plating, heat treatment is performed to prevent whiskers. Next, the thin portion generated due to the patterning defect is destroyed by applying a voltage. The condition of destruction is 30V-0.5 seconds. The condition may be a constant voltage or a constant current. Since the resistance increases in the thin portion, Joule heat is generated in the thin portion by applying a voltage and passing a current, and the pattern is broken. The step of applying a voltage may be performed at any time after etching, but it is more reliable to perform it on the side closer to shipping. By applying this voltage, it is possible to completely disconnect the thin pattern portion that is disconnected by stress. Next, pattern inspection is performed by the non-contact inspection method. Inspection can be performed for disconnection and short circuit. Next, a reinforcing plate is attached, the outer shape is punched out, and a visual inspection is performed to complete the flexible substrate.

【0016】電圧印加の条件は、銅箔の厚みや品質保証
の条件で決めればよいことであり、上記条件にこだわる
ものではない。パターンのオープンショート検査は、非
接触検査法にこだわるものではない。電圧印加は、全電
極にする必要は無く、特にファインパターン部を対象と
して実施することもある。 (実施例2)パターンは複数であり連続に配列し、その
電極が束状にある場合は、電極の端部と一方の端部を導
電ゴムでコンタクトをとり電圧を印加する。導電ゴム
は、エラストマー樹脂にカーボンフレークを混ぜて作
る。製品の形状に合わせて、作っても良い。
The condition of voltage application may be determined by the thickness of the copper foil and the condition of quality assurance, and is not limited to the above condition. The open / short inspection of patterns is not limited to the non-contact inspection method. It is not necessary to apply the voltage to all electrodes, and the voltage may be applied especially to the fine pattern portion. (Embodiment 2) If there are a plurality of patterns and they are arranged continuously and the electrodes are in a bundle, the ends of the electrodes and one end thereof are contacted with a conductive rubber to apply a voltage. Conductive rubber is made by mixing carbon flakes with elastomer resin. You may make it according to the shape of the product.

【0017】[0017]

【発明の効果】本発明は以上説明したように、本発明の
電圧印加工程により、ストレスにより発生するパターン
断線の流出を防止でき、安定したファインパターンのフ
レキシブル基板の品質を得ることができた。
As described above, according to the present invention, by the voltage application process of the present invention, it is possible to prevent outflow of pattern disconnection caused by stress, and obtain a stable quality of a flexible substrate having a fine pattern.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1の工程を示したフロー図FIG. 1 is a flowchart showing the steps of Example 1 of the present invention.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小泉 信和 神奈川県藤沢市村岡東1丁目18番地の2 株式会社丸和製作所内 Fターム(参考) 2H090 HC12 JB03 JD13 LA01 LA04   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nobukazu Koizumi             2-18-1 Muraoka Higashi, Fujisawa City, Kanagawa Prefecture             Maruwa Manufacturing Co., Ltd. F-term (reference) 2H090 HC12 JB03 JD13 LA01 LA04

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁フィルム上に金属パターンを形成す
る工程と、パターンの欠け等で断線しかかった部分を破
壊するパために、パターンの両端に一定の電圧を印加す
るか、もしくは、一定の電流を流すパターン破壊工程
と、その後、パターン検査をおこなう工程と、を備える
ことを特徴とするフレキシブル基板の製造方法。
1. A step of forming a metal pattern on an insulating film, and a constant voltage is applied to both ends of the pattern or a constant voltage in order to destroy a portion which is about to be disconnected due to a chip or the like of the pattern. A method of manufacturing a flexible substrate, comprising: a pattern destruction step of passing an electric current; and a step of subsequently performing a pattern inspection.
【請求項2】 前記パターン破壊工程において、複数の
電極に一括して電圧を印加することを特徴とする請求項
1に記載のフレキシブル基板の製造方法。
2. The method of manufacturing a flexible substrate according to claim 1, wherein a voltage is applied to a plurality of electrodes at a time in the pattern destruction step.
JP2002035326A 2002-02-13 2002-02-13 Method of manufacturing flexible board Pending JP2003243799A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002035326A JP2003243799A (en) 2002-02-13 2002-02-13 Method of manufacturing flexible board

Publications (2)

Publication Number Publication Date
JP2003243799A true JP2003243799A (en) 2003-08-29
JP2003243799A5 JP2003243799A5 (en) 2005-07-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2003243799A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007097249A1 (en) 2006-02-20 2007-08-30 Daicel Chemical Industries, Ltd. Porous film and layered product including porous film
US7821281B2 (en) 2009-02-23 2010-10-26 Faraday Technology Corp. Method and apparatus of testing die to die interconnection for system in package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007097249A1 (en) 2006-02-20 2007-08-30 Daicel Chemical Industries, Ltd. Porous film and layered product including porous film
EP2410824A2 (en) 2006-02-20 2012-01-25 Daicel Chemical Industries, Ltd. Porous film and layered product including porous film
EP2487030A2 (en) 2006-02-20 2012-08-15 Daicel Chemical Industries, Ltd. Porous film and layered product including porous film
US8294040B2 (en) 2006-02-20 2012-10-23 Daicel Chemical Industries, Ltd. Porous film and multilayer assembly using the same
EP2591912A1 (en) 2006-02-20 2013-05-15 Daicel Chemical Industries, Ltd. Multilayer assembly and composite material comprising same
US7821281B2 (en) 2009-02-23 2010-10-26 Faraday Technology Corp. Method and apparatus of testing die to die interconnection for system in package

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