JP2003243657A - Semiconductor device, electrooptic device, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing electrooptic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, electrooptic device, electronic equipment, method for manufacturing semiconductor devices, and a method for manufacturing electrooptic devices, capable of a high level balancing of the on-current levels of N-channel type and P-channel type TFTs used in a complementary circuit. <P>SOLUTION: An N-channel type circuit driving TFT90 and a P-channel type circuit driving TFT80 constitute a complementary circuit 62 on a TFT array substrate 10. The TFT90 has a top gate structure, with a gate electrode 65 provided only at the upper layer side of a channel forming region 91, while the TFT80 has a bottom gate/top gate structure, with gate electrodes 65a, 65b provided at the lower layer side and the upper layer side of the channel forming region 91, respectively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a complementary circuit is composed of an N-channel type thin film transistor (hereinafter referred to as TFT) and a P-channel type TFT, and this semiconductor device is used as a TFT array substrate. The present invention relates to an electro-optical device, an electronic apparatus using the electro-optical device, a semiconductor device manufacturing method, and an electro-optical device manufacturing method using the semiconductor device as a TFT array substrate.

[0002]

2. Description of the Related Art In an electro-optical device such as a liquid crystal device using an active matrix substrate (TFT array substrate) with a built-in drive circuit or a display device in which an organic electroluminescence element is formed on the same substrate as a drive circuit, In the drive circuit, as shown in FIG. 17, an N-channel TF
The complementary circuit 62 is configured by the T90 and the P-channel TFT 80. In the complementary circuit 62 shown here, the N-channel type TFT 90 and the P-channel type TFT 80 are generally formed to have the same structure. In the example shown in FIG. 17, the N-channel type TFT 90, In both the P-channel TFT 80 and the P-channel TFT 80, the low-concentration source / drain regions 83 and 95 and the low-concentration source
It has an LDD structure including drain regions 83 and 85, respectively.

[0003]

However, comparing electrons with holes, holes have a lower mobility, and therefore N
Channel type TFT 90 and P channel type TFT
In FIG. 18, those source / drain current-gate voltage characteristics are shown in FIG. 18 as a solid line L90 and a dashed line L80, respectively.
As shown in, P compared to N-channel TFT 90
The on-current level of the channel type TFT 90 is low. Therefore, in the conventional complementary circuit 62, the N-channel type TFT is used.
90 and the P-channel type TFT 80 have a bad balance of on-current levels, resulting in a narrow operation margin and a erroneous operation.

Therefore, in the past, the N-channel type TFT 9 has been used.
0 has an LDD structure, while a P-channel TFT 80
With respect to the above, measures such as a self-aligned structure have been taken, but such measures cannot completely eliminate the above problems.

In view of the above problems, the object of the present invention is to
A semiconductor device, an electro-optical device, an electronic device capable of balancing the ON current levels of the N-channel TFT and the P-channel TFT used in the complementary circuit at a high level.
It is to provide a method for manufacturing a semiconductor device and a method for manufacturing an electro-optical device.

[0006]

In order to solve the above problems, according to the present invention, in a semiconductor device in which a complementary circuit is formed on a substrate by a first conductivity type TFT and a second conductivity type TFT, The first conductivity type TFT has a gate electrode facing the channel formation region via a gate insulating film only on one of the upper layer side and the lower layer side of the channel formation region, while the second conductivity type TFT is provided. TFT of
A first gate electrode that faces the channel formation region via a first gate insulating film on the lower layer side of the channel formation region, and a second gate electrode on the upper layer side of the channel formation region with respect to the channel formation region. And a second gate electrode facing each other with a gate insulating film interposed therebetween.

In the present invention, for the first conductivity type TFT, the gate electrode is formed only on one of the upper layer side and the lower layer side of the channel formation region, while for the second conductivity type TFT, the channel electrode is formed. A first gate electrode and a second gate electrode are provided on both the lower layer side and the upper layer side of the formation region, respectively. Therefore, in the first conductivity type TFT,
While the channel is formed only in the lower layer or the upper layer of the channel forming region, for the second conductivity type TFT, the channel is formed in both the upper layer side and the lower layer side of the channel forming region. The on-current level of the TFT can be increased to the on-current level of the first conductivity type TFT. Therefore, the first conductivity type T used in the complementary circuit
Since the on-current balance between the FT and the second conductivity type TFT can be improved, a semiconductor device in which malfunction does not easily occur can be provided.

In the present invention, in the second conductivity type TFT, the on-current level of the second conductivity type TFT is increased by disposing the gate electrodes on both the upper layer side and the lower layer side of the channel formation region. Therefore, the first conductivity type T
FT is an N-type channel type and the second conductivity type TF is used.
If T is a P-channel type, in a complementary circuit,
This means that the on-current level of the P-channel type TFT can be increased to the on-current level of the N-channel type TFT.

In the present invention, the upper and lower two gate electrodes are provided for the second conductivity type TFT whose on-current level tends to be low. Therefore, in the second conductivity type TFT, the second conductivity type TFT is connected to the second gate electrode. It is preferable to form the high-concentration source / drain regions in a self-aligned manner to increase the on-current level.

In the present invention, the second conductivity type TFT
Is preferably equal to or longer in the channel length direction than the first gate electrode.

In the present invention, the high-concentration source / drain regions of the second conductive type thin film transistor are the first
Has an overlapping region facing the first gate electrode through the gate insulating film.

In the present invention, the first conductivity type TFT
For example, the gate electrode is provided only on the upper layer side of the channel formation region.

In the present invention, the first conductivity type TFT
For example, it is preferable that the high-concentration source / drain regions are formed in self-alignment with the gate electrode. That is, according to the present invention, in the second-conductivity-type TFT, the two gate electrodes are arranged above and below the channel formation region to increase the on-current level.
For the above, even if the self-aligned structure is used and the on-current level is set to be high, the first conductivity type TFT and the second conductivity type T
The on-current level can be balanced at a high level with respect to FT. Therefore, a complementary circuit having a high operating speed can be constructed.

In the present invention, the first conductivity type TFT
Is a low-concentration source in the area facing the edge of the gate electrode.
LDD (Lightly Dop) having a drain region
edDrain) structure or an offset gate structure having a high-concentration source / drain region at a position shifted in the channel length direction with respect to the end of the gate electrode. For example, an N-channel TFT has an advantage that the on-current level is high, but
It has the drawbacks of low withstand voltage and high off-leakage current level.
This can be solved by adopting the DD structure or the offset gate structure.

In the present invention, the first conductivity type TFT
With respect to the above, a multi-gate structure including a plurality of gate electrodes in the channel length direction may be used to improve the withstand voltage.

A semiconductor device to which the present invention is applied is, for example,
A liquid crystal device or an organic electroluminescence display device can be configured as a TFT array substrate holding an electro-optical material. In this case, the TFT array substrate has a TFT for pixel switching in an image display region.
Pixels having pixel electrodes are formed in a matrix, and a peripheral circuit having the complementary circuit is formed on the outer peripheral side of the image display area.

In the present invention, the electro-optical material is, for example, liquid crystal.

The electro-optical device to which the present invention is applied can be used in electronic devices such as mobile computers and mobile phones.

In the method of manufacturing a semiconductor device to which the present invention is applied, in forming the second conductivity type TFT,
A first gate electrode, a first gate insulating film, a semiconductor film forming a channel formation region, a second gate insulating film, and a second gate electrode are formed in this order on the substrate, while the first gate electrode is formed. In forming the conductive type TFT, the first conductive type T is formed by using the step of forming the semiconductor film forming the channel forming region of the second conductive type TFT.
Forming a semiconductor film forming a channel formation region of FT,
And a step of forming a first gate electrode and a first gate insulating film of the second conductivity type TFT, or a step of forming a second gate electrode and a second gate insulating film of the second conductivity type TFT. One of the above is used to form a gate electrode that faces the channel formation region via the gate insulating film only on one of the upper layer side and the lower layer side of the channel formation region.

With this structure, the TF of the first conductivity type is formed.
Since the process is shared between T and the second conductivity type TFT,
The semiconductor device according to the present invention can be manufactured with the minimum required number of steps.

In the present invention, the second conductivity type TFT
In forming the film, a high-concentration impurity is introduced into the semiconductor film by using the second gate electrode as a mask to self-align the high-concentration source layer with the second gate electrode.
It is preferable to form the drain region.

In the present invention, the first conductivity type TFT
As for the above, it is preferable to form the gate electrode and the gate insulating film only on the upper layer side of the channel formation region. According to this structure, when the first conductivity type TFT has a self-aligned structure or an LDD structure, impurities are introduced into the semiconductor film using the gate electrode as a mask to self-align the high-concentration source / gate with the gate electrode. A drain region or low concentration source / drain regions can be formed.

When the semiconductor device according to the present invention is formed as a TFT array substrate holding an electro-optical material, the TFT array substrate is provided with a pixel provided with a pixel switching TFT and a pixel electrode in the image display region. Are formed in a matrix, and a peripheral circuit provided with the complementary circuit is formed on the outer peripheral side of the image display area to form a driving circuit built-in type TFT array substrate.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type.

(Overall Structure of Liquid Crystal Device) FIG.
1B is a plan view of a liquid crystal device (electro-optical device) to which the present invention is applied, together with the respective components formed thereon, as seen from the side of the counter substrate, and HH ′ in FIG. 1A. FIG.

In FIG. 1A, T of the liquid crystal device 100 is shown.
A sealing material 107 is provided on the FT array substrate 10 (semiconductor device) along the edge of the counter substrate 20. In the area outside the sealing material 107, the data line driving circuit 101 and the mounting terminal 102 are provided with the TFT array substrate 10.
Are provided along one side of the scanning line driving circuit 104.
Are formed along two sides adjacent to this one side.

It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line does not matter. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a. For example, the odd-numbered data lines supply the image signal from the data line driving circuit arranged along one side of the image display area 10a, and the even-numbered data lines are provided on the opposite side of the image display area 10a. An image signal may be supplied from a data line driving circuit arranged along the line. By thus driving the data lines in a comb shape, the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured.

Further, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided on the remaining side of the TFT array substrate 10, and further below the frame 108. A precharge circuit or an inspection circuit may be provided by utilizing the above. Further, at least one position of the corner portion of the counter substrate 20 is formed with a vertical conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20.

Then, as shown in FIG.
The counter substrate 20 having substantially the same contour as the sealing material 107 shown in (A) is fixed to the TFT array substrate 10 by this sealing material 107. The sealing material 107 is T
An adhesive made of a photo-curing resin or a thermosetting resin for bonding the FT array substrate 10 and the counter substrate 20 around their periphery, and a glass fiber for setting the distance between the substrates to a predetermined value, or Gap materials such as glass beads are mixed.

The TFT array substrate 1 will be described in detail later.
At 0, pixel electrodes 9a are formed in a matrix. On the other hand, the sealing material 107 is formed on the counter substrate 20.
A frame 108 made of a light-shielding material is formed in the inner region of the frame. Further, on the counter substrate 20, a light-shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrodes 9a formed on the TFT array substrate 10, and its upper layer side. A counter electrode 21 made of an ITO film is formed on the.

When the liquid crystal device 100 formed in this way is used in a projection type display device (liquid crystal projector), three liquid crystal devices 100 are used as light valves for RGB, and each liquid crystal device 100 is used. Each of the RG
The light of each color separated through the dichroic mirror for B color separation is incident as projection light. Therefore, the color filter is not formed in the liquid crystal device 100 of each of the above-described embodiments. However, by forming an RGB color filter together with its protective film in a region of the counter substrate 20 facing each pixel electrode 9a, it can be used as a color display device of an electronic device such as a mobile computer, a mobile phone, or a liquid crystal television described later. You can

(Structure and Operation of Liquid Crystal Device 100) Next, the structure and operation of the active matrix type liquid crystal device will be described with reference to FIGS.

FIG. 2 shows the image display area 1 of the liquid crystal device 100.
It is an equivalent circuit diagram of various elements, wirings, etc. in a plurality of pixels formed in a matrix to form 0a.
FIG. 3 is a plan view of pixels adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. FIG. 4 is a cross-sectional view of the liquid crystal device taken along the line AA ′ in FIG. In these figures, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 2, in the image display area 10a of the liquid crystal device 100, a pixel electrode 9a and a pixel switching TFT 30 for controlling the pixel electrode 9a are provided in each of a plurality of pixels formed in a matrix. The data line 6a that is formed and supplies the pixel signal is
It is electrically connected to the source of the FT 30. The pixel signals S1, S2 ... Sn to be written to the data line 6a are line-sequentially supplied in this order. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2, ... Are pulsed to the scanning line 3a at a predetermined timing.
-Gm is configured to be applied line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30 and serves as the switching element TFT 30.
Is turned on for a certain period of time, the pixel signals S1, S2 ... Sn supplied from the data line 6a are written to each pixel at a predetermined timing. The predetermined-level pixel signals S1, S2, ... Sn written in the liquid crystal through the pixel electrode 9a in this manner are held for a certain period of time between the pixel signals S1, S2, ... Sn, which will be described later.

Here, in order to prevent the held pixel signal from leaking, a storage capacitor 70 (capacitor) is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. There is. The storage capacitor 70 holds the voltage of the pixel electrode 9a for a time that is, for example, three digits longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and a liquid crystal device capable of performing display with a high contrast ratio can be realized. The storage capacitor 70 may be formed either between the capacitor line 3b, which is a wiring for forming the capacitor, or between the preceding scanning line 3a. Good.

In FIG. 3, on the TFT array substrate 10 of the liquid crystal device 100, a plurality of transparent pixel electrodes 9a (regions surrounded by dotted lines) are formed in a matrix for each pixel, and the pixel electrodes 9a are arranged vertically and horizontally. Data line 6 along the boundary area of
a (shown by a chain line), a scanning line 3a (shown by a solid line), and a capacitance line 3b (shown by a solid line) are formed.

(Structure of Pixel Switching TFT) FIG.
In the above, the substrate of the TFT array substrate 10 is made of a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the substrate of the counter substrate 20 is made of a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate. A pixel electrode 9a is formed on the TFT array substrate 10, and an alignment film 16 made of a polyimide film or the like that has been subjected to a predetermined alignment treatment such as a rubbing treatment is formed on the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is formed by rubbing an organic film such as a polyimide film. In the counter substrate 20, an alignment film 22 made of a polyimide film is formed also on the upper layer side of the counter electrode 21, and the alignment film 22 is also a film obtained by rubbing the polyimide film.

The TFT array substrate 10 includes a transparent substrate 10
While the base protective film 12 is formed on the surface of b,
On the front surface side, in the image display region 10a, a pixel switching TFT 30 for switching control of each pixel electrode 9a is formed at a position adjacent to each pixel electrode 9a.

The pixel switching TFT 30 may be either an N-channel type or a P-channel type, but in this embodiment, an N-channel type TFT is used.

The pixel switching TFT 3 shown here
0 has an LDD structure, and in the semiconductor film 1a, a channel forming region 1a 'in which a channel is formed by an electric field from the scanning line 3a, a low concentration source region 1b, a low concentration drain region 1c, a high concentration source is formed. A region 1d and a high concentration drain region 1e are formed. In addition, the semiconductor film 1a
A gate insulating film 2b (second gate insulating film) that insulates the semiconductor film 1a from the scanning line 3a is formed on the upper layer side.

On the front surface side of the TFT 30, interlayer insulating films 4 and 7 made of a silicon oxide film are formed. A data line 6a is formed on the surface of the interlayer insulating film 4, and the data line 6a is electrically connected to the high-concentration source region 1d through a contact hole 5 formed in the interlayer insulating film 4. A pixel electrode 9a made of an ITO film is formed on the surface of the interlayer insulating film 7. The pixel electrode 9a is electrically connected to the high-concentration drain region 1e through a contact hole 8 formed in the interlayer insulating films 4 and 7 and the gate insulating film 2. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a.

The extended portion 1 extending from the high-concentration drain region 1e
With respect to f (lower electrode), the capacitance line 3b in the same layer as the scanning line 3a opposes as an upper electrode via an insulating film (dielectric film) formed at the same time as the gate insulating film 2a, so that storage is performed. A capacity 70 is configured.

The TFT 30 preferably has the LDD structure as described above, but has the offset structure in which the impurity ions are not implanted into the regions corresponding to the low concentration source region 1b and the low concentration drain region 1c. May be. Further, the TFT 30 may be a self-alignment type TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting high-concentration impurity ions using the gate electrode (a part of the scanning line 3a) as a mask. . Further, in the present embodiment, the gate electrode of the TFT 30 (the scanning line 3
Although a) has a single gate structure in which only one is arranged between the source and drain regions, two or more gate electrodes may be arranged between them. At this time, the same signal is applied to each gate electrode. In this way, if the TFT 30 is composed of a dual gate (double gate) or a triple gate or more, a channel and a source-
Leakage current at the junction of the drain region can be prevented, and the off-time current can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off current can be further reduced, and a stable switching element can be obtained.

The TFT array substrate 10 thus configured
And the counter substrate 20 are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and between these substrates,
A liquid crystal 50 as an electro-optical material is enclosed and sandwiched in a space surrounded by the sealing material 107 (see FIGS. 1 and 2). The liquid crystal 50 has a predetermined alignment state by the alignment film in a state where the electric field from the pixel electrode 9a is not applied. The liquid crystal 50 is made of, for example, one kind or a mixture of several kinds of nematic liquid crystals.

On the light incident side surface or the light emitting side of the counter substrate 20 and the TFT array substrate 10, the type of liquid crystal 50 used, that is, TN (twisted nematic) mode, STN (super TN) mode, etc., is used. A polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction depending on the operation mode and normally white mode / normally black mode.

(Structure of Complementary Circuit) Referring again to FIG. 1, in the liquid crystal device 100 of the present embodiment, the data line driving circuit 101 and the scanning are performed using the peripheral area of the image display area 10a on the front surface side of the TFT array substrate 10. The line drive circuit 104 is formed. The data line driving circuit 101 and the scanning line driving circuit 104 as described above are basically the N-channel TFT and the P-channel TF shown in FIGS.
It is composed of T and T.

FIG. 5 is a plan view of complementary circuits constituting peripheral circuits such as the scanning line driving circuit 104 and the data line driving circuit 101. FIG. 6 shows a TFT which constitutes this complementary circuit.
6 is a cross-sectional view taken along the line BB ′ of FIG. FIG. 7 is a graph showing the source / drain current-gate voltage characteristics of N-channel type and P-channel type TFTs forming a complementary circuit formed on the TFT array substrate of this embodiment.

5 and 6, the complementary circuit 62 is shown.
Is composed of an N-channel type (first conductivity type) TFT 90 and a P-channel type (second conductivity type) TFT 80. The semiconductor film 60 (outline is shown by a dotted line) forming the TFTs 80 and 90 for these drive circuits is formed in an island shape with the underlying protective film 12 formed on the substrate 10b.

A high potential line 71 and a low potential line 72 are electrically connected to the source regions of the semiconductor film 60 in the TFTs 80 and 90 through contact holes 63 and 64, respectively. In addition, the input wiring 66 includes the gate electrodes 65a and 65a.
The output wiring 67 is electrically connected to the drain region of the semiconductor film 60 via the contact holes 68 and 69, respectively.

An N-channel type TFT 90 and a P-channel type TFT 80 which compose such a complementary circuit 62.
Also, since it is formed through the same process as the image display region 10a, the peripheral circuit region is basically formed with the interlayer insulating films 4 and 7 and the gate insulating film 2b (second gate insulating film). Common structure.

Here, the TF for the N-channel drive circuit
Similar to the pixel switching TFT 30, T90 has a top gate type LDD structure, and the gate electrode 6 formed on the upper layer side on both sides of the channel formation region 91.
5b (second gate electrode) self-aligned with the low-concentration source region 93 and the low-concentration drain region 95.
Are formed. In addition, a high-concentration source region 92 and a high-concentration drain region 94 are formed at positions adjacent to the low-concentration region.

On the other hand, unlike the pixel switching TFT 30 and the N-channel type drive circuit TFT 90, the P-channel type drive circuit TFT 80 first has a semiconductor on the surface of the base protective film 12. A gate electrode 65a (first gate electrode) is formed on the lower layer side of the film 60, and the gate insulating film 2a is formed on the surface of the gate electrode 65a.
(First gate insulating film) is formed. Here, the gate insulating film 2a is formed on the entire surface of the transparent substrate 10b.

Further, a TFT for a P-channel type drive circuit
Reference numeral 80 denotes a gate electrode 65b on the upper layer side of the channel formation region 81 via the gate insulating film 2b (second gate insulating film).
The semiconductor film 60 has a (second gate electrode), and in the semiconductor film 60, the high-concentration source region 82 and the high-concentration drain region 8 are self-aligned with the second gate electrode 65b.
4 are formed. Here, the TFT 80 for the P-channel drive circuit is the TFT for the N-channel drive circuit.
The channel length is shorter than that of 90.

Since the first gate electrode 65a and the second gate electrode 65b are electrically connected, for example, via the contact hole 73 shown in FIG. 5, the same signal is supplied.

In the TFT 80 for the P-channel type drive circuit thus constructed, the first gate electrode 65a is formed.
Are formed to be longer than the channel formation region 81 in the channel length direction, so that the end portion of the first gate electrode 65a is closer to the end portions of the high-concentration source region 82 and the high-concentration drain region 84 than the gate insulating film. They face each other via 2a. Therefore, in the channel length direction, the dimension of the second gate electrode 65b is equal to the dimension of the channel formation region 81, but shorter than the dimension of the first gate electrode 65a.

As described above, in the TFT array substrate 10 of the present embodiment, the N-channel type of the TFT 90 for the N-channel type drive circuit and the TFT 80 for the P-channel type drive circuit which form the complementary circuit 62. The drive circuit TFT 90 has a top gate structure in which the gate electrode 65 is provided only on the upper layer side of the channel formation region 91. On the other hand, a TFT for a P-channel drive circuit
80 includes gate electrodes 65a and 65b on the lower layer side and the upper layer side of the channel formation region 91, and has both a bottom gate structure and a top gate structure.

Therefore, in the complementary circuit 62, the channel 90 is formed only on the upper layer side of the channel formation region 91 in the TFT 90 for the N-channel type drive circuit, while the channel is formed in the TFT 80 for the P-channel type drive circuit. Channels are formed on both the upper layer side and the lower layer side of the formation region 81.

Further, a TFT for a P-channel drive circuit
In 80, the high-concentration source region 82 and the high-concentration drain region 84 are formed in a self-aligned manner with respect to the second gate electrode 65b.

Further, the TF for the P-channel drive circuit
The channel length of T80 is shorter than that of the TFT 90 for the N-channel drive circuit.

Further, the TF for the P-channel drive circuit
The high-concentration source region 82 and the high-concentration drain region 84 of T80 have an overlapping region facing the first gate electrode 65a with the first gate insulating film 2a interposed therebetween.

Therefore, the TF for the P-channel drive circuit
The on-current level of T80 is higher than that of a P-channel TFT having a normal top gate structure. Therefore, even if holes have lower mobility than electrons, the solid line L in FIG.
As can be seen by comparing the on-current level of the TFT 90 for the N-channel drive circuit shown by 9 with the on-current level of the TFT 80 for the P-channel drive circuit shown by the alternate long and short dash line L8 in FIG. , 90 have the same on-current level. Therefore, the TF for the N-channel drive circuit
Since the on-current level of T90 and the on-current level of the TFT 80 for the P-channel drive circuit are balanced, the complementary circuit 62 is less likely to malfunction.

Moreover, the TF for the N-channel drive circuit
Since T90 has an LDD structure, it also has the advantage of high withstand voltage.

(Manufacturing Method of TFT Array Substrate) FIGS. 8 to 11 are process sectional views showing a manufacturing method of the TFT array substrate 10 of this embodiment.

In this embodiment, first, as shown in FIG. 8A, a transparent substrate 10b made of glass or the like cleaned by ultrasonic cleaning or the like is prepared, and then the substrate temperature is 150 ° C. to 450 ° C.
Under the temperature condition of, an insulating film made of a silicon oxide film for forming the base protective film 12 is formed on the entire surface of the transparent substrate 10b by the plasma CVD method to a thickness of 300 nm to 500 nm. As the raw material gas at this time, for example, a mixed gas of monosilane and laughing gas, TEOS and oxygen, or disilane and ammonia can be used.

Next, as shown in FIG.
After forming a conductive film 65 of aluminum, tungsten, molybdenum, tantalum, or the like for forming the first gate electrode 65a on the entire surface of b, a resist mask 401 is formed on the surface of the conductive film 65 by using a photolithography technique.
To form. Next, after etching the conductive film 65 from the opening of the rendist mask 401 to form the gate electrode 65a as shown in FIG. 8C, the resist mask 4 is formed.
01 is removed.

Next, as shown in FIG. 8D, a first gate insulating film 2a made of a silicon oxide film is formed on the surface side of the first gate electrode 65a by using the CVD method or the like.

Next, as shown in FIG. 9 (E), the transparent substrate 10b is heated under the temperature condition of the substrate temperature of 150.degree.
A semiconductor film 1 made of an amorphous silicon film is formed on the entire surface of the substrate by a plasma CVD method to a thickness of 30 nm to 100 nm. As the raw material gas at this time, for example, disilane or monosilane can be used. Next, the semiconductor film 1
A laser beam is irradiated to the substrate to perform laser annealing. As a result, the amorphous semiconductor film 1 is once melted and crystallized through a cooling and solidifying process. At this time, the irradiation time of the laser beam to each area is very short, and the irradiation area is local to the entire substrate, so that the entire substrate is not heated to a high temperature at the same time. Therefore, even if a glass substrate or the like is used as the transparent substrate 10, deformation or cracking due to heat does not occur.

Next, as shown in FIG. 9F, a resist mask 402 is formed on the surface of the semiconductor film 1 by using the photolithography technique. Next, the semiconductor film 1 is etched from the opening portion of the resist mask 402 to form a semiconductor film 1a forming the pixel switching TFT 30 and the driving circuit TFTs 80 and 90 as shown in FIG. 9G. After the semiconductor film 60 to be formed is formed into an island shape, the resist mask 402 is removed.

Next, as shown in FIG. 9H, a second gate insulating film 2b made of a silicon oxide film is formed on the surfaces of the semiconductor films 1a and 60 by using the CVD method or the like. Although illustration is omitted, after this step, impurity ions are implanted into the extended portion 1f of the semiconductor film 1a to form the capacitance line 3b.
And a lower electrode for forming the storage capacitor 70 is formed between and.

Next, contact holes 73 (see FIG. 5) reaching the gate electrode 65a are formed in the gate insulating films 2a and 2b.

Next, as shown in FIG. 10 (I), aluminum, tungsten, molybdenum, tantalum, etc. for forming the scanning lines 3a, the capacitance lines 3b, and the gate electrodes 65b are formed on the entire surface of the transparent substrate 10b. After forming the conductive film 3, a resist mask 403 is formed on the surface of the conductive film 3 using a photolithography technique.

Next, after etching the conductive film 3 from the opening of the resist mask 403 to form the scanning line 3a, the capacitance line 3b, and the second gate electrode 65b as shown in FIG. 10 (J). Then, the resist mask 403 is removed. As a result, the second gate electrode 65b becomes the first gate electrode 65a through the contact hole 73 shown in FIG.
Will be electrically connected to.

Next, as shown in FIG. 10K, the semiconductor film 60 for forming the TFT 80 for the P-channel drive circuit is covered, and the scanning line 3a and the gate electrode 6 are formed.
A resist mask 411 wider than 5b is formed, and in this state, high-concentration N-type impurity ions (phosphorus ions) are applied at a dose amount of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ^2. After the implantation, the high-concentration source regions 1d and 92 and the drain regions 1e and 94 are formed, the resist mask 411 is removed.

Next, as shown in FIG. 10L, a resist mask 412 is formed to cover the semiconductor film 60 for forming the TFT 80 for the P-channel type drive circuit, and in this state, a resist mask 412 for pixel switching is formed. About 0.1 × 10 ¹³ / cm ^{2 of} the semiconductor film 1a forming the TFT 30 and the semiconductor film 60 forming the TFT 90 for the N-channel type driving circuit using the scanning line 3a and the gate electrode 65b as a mask.
A low concentration N-type impurity ion (phosphorus ion) is implanted at a dose amount of about 10 × 10 ¹³ / cm ² so that the impurity concentration is about 1 × 10 ¹⁹ / in a self-aligned manner with respect to the scanning line 3a and the gate electrode 65b. low-concentration source region 1b of cm ³ or less,
After forming 93 and the low-concentration drain regions 1c and 95, the resist mask 412 is removed.

Here, since it is located directly below the scanning line 3a and the gate electrode 65b, the portion where the impurity ions are not introduced becomes the channel forming regions 1a 'and 91 of the semiconductor films 1a and 60 as they are.

Next, as shown in FIG. 10M, a resist mask 413 is formed to cover the semiconductor film 60 for forming the TFT 90 for the N-channel type driving circuit, and in this state, a P-channel type is formed. About 0.1 × 10 ¹⁵ / cm ² to about 10 of high concentration P-type impurity ions (boron ions) are added to the semiconductor film 60 that constitutes the TFT 80 for the drive circuit.
After implanting with a dose amount of × 10 ¹⁵ / cm ² to form the high concentration source region 82 and the drain region 84, the resist mask 413 is removed.

Here, since it is located right below the gate electrode 65b, the portion where the impurity ions are not introduced becomes the channel forming region 81 of the semiconductor film 60 as it is.

Next, as shown in FIG. 11N, after the interlayer insulating film 4 made of a silicon oxide film or the like is formed on the entire surface of the transparent substrate 10b, the interlayer insulating film 4 is formed by photolithography. A resist mask is formed on the surface, and the interlayer insulating film 4 is etched from the opening of the resist mask to form the contact holes 5, 63, 64, 68, 69.
After each of these is formed, the resist mask is removed.

Next, as shown in FIG. 11 (O), an aluminum film or the like for forming the data line 6a (source electrode) or the like is formed on the entire surface of the transparent substrate 10b to a thickness of 500 nm or less.
After the film is formed to a thickness of 1000 nm, a resist mask is formed on the surface of the aluminum film by using the photolithography technique, and the aluminum film is etched through the opening of the resist mask, so that the data line 6a, the high potential line 71, the low potential line 71 Potential line 72, input wiring 66 (see FIG. 4), output wiring 6
After forming 7, the resist mask is removed. As a result, P-channel and N-channel TFTs 80 and 90 are completed in the peripheral circuit region.

Next, as shown in FIG. 11P, after forming an interlayer insulating film 7 made of a silicon oxide film or the like, a resist mask is formed on the surface of the interlayer insulating film 7 using a photolithography technique. The interlayer insulating film 7 is etched from the opening of the resist mask to form a contact hole 8 and then the resist mask is removed.

Next, as shown in FIG. 11Q, after a transparent conductive film such as the ITO film 9 is formed on the entire surface of the transparent substrate 10b, a resist is applied to the surface of the ITO film 9 by photolithography. A mask 407 is formed. Next, the ITO film 9 is etched from the opening of the resist mask 407 to form the pixel electrode 9a as shown in FIG. 4, and then the resist mask 407 is removed.

Then, as shown in FIG. 4, the alignment film 1 is formed.
6 is formed. As a result, the TFT array substrate 10 is completed.

[Other Embodiments] FIG. 12 (A),
3B is a cross-sectional view of complementary circuits formed on another TFT array substrate to which the present invention is applied. 13 is a plan view of a complementary circuit formed on yet another TFT array substrate to which the present invention is applied, and FIG. 14 is a sectional view of the complementary circuit shown in FIG.

In the above embodiment, the TFT 90 for the N-channel drive circuit has the LDD structure, but FIG.
By omitting the low-concentration N-type impurity introduction step shown in (L),
As shown in FIG. 12A, T of the offset gate structure is
The FT 90 may be formed. Further, instead of omitting the high-concentration N-type impurity introduction step shown in FIG.
By introducing a high-concentration N-type impurity in the step shown in 0 (L), a TFT 90 having a self-aligned structure may be formed as shown in FIG. 12 (B).

Further, as shown in FIGS. 13 and 14,
The TFT 90 for the N-channel drive circuit may have a multi-gate structure including a plurality of gate electrodes 65b in the channel length direction to improve withstand voltage.

Furthermore, in the above embodiment, as a semiconductor device, a TF used for an active matrix type liquid crystal device.
Although the T-array substrate has been described as an example, the present invention is applicable to manufacturing an electro-optical device using an electro-optical material other than liquid crystal, for example, a TFT array substrate used in an organic electroluminescence display device, or a semiconductor device other than the electro-optical device. May be applied.

[Application to Electronic Device] Next, an example of an electronic device including the liquid crystal device 100 (electro-optical device) to which the present invention is applied will be described with reference to FIGS. 15, 16A, and 16B. Explain.

FIG. 15 is a block diagram showing the configuration of an electronic apparatus including a liquid crystal device 100 having the same configuration as the electro-optical device according to each of the above embodiments. 16A and 16B are an explanatory view of a mobile personal computer and an explanatory view of a mobile phone as an example of an electronic apparatus using the liquid crystal device according to the present invention.

In FIG. 15, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, the liquid crystal device 100, the clock generation circuit 1008,
And a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Me
memory), RAM (Random AccessMe)
memory), a memory such as an optical disk, a tuning circuit that tunes and outputs a picture signal of a television signal, and the like, and processes an image signal of a predetermined format based on a clock from a clock generation circuit 1008 to display information. Output to the processing circuit 1002. This display information output circuit 10
Reference numeral 02 denotes a well-known processing circuit such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit, which is a digital signal based on display information input based on a clock signal. Drive circuit 1 together with the clock signal CLK.
Output to 004. The drive circuit 1004 is used for the liquid crystal device 10.
Drive 0. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The drive circuit 1004 may be formed on the TFT array substrate that constitutes the liquid crystal device 100, and in addition to this, the display information processing circuit 1002 also has a TF.
It may be formed on the T array substrate.

The electronic equipment having such a configuration includes a projection type liquid crystal display device (liquid crystal projector), a multimedia compatible personal computer (PC), an engineering workstation (EWS), a pager, a mobile phone, a word processor, and the like. Examples thereof include a television, a viewfinder type or a monitor direct-view type video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a touch panel.

That is, as shown in FIG. 16A, the personal computer 180 has a main body 182 having a keyboard 181, and a liquid crystal display unit 183. The liquid crystal display unit 183 is the liquid crystal device 10 described above.
It is configured to include 0.

Further, as shown in FIG. 16B, the mobile phone 190 has a plurality of operation buttons 191 and a display section including the liquid crystal device 100 described above.

[0093]

As described above, according to the present invention, the first
For the conductivity type TFT, the gate electrode is formed only on one of the upper layer side and the lower layer side of the channel formation region, while for the second conductivity type TFT, the gate electrode is formed on the lower layer side and the upper layer side of the channel formation region. A first gate electrode and a second gate electrode are provided on both sides. For this reason,
In the first conductivity type TFT, the channel is formed only in the lower layer or the upper layer of the channel formation region, whereas in the second conductivity type TFT, the channel is formed in both the upper layer side and the lower layer side of the channel formation region. Therefore, the on-current level of the second conductivity type TFT can be increased to the on-current level of the first conductivity type TFT. Therefore, the on-current balance of the first conductivity type TFT and the second conductivity type TFT used in the complementary circuit can be improved, so that a semiconductor device in which malfunction does not easily occur can be provided.

[Brief description of drawings]

1A and 1B are plan views of a liquid crystal device to which the present invention is applied, together with the respective components formed thereon, as seen from the side of a counter substrate, and H in FIG. 1A. FIG.

FIG. 2 is an equivalent circuit diagram of a plurality of pixels formed on the TFT array substrate shown in FIG.

FIG. 3 is a plan view showing a configuration of each pixel formed on the TFT array substrate shown in FIG.

4 is a cross-sectional view of the liquid crystal device shown in FIG. 1 taken along the line AA ′ in FIG.

5 is a plan view of a complementary circuit formed in the drive circuit shown in FIG.

FIG. 6 is a cross-sectional view of the complementary circuit cut at a position corresponding to the line BB ′ shown in FIG.

FIG. 7 is a graph showing source / drain current-gate voltage characteristics of N-channel type and P-channel type TFTs that form a complementary circuit formed on a TFT array substrate to which the present invention is applied.

8A to 8D are process cross-sectional views showing a method for manufacturing a TFT array substrate according to the present invention.

9 (E) to 9 (H) are process cross-sectional views showing a method of manufacturing a TFT array substrate according to the present invention.

10 (I) to (M) are TFTs according to the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing the array substrate.

11 (N) to (Q) are TFTs according to the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing the array substrate.

12A and 12B are cross-sectional views of complementary circuits formed on another TFT array substrate to which the present invention is applied.

FIG. 13 is a plan view of a complementary circuit formed on still another TFT array substrate to which the present invention is applied.

14 is a cross-sectional view of the complementary circuit shown in FIG.

FIG. 15 is a block diagram showing a circuit configuration of an electronic device using the liquid crystal device according to the present invention.

16A and 16B are an explanatory view of a mobile personal computer and an explanatory view of a mobile phone as an example of an electronic apparatus using the liquid crystal device according to the present invention.

FIG. 17 is a sectional view of a complementary circuit formed on a conventional TFT array substrate.

FIG. 18 is a graph showing source / drain current-gate voltage characteristics of N-channel type and P-channel type TFTs forming a complementary circuit formed on a conventional TFT array substrate.

[Explanation of symbols]

1a, 60 semiconductor film 2a gate insulating film (first gate insulating film) 2b gate insulating film (second gate insulating film) 3a scanning line 6a data line 10 TFT array substrate (semiconductor device) 10b as a base of the TFT array substrate Transparent substrate 30 Pixel switching TFT 62 Complementary circuit 65a Gate electrode (first gate electrode) 65b Gate electrode (second gate electrode) 80 P-channel drive circuit TFT (second conductivity type TFT) 90 N-channel type drive circuit TFT (first conductivity type TFT) 100 Liquid crystal device

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 616A 617A 612B F term (reference) 2H092 JA24 NA11 PA06 2H093 NA16 NC09 NC11 NC34 ND37 ND60 NE03 5F048 AC04 BA16 BB10 BB16 BC11 BE08 BG07 CB08 5F110 AA07 BB02 BB04 CC02 DD02 DD03 DD13 EE03 EE04 EE25 EE28 EE30 FF02 FF29 GG02 GG13 GG25 GG45 HJ01 HJ04 HJ13 HL03 HL07 HM14 HM15 NN02 NN02 NN02 NN23 NN02 NN23

Claims (18)

[Claims] 1. A first conductivity type thin film transistor, and a second
In a semiconductor device in which a complementary circuit is formed on a substrate by a conductive type thin film transistor, the first conductive type thin film transistor is gate-insulated with respect to the channel forming region only on one of an upper layer side and a lower layer side of the channel forming region. The thin film transistor of the second conductivity type is provided with a gate electrode opposed to the channel formation region via a first gate insulating film on the lower layer side of the channel formation region via a first gate insulating film. And a second gate electrode facing the channel formation region via a second gate insulating film on the upper layer side of the channel formation region. 2. The semiconductor device according to claim 1, wherein the first conductive type thin film transistor is an N type channel type, and the second conductive type thin film transistor is a P type channel type. 3. The thin film transistor of the second conductivity type according to claim 1, further comprising a high concentration source / drain region formed in self-alignment with the second gate electrode. Semiconductor device. 4. The semiconductor according to claim 3, wherein in the thin film transistor of the second conductivity type, the second gate electrode has a longer dimension in the channel length direction than the first gate electrode. apparatus. 5. The high-concentration source / drain region of the second conductive type thin film transistor according to claim 3, wherein the high-concentration source / drain region has an overlapping region facing the first gate electrode through the first gate insulating film. A semiconductor device characterized by: 6. The method according to any one of claims 1 to 5,
The first conductive type thin film transistor is provided with a gate electrode only on an upper layer side of a channel formation region. 7. The semiconductor device according to claim 6, wherein the high-concentration source / drain regions of the first conductive type thin film transistor are formed in self-alignment with the gate electrode. 8. The LDD (Light) according to claim 6, wherein the first-conductivity-type thin film transistor includes a low-concentration source / drain region in a region facing the end of the gate electrode.
A semiconductor device having a tally doped drain structure or an offset gate structure having a high-concentration source / drain region at a position deviated in the channel length direction from the end of the gate electrode. 9. The semiconductor device according to claim 6, wherein the first conductive type thin film transistor has a multi-gate structure including a plurality of gate electrodes in a channel length direction. 10. The semiconductor device according to claim 1 is used as a TFT array substrate holding an electro-optical material, and the TFT array substrate has a thin film transistor for pixel switching in an image display region and a thin film transistor. An electro-optical device, wherein pixels having pixel electrodes are formed in a matrix, and peripheral circuits having the complementary circuits are formed on the outer peripheral side of the image display area. 11. The electro-optical device according to claim 10, wherein the electro-optical substance is liquid crystal. 12. An electronic apparatus using the electro-optical device defined in claim 10. 13. A method of manufacturing a semiconductor device in which a complementary circuit is formed on a substrate by a first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor, wherein the second-conductivity-type thin film transistor is formed by: A first gate electrode, a first gate insulating film, a semiconductor film forming a channel formation region, a second gate insulating film, and a second gate electrode are formed in this order on the substrate, while the first gate electrode is formed. In forming the conductive type thin film transistor, the semiconductor film forming the channel forming region of the first conductive type thin film transistor is utilized by utilizing the step of forming the semiconductor film forming the channel forming region of the second conductive type thin film transistor. Forming and forming a first gate electrode and a first gate insulating film of the second conductivity type thin film transistor Alternatively, by utilizing one of the steps of forming the second gate electrode and the second gate insulating film of the second conductivity type thin film transistor, the channel formation region is formed only on one of the upper layer side and the lower layer side of the channel formation region. A method of manufacturing a semiconductor device, comprising forming a gate electrode opposed to the gate electrode via a gate insulating film. 14. The thin film transistor according to claim 13, wherein the first conductive type thin film transistor is an N type channel type,
A method of manufacturing a semiconductor device, wherein the conductive type thin film transistor is a P type channel type. 15. The method of forming a thin film transistor of the second conductivity type according to claim 13, wherein a high concentration impurity is introduced into the semiconductor film by using the second gate electrode as a mask. On the other hand, a method of manufacturing a semiconductor device, characterized in that the high-concentration source / drain regions are formed in a self-aligned manner. 16. The semiconductor device according to claim 13, wherein in the first conductivity type thin film transistor, a gate electrode and a gate insulating film are formed only on an upper layer side of a channel formation region. Manufacturing method. 17. The method of manufacturing a semiconductor device according to claim 16, wherein in forming the first conductivity type thin film transistor, impurities are introduced into the semiconductor film by using the gate electrode as a mask. 18. A semiconductor device as defined in claim 13 is formed as a TFT array substrate holding an electro-optical material, and the TFT array substrate has a thin film transistor for pixel switching in an image display region. A method of manufacturing an electro-optical device, further comprising: forming pixels having pixel electrodes in a matrix, and forming a peripheral circuit having the complementary circuit on an outer peripheral side of the image display area.