JP2003243391A - Method for forming interconnection and interconnection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming interconnections and interconnections in which increase of line resistance can be suppressed by preventing occurrence of dishing or errosion incident to chemical mechanical polishing when planarizing a metal barrier layer and a Cu interconnection layer, and open circuit can be prevented by avoiding occurrence of scratch. <P>SOLUTION: Since a conductive protection film is formed on Cu interconnections filling interconnection trenches after a Cu interconnection layer is polished up to a metal barrier layer, the Cu interconnections are protected by the protection film and occurrence of dishing, errosion or scratch is avoided and thereby increase of line resistance and open circuit can be prevented. Furthermore, resistance against electromigration and stress migration is enhanced resulting in interconnections exhibiting excellent resistance against electromigration and stress migration. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method and wiring of a semiconductor device, and more particularly to a wiring flattening technique.

[0002]

2. Description of the Related Art Conventionally, with the reduction of design rules, LSI (Large Scale Integrat) has been developed.
Although the wiring material of ed circuit has been changed from aluminum alloy (Al alloy) to copper (Cu), it is very difficult to process by dry etching used in conventional wiring formation in Cu wiring formation. There is. In order to solve such a problem, a damascene method (Damascene method) is a method in which a wiring groove or a via hole (hole: Via Hole) for forming a Cu wiring is processed and Cu is embedded in the wiring groove or the via hole (hole). Method)
Is widely adopted.

In the damascene method for embedding Cu, the method shown in FIG.
As shown in (a), after forming a wiring groove 102 and a via hole (hole) for burying Cu in the insulating film 101, the wiring groove 102 is formed.
Chemical vapor deposition (CVD method: Ch
electrical vapor deposition or physical vapor deposition method (PVD method: Physical Va)
Barrier metal 1 by por Deposition)
03 (FIG. 6B), a Cu wiring layer 104a is formed on the entire surface of the insulating film 101, and the wiring groove 102 is filled with Cu (FIG. 6C). At this time, the Cu wiring layer 104a that fills the wiring groove 102 is formed into a wiring groove and a hole by plating after forming a Cu seed layer by PVD method or CVD method as seeding necessary for plating film formation called Cu film formation. The Cu wiring layer 104a is formed so that voids and the like do not occur.

The Cu wiring layer 104a is formed to form the wiring groove 10.
After embedding 2 with Cu, the Cu on the surface of the insulating film is removed and flattened (FIG. 7D), and then the barrier metal other than the inside of the wiring groove is removed and flattened in order to remove Cu. Then, the Cu wiring 104 is formed (FIG. 7E).

In the Cu removing process and the barrier metal removing process, in order to suppress an increase in the wiring resistance, Cu and the barrier metal are not left in a portion having no wiring groove or via hole (hole), and further, the wiring groove 102. It is necessary to form Cu so that 90% or more of Cu is embedded therein. Therefore, in this step, the chemical mechanical polishing method (CMP: Ch
(eco-mechanical Polish)
Is widely used.

After embedding Cu in the wiring groove 102 as described above, Cu and barrier metal are filled in the wiring groove 102 and a portion having no hole, and a polishing agent (slurry: Slurry) used by a chemical mechanical polishing (CMP) method. The wafer is cleaned in order to remove metal ions such as the above and further to remove the polishing abrasive grains contained in the slurry from the wafer.

[0007]

However, the wiring groove 102 is formed.
In the damascene method in which Cu is embedded in the substrate and planarized by chemical mechanical polishing (CMP) to form a wiring having a wide wiring width (width between wiring grooves 102) of 5 μm or more, the wiring groove 102 There is a problem that dishing occurs in which the height of the embedded Cu is recessed from the height of the surface of the insulating film 101. For example, in a wiring in which the height of the wiring groove 102 is 5 μm, 0.1 μm is generated by dishing, and the height of Cu embedded in the wiring groove 102 becomes 0.4 μm.
Cu is buried in No. 2 by only about 80%, and accordingly, the wiring resistance increases by 20%.

Furthermore, the damascene method (Damascen
When the wiring is formed by embedding Cu by the method e),
With a pattern having a wiring density of 50% or more, as in the case of dishing, the erosion (E) in which the pattern portion having a wiring density of 50% or more is dented by being removed more than the height of the insulating film.
and the wiring resistance rises.

When polishing Cu and barrier metal by chemical mechanical polishing (CMP) to flatten the surface, a polishing chemical liquid (slurry) is used. Cu is contained in the polishing chemical liquid (slurry). In addition to a chemical liquid that causes a chemical reaction (chemical reaction), abrasive grains (silica, alumina, etc.) for physically scraping are mixed. Not only is this abrasive grain generated, but a certain amount of load is applied in chemical mechanical polishing (CMP) for the purpose of shaving, so
There is also a problem in that Cu, which is a soft material, is scratched by scratches due to the abrasive grains and the applied load. The scratches / scratches are very large and have a depth of 1 μm or more and a wiring height of 0.5 μm,
Wiring breaks will occur at the scratches.

The present invention is directed to dishing resulting from a chemical mechanical polishing method for planarizing a barrier metal and Cu,
An object of the present invention is to provide a wiring forming method and a wiring capable of preventing erosion from occurring and suppressing an increase in wiring resistance, and avoiding occurrence of scratches and preventing wiring breakage. .

[0011]

According to the method of forming a wiring in the present invention, an interlayer insulating film is formed on a substrate, a part of the interlayer insulating film is removed to form a deletion region, and a metal is formed in the deletion region. In a method of forming a wiring in which a metal layer is embedded after forming a barrier layer, a step of removing the metal layer on the metal barrier layer outside the deletion region, and a top surface of the metal layer in the deletion region, The method is characterized by including a step of forming a protective film for protecting the metal layer from removal, and a step of removing the metal barrier layer outside the deleted region and removing the protective film.

In the wiring forming method of the present invention, the metal barrier layer and the metal layer formed on the interlayer insulating film are not continuously polished and removed to form the wiring, but after the metal layer is removed. Since a conductive protective film is formed on the metal wiring that fills the wiring groove and the metal barrier layer is polished and removed while the metal wiring is covered with the protective film, the metal wiring is protected and polished by the protective film. Never. Therefore, it is possible to prevent the wiring portion from being scooped like dishing by the applied load or polishing abrasives when polishing the metal layer by the chemical mechanical polishing method, or being prevented from being scooped out as a whole such as erosion. It is possible to suppress an increase in wiring resistance. Further, since scratches that occur when polishing a metal layer by a chemical mechanical polishing method can be avoided, it is possible to prevent wiring breakage due to scratches, and to form good wiring. You can

For example, when Cu is used for the metal layer, since Cu is a soft material, dishing, erosion, and scratches easily occur. By forming the protective film having a good property, it is possible to realize a good Cu wiring in which the increase of the wiring resistance is suppressed and the breakage of the wiring is prevented without causing the dishing, erosion and scratch.

In the wiring according to the present invention, an interlayer insulating film is formed on a substrate, a part of the interlayer insulating film is removed to form a deleted region, and a metal barrier layer is formed on the interlayer insulating film and the deleted region. In a wiring formed by embedding a metal layer after the formation, the metal layer on the metal barrier layer outside the deleted region is removed, and the metal layer is removed on the upper surface of the metal layer in the deleted region. After forming a protective film for protecting the metal barrier layer from outside, the metal barrier layer outside the deleted region is removed and the protective film is removed.

The wiring of the present invention is not formed by removing the metal barrier layer and the metal layer formed on the interlayer insulating film by continuous polishing, but a metal filling the wiring groove after the metal layer is removed. Since a conductive protective film is formed on the wiring and the metal barrier layer is removed by polishing while the metal wiring is covered with the protective film, the metal wiring is protected by the protective film and is formed without being polished. It Therefore, it is possible to prevent the wiring portion from being scooped like dishing by the applied load or polishing abrasives when polishing the metal layer by the chemical mechanical polishing method, or being prevented from being scooped out as a whole such as erosion. Therefore, it is possible to obtain a wiring in which an increase in wiring resistance is suppressed. In addition, since scratches that occur when polishing a metal layer by a chemical mechanical polishing method can be avoided, it is possible to prevent wiring breakage due to scratches, and realize good wiring. You can

For example, when Cu is used for the metal layer, since Cu is a soft material, dishing, erosion, and scratches are likely to occur. By forming the protective film having a good conductivity, the rise of the wiring resistance can be suppressed without causing dishing, erosion and scratch, and good Cu wiring in which the wiring is prevented from being broken can be realized.

The method of forming a wiring according to the present invention is the method of forming a wiring in which an insulating region is formed on a substrate and a metal layer is embedded in a deletion region formed surrounded by the insulating region. Forming a diffusion prevention layer for preventing diffusion of a metal from the metal layer into the insulation region on the insulation region including, and then depositing the metal layer on the diffusion prevention layer to fill the deleted region. A step of removing the metal layer on the diffusion prevention layer outside the deleted area; a step of forming a protective layer on the upper surface of the metal layer in the deleted area to protect the metal layer from removal; And removing the diffusion prevention layer outside the deleted region and the protective layer.

In the wiring forming method of the present invention, the metal barrier layer and the metal layer formed on the interlayer insulating film are not continuously polished and removed to form the wiring, but after the metal layer is removed. Since a conductive protective film is formed on the metal wiring that fills the wiring groove and the metal barrier layer is polished and removed while the metal wiring is covered with the protective film, the metal wiring is protected and polished by the protective film. Never. Therefore, it is possible to prevent the wiring portion from being scooped like dishing by the applied load or polishing abrasives when polishing the metal layer by the chemical mechanical polishing method, or being prevented from being scooped out as a whole such as erosion. It is possible to suppress an increase in wiring resistance. Further, since scratches that occur when polishing a metal layer by a chemical mechanical polishing method can be avoided, it is possible to prevent wiring breakage due to scratches, and to form good wiring. You can

For example, when Cu is used for the metal layer, since Cu is a soft material, dishing, erosion, and scratches are likely to occur. By forming the protective film having a good property, it is possible to realize a good Cu wiring in which the increase of the wiring resistance is suppressed and the breakage of the wiring is prevented without causing the dishing, erosion and scratch.

In the wiring according to the present invention, an insulating region is formed on a substrate, and a metal from the metal layer to the insulating region is formed on the insulating region including a deleted region surrounded by the insulating region. In a wiring formed by forming a diffusion prevention layer for preventing diffusion, depositing the metal layer on the diffusion prevention layer and burying the metal layer in the deletion region, the diffusion prevention outside the deletion region The metal layer on the layer is removed, and a protective layer for protecting the metal layer from removal is formed on the upper surface of the metal layer in the deleted region, and then the diffusion prevention layer outside the deleted region is removed. The protective layer is removed and formed.

The wiring of the present invention is not formed by removing the metal barrier layer and the metal layer formed on the interlayer insulating film by continuous polishing, but a metal filling the wiring groove after the metal layer is removed. Since a conductive protective film is formed on the wiring and the metal barrier layer is removed by polishing while the metal wiring is covered with the protective film, the metal wiring is protected by the protective film and is formed without being polished. It Therefore, it is possible to prevent the wiring portion from being scooped like dishing by the applied load or polishing abrasives when polishing the metal layer by the chemical mechanical polishing method, or being prevented from being scooped out as a whole such as erosion. Therefore, it is possible to obtain a wiring in which an increase in wiring resistance is suppressed. Further, since scratches that occur when polishing the metal layer by the chemical mechanical polishing method can be avoided, it is possible to prevent wiring breakage due to scratches, and realize good wiring. .

For example, when Cu is used as the metal layer, since Cu is a soft material, dishing, erosion, and scratches are likely to occur. By forming the protective film having a good conductivity, the rise of the wiring resistance can be suppressed without causing dishing, erosion and scratch, and good Cu wiring in which the wiring is prevented from being broken can be realized.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

In the present embodiment, the case where Cu is used as the metal layer embedded in the wiring groove to form the wiring will be described, but Al is used as the metal wiring embedded in the wiring groove.
It may be an alloy or tungsten (W). In this embodiment, the wiring formed by burying Cu in the wiring groove will be described. However, C is formed in the via hole formed in the interlayer insulating film.
Wiring may be formed by embedding u.

Further, in the present embodiment, a single damascene (Single damascene) in which a wiring groove and a via hole (hole) are separately formed and Cu is embedded separately is formed.
The structure of a dual damascene (dual damascene method: dual damascene method) in which a wiring groove and a via hole (hole) are formed at the same time and Cu is embedded at the same time.
It can also be applied to the structure of a mask.

FIG. 1A shows a step of forming a wiring groove in an interlayer insulating film. An interlayer insulating film is laminated and formed as an insulating region on the substrate. The interlayer insulating film 11 is formed, and the wiring groove is formed in the interlayer insulating film 11. The interlayer insulating film 11 can be formed using an oxide film such as a silicon oxide film or a low dielectric constant material, and can be formed by a chemical vapor deposition (CV) method.
D method) and the like. When the Cu wiring is formed in the interlayer insulating film 11 between the upper interlayer insulating film and the lower interlayer insulating film 11, the Cu wiring directly contacts the interlayer insulating film 11 and Cu Insulating film 11
An insulating film barrier layer may be formed in order to prevent the diffusion. The insulating film barrier layer is a silicon nitride film (SiN)
Although it can be formed using silicon carbide (SiC) or the like, when the insulating film barrier layer is not formed as in the present embodiment, Cu is formed at a temperature at which Cu does not diffuse when forming Cu wiring. The wiring will be formed.

The wiring groove 12 is formed on the interlayer insulating film 11. The wiring groove 12 is formed by reactive ion etching (R).
It is formed by anisotropic etching such as IE (Reactive Ion Etching). Interlayer insulation film 1
After the wiring groove 12 is formed on the metal layer 1, the metal barrier layer 13 is formed as shown in FIG. Metal barrier layer 1
3 can be formed by using a material having an excellent barrier property against Cu such as Ta, TaN, TiN, and WN, and can be formed by a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD).
Method) or the like. The thickness of the metal barrier layer 13 depends on the design rule, but is preferably 0.05 μm or less as an example. As shown in FIG. 1B, when the metal barrier layer 13 is formed on the interlayer insulating film 11, the metal barrier layer 13 is formed on the surface of the interlayer insulating film 11 and the inner wall of the wiring groove 12, and the inner wall of the wiring groove 12 is formed. The metal barrier layer 13 formed on the substrate can prevent Cu of the Cu wiring from diffusing into the interlayer insulating film 11.

As shown in FIG. 1C, after the metal barrier layer 13 is formed on the interlayer insulating film 11, the metal barrier layer 1 is formed.
3 has a thick Cu wiring layer 14a formed on the entire surface of the wiring groove 12
Cu is embedded in the inside of. The Cu wiring layer 14a is formed on the entire surface of the metal barrier layer 13. First, a seed layer is formed by a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method). Cu wiring layer 1 by plating method
4a is formed. However, in the plating method, a plating film is not formed unless there is a seed for plating. Therefore, by forming this seed layer and forming it, the seed layer is used as a seed for the Cu wiring layer in the next plating method. 14a can be formed. The film thickness of the seed layer is preferably 0.2 μm or less in consideration of the coverage of the metal barrier layer 13 and the wiring groove 12. The Cu wiring layer 14a is formed as a plated film by the plating method using the seed layer as a seed, and the wiring groove 1 is formed.
2 is filled with Cu. The thickness of the Cu wiring layer 14a varies depending on the thickness of the wiring groove 12, but is 2.0 μm.
The following is preferable. Further, since the metal barrier layer 13 which is a metal is formed on the interlayer insulating film 11,
The Cu wiring layer 14a is formed on the metal barrier layer 13 by plating.
It can be reliably deposited without peeling off.

As shown in FIG. 2D, the Cu wiring layer 14a formed on the metal barrier layer 13 is removed and planarized. The Cu wiring layer 14a is formed by a chemical mechanical polishing method (CM
P) and electropolishing (ECP: Electropolis)
It can be removed by polishing according to h). At this time,
The polishing is stopped from the time when the metal barrier layer 13 appears until before a part of the metal barrier layer 13 on the interlayer insulating film 11 disappears, and the metal barrier layer 13 is polished as a stop film (stopper). At this time, polishing of the metal barrier layer 13 has a peculiar pattern dependency. For example, as shown in FIG. 2D, a pad with a wide wiring pattern (Cu wiring pattern on the right side of FIG. 2D) is used. The bending causes dishing, and erosion occurs in a pattern having a small wiring width and a large wiring density (Cu wiring pattern on the left side in FIG. 2D). This is because the Cu wiring layer 1 is formed in the wiring groove 12 having a wide wiring pattern.
4a is deposited substantially flat, whereas the Cu wiring layer 14a is deposited in the wiring groove 12 having a pattern having a small wiring width and a large wiring density in a raised manner. The polishing is the longest until the time when a part of the metal barrier layer 13 disappears, but Cu may remain on the insulating film due to the pattern dependence peculiar to the polishing. Since the Cu wiring is etched in order to remove the Cu wiring layer corresponding to the thickness, it is not necessary to worry about the pattern dependence.
Cu wiring layer 14a by chemical mechanical polishing (CMP)
Regarding the above polishing, in order to improve the flatness, the polishing is performed at low pressure and high speed rotation. As the polishing chemical (slurry), one having a selectivity of 100 or more between the Cu wiring layer 14a and the metal barrier layer 13 is used. Although not shown in the drawing, since polishing abrasive grains and metal ions mixed in the polishing chemical liquid (slurry) used for polishing are adhered on the wafer as in the flattening step in the conventional example,
After polishing, cleaning is performed to remove polishing abrasive grains and impurities such as metal ions.

After the Cu wiring layer 14a is removed and flattened, in order to form a conductive protective film on the Cu wiring 14 in a step described later, the Cu wiring 14 corresponding to the thickness of the conductive protective film is etched ( In the present embodiment, this etching is called recess etching), and the Cu wiring 14a is formed in the recess structure (FIG. 2E). Wet etching or dry etching is used for the recess etching of the Cu wiring 14. Since this etching requires some control, it is preferable that the etching time be 30 seconds (sec) or more. When performing recess etching by wet etching, HF + H ₂ O ₂ , an acid-based chemical solution, an alkali-based chemical solution, an organic acid chemical solution, or the like can be used. When performing recess etching by dry etching, etching that does not corrode Cu of the Cu wiring 14 is preferable, and sputtering etching that physically removes Cu or the like is available. For example, when Ar or the like is used, Cu
The Cu wiring 14 can be etched by recess etching without corroding the Cu. The etching amount depends on the thickness of the barrier metal and is preferably 1000 Å or less. If the recess amount is too large, the Cu of the Cu wiring 14 is
The part decreases and the resistance value increases. Further, if the recess amount is too small, the conductive protective film that prevents scratches when the metal barrier layer 13 is removed in the process described below disappears,
For example, scratches may occur when the metal barrier layer 13 is removed by chemical mechanical polishing (CMP). Regarding the standard of the etching amount in the recess etching of the Cu wiring 14, the height of the Cu wiring 14 is defined as x.
(Μm) and the thickness of the metal barrier layer 13 is y (μm), it is preferable that the etching amount t (μm) = 0.1x + y. If the polishing of the Cu wiring layer 14a is stopped in a completely non-dishing state when polishing is stopped, a large polishing residue occurs in a dense wiring pattern. Polishing is stopped at the time. At this time, even if the polishing residue of the Cu wiring layer 14a remains on the metal barrier layer 13, the recess structure can be formed and the polishing residue can be removed by performing recess etching.

4 and 5 show an example of a polished state in the flattening step of the Cu wiring layer 14a. 4 (a) and 4
As shown in (b), when Cu remains on the wiring groove 12, the polishing amount is insufficient, so that the Cu wiring layer 14a is further polished and removed. At this time, Cu
Being careful not to polish the wiring layer 14a too much, recess etching is performed after the polishing to remove only the thickness of the conductive protective film. In the case shown in FIG. 4C, the Cu wiring layer 14
Since a is in a range that can be removed by recess etching, the margin of etching (Margin)
The etching may be performed as shown in FIG. With respect to FIG. 5D, if the Cu wiring layer 14a is removed by recess etching, the amount of Cu remaining in the wiring groove 12 is reduced. A protective film is selectively formed. If the Cu wiring layer 14a is excessively polished as shown in FIG.
Be careful not to over-polish the Cu wiring layer 14a, because Cu will be insufficient inside and wiring resistance will increase. In the present embodiment, if the Cu wiring layer 14a can be polished with good control, the Cu wiring layer 14 as shown in FIG.
a can be polished, thereby reducing process steps.

FIG. 2F shows a step of forming the conductive protective film 15 on the Cu wiring 14. The conductive protective film 15 is
Since it is a metal-based conductive film that can be selectively grown on the Cu wiring 14, it is a CoWP film or the like. This conductive protective film 15
Prevents the Cu wiring 14 from being dished, eroded, scratched, or the like when the metal barrier layer 13 described later is removed by polishing, and the upper wiring of the Cu wiring 14 is electrically connected to the wiring 14. Therefore, it has conductivity. Further, since the conductive protective film 15 is polished at the same time when the metal barrier layer 13 is polished in the process described below,
At this time, a material having substantially the same strength as that of the metal barrier layer 13 is used so that the surface of the Cu wiring 14 is not excessively polished and exposed.

As shown in FIG. 3 (g), the conductive protective film 1
5 is removed at the same time when the metal barrier layer 13 is polished, and the height of the conductive protective film 15 is flattened to the height of the interlayer insulating film 11. For the metal barrier layer 13 and the conductive protective film 15, there are a chemical mechanical polishing method (CMP), an electric field polishing method (ECP), dry etching, and the like. When planarizing by chemical mechanical polishing (CMP), since planarity is important, the planarizing process is performed at low pressure and high speed rotation. In the present embodiment, since the step formed on the wiring 14 of the wiring groove 12 is filled with the conductive protective film 15,
The polishing can be applied uniformly on the flat surface of the interlayer insulating film 11 so that the metal barrier layer 13 can be polished.
It can be uniformly polished up to 1. Further, the slurry used for polishing is the conductive protective film 15 in this embodiment.
Since Cu is not polished by the above method, in order to improve the polishing rate, polishing particles may be contained in the insulating film to the extent that scratches do not enter. When flattening by dry etching, anisotropic etching such as ordinary reactive ion etching (RIE) is performed to etch the metal barrier layer 13 and the conductive protective film 15 without a selection ratio. Further, since Cu of the Cu wiring 14 is not exposed on the surface of the interlayer insulating film 11, the surface of the interlayer insulating film 11 is not corroded by Cu. In addition to the case of using the reactive ion etching (RIE), the metal barrier layer 13
Since the film thickness is as thin as 500 Å or less, it can be planarized by using physical etching such as sputtering etching using Ar or the like. Although not shown in the drawing, as in the conventional flattening process, since polishing abrasive grains and metal ions mixed in the polishing chemical liquid (slurry) used for polishing are attached on the wafer, After that, cleaning is performed to remove impurities such as abrasive grains and metal ions.

In the conventional example, the Cu wiring layer 14a and the metal barrier layer 13 are continuously polished and removed by the chemical mechanical polishing method (CMP). However, after the Cu wiring layer 14a is polished, the metal barrier layer is removed. When polishing is performed until 13 is exposed, the polishing rate of the metal barrier layer 13 is lower than the polishing rate of the Cu wiring layer 14a, so that the metal barrier layer 13 is more difficult to polish than the Cu wiring layer 14a. Therefore, when polishing the metal barrier layer 13, a large load is applied to the wafer and the like, and C is applied in a state where a large load is applied.
When the metal barrier layer 13 is continuously polished following the u wiring layer 14a, a weak portion such as a wide wiring groove 12 or a portion having a large wiring density is loaded, and a weak portion having a large load is scraped more. Will end up. In particular, when wiring is formed using Cu, since Cu is a soft material, a load is applied to the Cu wiring layer 14a formed in a wide wiring groove 12 or a weak portion such as a portion having a large wiring density,
A large amount of Cu that is subjected to a large load is scraped off. For example, in a wide wiring width, there is a phenomenon of dishing of a wiring portion, which is called dishing. To do. Therefore, the wiring resistance of the Cu wiring 14 increases due to dishing or erosion that occurs in the Cu wiring 14. Further, since the polishing pressure is applied even after the metal barrier layer 13 is polished and the polishing abrasive particles are mixed in the polishing chemical liquid (slurry), it is generated when the metal barrier layer 13 is polished and removed. Cannot recover dishing or erosion. Further, since the metal barrier layer 13 and the Cu wiring layer 14a are polished in the polishing grains, an applied load is applied for polishing,
Occurrence of scratches on soft Cu cannot be avoided. Therefore, not only the wiring resistance of the Cu wiring 14 increases due to dishing or erosion that occurs in the Cu wiring 14, but also the wiring breaks due to the occurrence of scratches.

On the other hand, in the present embodiment, as described above, the wiring groove 1 is formed before the metal barrier layer 13 is polished.
Since the conductive protective film 15 is selectively formed on the Cu wiring 14 that embeds 2, the wiring 14 is weakly subjected to a large load when the metal barrier layer 13 is polished by the conductive protective film 15 when the metal barrier layer 13 is polished. Part of Cu
The wiring 14 is protected. Further, when polishing the metal barrier layer 13, a conductive protective film 15 for protecting the Cu wiring 14 is provided.
However, the Cu wiring 14 is not polished, and the Cu wiring 14 is not affected by the polishing of the metal barrier layer 13. Therefore, the wiring portion of the Cu wiring 14 is not scooped like dishing, and the entire dense wiring is not scooped like erosion, and scratches on soft Cu due to the abrasive grains can be avoided. Then, by polishing the metal barrier layer 13 and the conductive protective film 15, it is possible to prevent dishing and erosion without polishing the Cu wiring 14 and suppress an increase in wiring resistance, and avoid occurrence of scratches. It is possible to prevent wiring breakage.

As described above, since it is possible to prevent dishing and erosion caused by an excessive applied load applied to the Cu wiring layer 14a and suppress an increase in wiring resistance, the Cu wiring embedded in the wiring groove 12 is prevented. 14 is prevented from decreasing due to dishing or erosion, and electromigration (Electro Mi
gration) and stress migration (Str
The Cu wiring 14 excellent in ess migration resistance can be formed. Also, the Cu wiring layer 14a
Since it is possible to prevent the occurrence of scratches due to excessive applied load and polishing abrasive particles applied to
It is possible to improve electromigration and stress migration without causing voids or wire breakage in the Cu wiring 14, and to realize a highly reliable Cu wiring 14.

Furthermore, since dishing and erosion are eliminated, a process with a margin can be performed when the wiring trench 12 on the interlayer insulating film 11 is patterned by the lithography technique and is formed by anisotropic etching. No step is formed on the Cu wiring 14. Therefore, it is possible to prevent Cu residue from being generated due to a step when forming a wiring on the upper layer on the interlayer insulating film 11, and by relaxing the step, the process margin is increased, and the stacked wiring integration ( Integration) can be simplified. Further, since scratches are eliminated, the step of inspecting foreign matter can be reduced, and the process margin can be increased by simplifying the laminated wiring integration.

[0038]

According to the method of forming a wiring of the present invention, when the metal barrier layer which is the diffusion preventing layer and the metal layer which fills the deleted region are planarized, the metal which fills the wiring groove after removing the metal layer is used. By forming a conductive protective film on the wiring, the wiring part is cut off like dishing due to excessive applied load and polishing abrasives applied on the metal wiring at the time of flattening, or the entire dense wiring like erosion. It is possible to prevent scraping off and to prevent scratches caused by the abrasive grains.

Since it is possible to prevent dishing and erosion that occur in the wiring, it is possible to form a wiring having excellent resistance to electromigration and stress migration, and to avoid the occurrence of scratches due to abrasive grains. As a result, there is no void or disconnection in the wiring, and resistance to electromigration and stress migration can be improved. Therefore, according to the wiring forming method of the present invention, it is possible to form a highly reliable wiring.

Furthermore, since dishing and erosion are eliminated, a process with a margin can be performed when the wiring groove and the via hole on the interlayer insulating film are patterned by the lithography technique and formed by anisotropic etching. Will not occur. Therefore, it is possible to prevent Cu residue from being generated due to the step when forming the wiring on the upper layer on the interlayer insulating film, and the relaxation of the step increases the process margin and simplifies the laminated wiring integration. it can. Further, since scratches are eliminated, the step of inspecting foreign matter can be reduced, and the process margin can be increased by simplifying the laminated wiring integration.

[Brief description of drawings]

1A and 1B show steps of forming a wiring groove, forming a metal barrier layer, and forming a Cu wiring layer in a method for forming a wiring of the present invention, FIG. 1A is a sectional view of a wiring groove forming step, and FIG.
Is a process sectional view of forming a metal barrier layer, and (c) is C
It is a process sectional view of u wiring layer formation.

FIG. 2 shows a step of polishing a Cu wiring layer, etching a Cu wiring, and selectively forming a conductive protective film on a Cu wiring layer in the method for forming a wiring of the present invention, and (d) shows a Cu wiring layer polishing. 2E is a process sectional view of the Cu wiring layer etching, and FIG. 3F is a process sectional view of selectively forming the conductive protective film.

FIG. 3 shows a step of polishing a metal barrier layer and a conductive protective film in the wiring forming method of the present invention, and (g) is a sectional view of a step of polishing the metal barrier layer and the conductive protective film.

4A and 4B show a polishing state of a Cu wiring layer in the wiring forming method of the present invention, wherein FIG. 4A is a sectional view of a step with insufficient polishing, FIG. 4B is a sectional view of a step with insufficient polishing, and FIG. [FIG. 3] is a process cross-sectional view showing insufficient polishing.

5A and 5B show a polished state of a Cu wiring layer in the wiring forming method of the present invention, FIG. 5D is a sectional view of a step requiring etching, and FIG.

FIG. 6 is a view showing the formation of a wiring groove in the conventional wiring forming method,
The steps of forming a barrier metal and a Cu wiring layer are shown.
(A) is a process sectional view of forming a wiring groove, (b) is a process sectional view of forming a barrier metal, and (c) is a process sectional view of forming a Cu wiring layer.

FIG. 7 shows a step of polishing a Cu wiring layer and a barrier metal in a conventional wiring forming method, and (d) shows Cu.
It is a process sectional view of wiring layer polish, and (e) is a process sectional view of barrier metal polish.

[Explanation of symbols]

11 Interlayer insulation film 12 wiring groove 13 Metal barrier layer 14a Cu wiring layer 14 Cu wiring 15 Conductive protective film 101 insulating film 102 wiring groove 103 Barrier metal 104a Cu wiring layer 104 Cu wiring

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kaori Tai             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Yutaka Ooka             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation (72) Inventor Yuji Segawa             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F term (reference) 5F033 HH07 HH11 HH21 HH32 HH33                       HH34 JJ01 JJ07 JJ11 JJ21                       JJ32 JJ33 JJ34 KK01 KK03                       KK07 LL04 MM01 MM02 MM12                       MM13 NN06 NN07 PP06 PP14                       PP27 PP28 PP33 QQ09 QQ11                       QQ13 QQ14 QQ16 QQ19 QQ24                       QQ37 QQ46 QQ48 QQ91 RR01                       RR04 RR06 SS11 XX00 XX01                       XX03 XX05 XX06 XX14 XX18                       XX28

Claims (22)

[Claims] 1. An interlayer insulating film is formed on a substrate, a part of the interlayer insulating film is removed to form a deleted region, a metal barrier layer is formed in the deleted region, and then a metal layer is embedded. In the method for forming a wiring, a step of removing the metal layer on the metal barrier layer outside the deleted area, and forming a protective film for protecting the metal layer from removal on the upper surface of the metal layer in the deleted area A method of forming a wiring, comprising: a step of removing the metal barrier layer outside the deleted region and a step of removing the protective film. 2. The deleted region is a wiring groove, a via hole,
The wiring forming method according to claim 1, wherein the wiring is a contact hole or a combination thereof. 3. The metal layer, after forming a seed layer,
The wiring forming method according to claim 1, wherein the wiring is formed by a plating method. 4. The wiring forming method according to claim 1, wherein the metal layer is formed using copper. 5. The method for forming a wiring according to claim 1, wherein the removal of the metal layer is performed by a chemical mechanical polishing method or an electropolishing method. 6. The method for forming a wiring according to claim 1, wherein after the metal layer is removed, a recess is formed on the upper surface of the metal layer in the deleted region. 7. After removing the metal layer, a recess is formed on the upper surface of the metal layer in the deleted region by anisotropic etching,
2. The wiring forming method according to claim 1, wherein the protective film is selectively formed in the recess. 8. The method of forming a wiring according to claim 1, wherein the protective film is a conductive film. 9. The method for forming a wiring according to claim 1, wherein the metal barrier layer is removed by a chemical mechanical polishing method or an anisotropic etching method. 10. An interlayer insulating film is formed on a substrate, a part of the interlayer insulating film is removed to form a deletion region, and a metal barrier layer is formed on the interlayer insulating film and the deletion region. In a wiring formed by embedding a metal layer, the metal layer on the metal barrier layer outside the deleted region is removed, and the metal layer upper surface in the deleted region is protected from removal of the metal layer. A wiring formed by removing the metal barrier layer outside the deleted region and removing the protective film after the film is formed. 11. A method of forming a wiring in which an insulating region is formed on a substrate, and a metal layer is embedded in a deleted region formed surrounded by the insulating region, wherein the insulating region including the deleted region is formed. Forming a diffusion prevention layer that prevents diffusion of metal from the metal layer into the insulating region, and then depositing the metal layer on the diffusion prevention layer to fill the deletion region; Removing the metal layer on the diffusion prevention layer, forming a protective layer on the upper surface of the metal layer in the deletion region to protect the metal layer from removal, and preventing diffusion outside the deletion region And a step of removing the protective layer as well as removing a layer. 12. The method of forming a wiring according to claim 11, wherein the insulating region is an interlayer insulating film. 13. The wiring forming method according to claim 11, wherein the deleted region is a wiring groove, a via hole, a contact hole, or a combination thereof. 14. The wiring forming method according to claim 11, wherein the metal layer is formed using copper, tungsten, aluminum, or a combination thereof. 15. The method of claim 11, wherein the metal layer is formed by a plating method after forming a seed layer. 16. The method for forming a wiring according to claim 11, wherein the removal of the metal layer is performed by a chemical mechanical polishing method or an electropolishing method. 17. The method according to claim 11, wherein a recess is formed on the upper surface of the metal layer in the deleted region after removing the metal layer. 18. The method according to claim 18, wherein after the metal layer is removed, a concave portion is formed on the upper surface of the metal layer in the deleted region by anisotropic etching, and the protective layer is selectively formed in the concave portion. 11. The method for forming wiring according to item 11. 19. The wiring forming method according to claim 11, wherein the protective layer is a conductive film. 20. The wiring forming method according to claim 11, wherein the diffusion prevention layer is a metal barrier layer. 21. The method of forming a wiring according to claim 11, wherein the diffusion prevention layer is removed by a chemical mechanical polishing method or an anisotropic etching method. 22. Diffusion for preventing diffusion of metal from the metal layer into the insulating region, wherein an insulating region is formed on a substrate, and the insulating region includes a deleted region surrounded by the insulating region. In a wiring formed by depositing the metal layer on the diffusion prevention layer and burying the metal layer in the deletion region after forming the prevention layer, the wiring on the diffusion prevention layer outside the deletion region. After the metal layer is removed and a protective layer for protecting the metal layer from removal is formed on the upper surface of the metal layer in the deleted region, the diffusion prevention layer outside the deleted region is removed and the protective layer is A wiring characterized by being removed and formed.