JP2003243384A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor deviceInfo
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- JP2003243384A JP2003243384A JP2002043242A JP2002043242A JP2003243384A JP 2003243384 A JP2003243384 A JP 2003243384A JP 2002043242 A JP2002043242 A JP 2002043242A JP 2002043242 A JP2002043242 A JP 2002043242A JP 2003243384 A JP2003243384 A JP 2003243384A
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- Prior art keywords
- insulating film
- film
- density
- low
- density insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、層間絶縁膜を改良
して製造プロセスの簡素化、及び、低コスト化を実現
し、高速動作性及び信頼性を向上した半導体装置を製造
することができる方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can improve the interlayer insulating film to simplify the manufacturing process and reduce the cost, and to manufacture a semiconductor device with improved high-speed operability and reliability. Regarding the method.
【０００２】[0002]
【従来の技術】一般に、半導体装置の多層配線に於ける
信号伝播速度の低下は、配線抵抗及び配線間の寄生容量
に依って決定されるのであるが、現在、半導体装置の高
集積化に起因して配線幅及び配線間隔が狭くなり、配線
抵抗が上昇し、また、配線間の寄生容量が増大してい
る。2. Description of the Related Art Generally, a decrease in signal propagation speed in a multi-layer wiring of a semiconductor device is determined by a wiring resistance and a parasitic capacitance between the wirings. As a result, the wiring width and the wiring interval are narrowed, the wiring resistance is increased, and the parasitic capacitance between the wirings is increased.
【０００３】半導体装置に於ける絶縁膜の容量は、配線
厚を薄く、且つ、断面積を小さくすることで低減できる
が、配線厚を薄くすると配線抵抗が上昇する為、高速動
作化に結び付かない。The capacitance of the insulating film in a semiconductor device can be reduced by reducing the wiring thickness and the cross-sectional area. However, thinning the wiring thickness increases wiring resistance, which leads to high-speed operation. It doesn't.
【０００４】高速動作化を図る為には、配線の低抵抗化
及び絶縁膜の低誘電率化が必須であり、半導体装置の性
能を支配する大きな要素である配線の低抵抗化及び絶縁
膜の低誘電率化が必須である。In order to achieve high-speed operation, it is indispensable to reduce the resistance of the wiring and the dielectric constant of the insulating film, and to reduce the resistance of the wiring and the insulating film, which are major factors that govern the performance of the semiconductor device. A low dielectric constant is essential.
【０００５】半導体装置を高集積化する為の配線間隔の
狭小化に伴う配線間の容量増大に起因する信号の配線遅
延は、
Ｔ∝ＣＲ ・・・・（２）
Ｔ：配線遅延
Ｒ：配線抵抗
Ｃ：配線間容量
で表される。また、式（２）に於いて、
Ｃ＝ε0 εＳ／ｄ ・・・・（３）
ε0 ：真空の誘電率
Ｓ ：電極面積
ｄ ：配線間隔
である。A wiring delay of a signal due to an increase in capacitance between wirings due to a narrowing of a wiring interval for high integration of a semiconductor device is: T∝CR (2) T: Wiring delay R: Wiring Resistance C: Represented by wiring capacitance. Further, in the formula (2), C = ε 0 εS / d (3) ε 0 : vacuum permittivity S: electrode area d: wiring interval.
【０００６】従って、配線遅延Ｔを小さくする為には、
絶縁膜の低誘電率化が有効な手段であることが判る。Therefore, in order to reduce the wiring delay T,
It can be seen that lowering the dielectric constant of the insulating film is an effective means.
【０００７】従来、絶縁膜の材料として、二酸化珪素
（ＳｉＯ2 ）、窒化珪素（ＳｉＮ）、燐珪酸ガラス（ｐ
ｈｏｓｐｈｏｓｉｌｉｃａｔｅ ｇｌａｓｓ：ＰＳＧ）
などの無機材料が用いられ、半導体装置に多用されてい
るＣＶＤ（ｃｈｅｍｉｃａｌｖａｐｏｕｒ ｄｅｐｏｓ
ｉｔｉｏｎ）法で成膜したＳｉＯ2 膜の誘電率は４程度
である。Conventionally, silicon dioxide (SiO 2 ), silicon nitride (SiN), phosphosilicate glass (p
hosphosilicate glass (PSG)
CVD (chemical vapor deposition), which is widely used for semiconductor devices, uses inorganic materials such as
The SiO 2 film formed by the ionization method has a dielectric constant of about 4.
【０００８】また、低誘電率材料膜としては、ＣＶＤ法
で成膜されるＳｉＯＦ膜、ポリイミドなどの有機系高分
子膜、更にまた、近年では、膜中に多数の空孔を生成さ
せることで誘電率を低下させることを目的とした多孔質
膜などが実用化されようとしている。As the low dielectric constant material film, a SiOF film formed by a CVD method, an organic polymer film such as polyimide, and more recently, by forming a large number of holes in the film. Porous films for the purpose of lowering the dielectric constant are about to be put into practical use.
【０００９】然しながら、ＣＶＤ法で成膜されたＳｉＯ
Ｆ膜の誘電率は低いとはいいながら約３．３〜３．５程
度にしかならず、３以下にすることは困難であり、従っ
て、配線間の容量低減は充分ではなく、また、吸湿性が
高いことから、使用環境に依っては、却って誘電率が上
昇してしまう旨の問題がある。However, SiO formed by the CVD method
Although the dielectric constant of the F film is low, it is only about 3.3 to 3.5, and it is difficult to reduce the dielectric constant to 3 or less. Since it is high, there is a problem that the dielectric constant rather rises depending on the use environment.
【００１０】また、ポリイミドなどの有機系高分子膜は
２〜３程度の低誘電率を達成することができるものの、
耐熱性や密着性が低い為、半導体装置の製造プロセスに
制限を加えることになる。Although an organic polymer film such as polyimide can achieve a low dielectric constant of about 2 to 3,
Since the heat resistance and the adhesion are low, it limits the manufacturing process of the semiconductor device.
【００１１】前記したようなことから、今後、要求され
る低誘電率を達成する為には、シリカ系多孔質膜が有望
と考えられているが、加工プロセスが複雑なこと、そし
て、エッチング表面が粗面になり易いことなどの問題が
ある。From the above, silica-based porous films are considered to be promising in order to achieve the required low dielectric constant in the future, but the processing process is complicated and the etching surface is However, there is a problem that the surface tends to be rough.
【００１２】例えば、多孔質膜を層間絶縁膜としてデュ
アル・ダマシン構造を形成する場合には、
（１） 多孔質膜であることに起因して膜の密度に分
布、即ち、粗密が存在し、エッチングに依って配線溝を
形成した際、該粗密が溝底に転写されてしまう。即ち、
エッチング表面にラフネスを生じることになるから、バ
リア・メタルで被覆する場合にも、その影響が現れてし
まう。
（２） 膜質が低密度であることから、エッチング・レ
ートが大きく、コントロール・エッチングが困難であ
る。従って、配線溝を正確に形成しようとする場合に
は、エッチング停止層を用いることが必要となり、加工
プロセスが複雑になることは回避できない。
（３） エッチング停止層を用いる場合には、通常、多
孔質シリカとのエッチング選択比を確保しなければなら
ないので気相成長膜を用いるようにしている。従って、
多孔質膜の成膜と気相成長膜の成膜とを交互に行う為、
コスト高になることは避けられない。
と云う問題がある。For example, when a dual damascene structure is formed by using a porous film as an interlayer insulating film, (1) the density of the film is distributed due to the porous film, that is, the density is uneven, When the wiring groove is formed by etching, the density is transferred to the groove bottom. That is,
Since roughness will be generated on the etching surface, the influence will appear even when coating with a barrier metal. (2) Since the film quality is low, the etching rate is high and control etching is difficult. Therefore, in order to accurately form the wiring groove, it is necessary to use the etching stop layer, and it is unavoidable that the processing process becomes complicated. (3) When the etching stopper layer is used, it is usually necessary to secure an etching selection ratio with respect to the porous silica, so that the vapor phase growth film is used. Therefore,
Since the formation of the porous film and the formation of the vapor phase growth film are performed alternately,
High costs are inevitable. There is a problem called.
【００１３】[0013]
【発明が解決しようとする課題】本発明では、エッチン
グした場合の表面ラフネスの解消、エッチング停止層な
どの加工性の向上、多孔質膜の保護効果の向上を目的と
して、半導体装置に於ける絶縁膜として低密度膜と高密
度膜との積層膜を用い、しかも、その低密度膜と高密度
膜とからなる積層膜を同一装置内で実現できるようにす
る。SUMMARY OF THE INVENTION In the present invention, for the purpose of eliminating the surface roughness when etching, improving the workability of the etching stop layer and the like, and improving the protective effect of the porous film, the insulation in the semiconductor device is improved. A laminated film of a low density film and a high density film is used as a film, and a laminated film of the low density film and the high density film can be realized in the same device.
【００１４】[0014]
【課題を解決するための手段】本発明では、半導体装置
に於ける絶縁膜として、低密度膜と高密度膜との積層膜
を用いることで、優れた特性の多層構造体を実現するの
であるが、低密度膜と高密度膜とを組み合わせること自
体は既に知られていることである。According to the present invention, by using a laminated film of a low density film and a high density film as an insulating film in a semiconductor device, a multilayer structure having excellent characteristics is realized. However, it is already known to combine a low-density film and a high-density film.
【００１５】然しながら、この多層構造体を用いるにし
ても、それを形成するに際し、プロセスが複雑化された
り、高コスト化されたり、勿論、半導体装置の高速動作
性や信頼性が損なわれるようでは実用にならない。However, even if this multi-layer structure is used, the process is complicated and the cost is high when it is formed, and of course, the high-speed operability and reliability of the semiconductor device are impaired. Not practical.
【００１６】本発明では、低密度絶縁膜（例えば多孔質
膜）と高密度絶縁膜（例えば多孔質化されていない膜）
との積層構造を同一成膜装置内で塗布法に依って成膜す
ることが基本になっている。即ち、半導体基板上に低密
度絶縁膜となる材料を塗布してプリベークを行い、次い
で、高密度絶縁膜となる材料を塗布してプリベークを行
う工程を繰り返して積層膜を形成した後、一括してキュ
アすることに依って多層構造体としている。In the present invention, a low-density insulating film (for example, a porous film) and a high-density insulating film (for example, a non-porous film)
Basically, the laminated structure of and is formed by a coating method in the same film forming apparatus. That is, a step of applying a material for a low-density insulating film on a semiconductor substrate and performing pre-baking, and then applying a material for a high-density insulating film and performing pre-baking is repeated to form a laminated film and then collectively. It is made into a multi-layered structure by being cured.
【００１７】ここで、絶縁膜形成材料を塗布してプリベ
ークして不溶化、即ち、ゲル化することは重要であり、
このようにすることで、低密度膜と高密度膜とを積層し
ても組成物のミキシングがおこらず、従って、低密度膜
及び高密度膜は、それぞれの特性を維持することができ
る。Here, it is important that the insulating film forming material is applied and pre-baked to insolubilize, that is, gelate.
By doing so, mixing of the composition does not occur even when the low-density film and the high-density film are laminated, and therefore, the low-density film and the high-density film can maintain their respective properties.
【００１８】前記手段を採ることに依り、層間絶縁膜と
して作用する各絶縁膜に気相成長膜を用いる必要はなく
なり、低密度絶縁膜も高密度絶縁膜も全て同一成膜装置
内で塗布法を適用して積層形成することが可能であり、
長い処理時間を必要とするキュアも一括で行うから、短
時間且つ低コストで多層配線を実現する為の多層構造体
を形成することができ、しかも、キュア時に積層膜が相
互に架橋する為、層間の密着強度も向上する。また、多
層構造体をデュアル・ダマシン加工する場合に於いて、
上層に配線溝を形成する際、下層の表面側に在る高密度
絶縁膜をエッチング停止層として作用させることがで
き、従って、配線溝底のラフネスを低減することが可能
であり、その結果、バリア・メタルの被覆性は良好に維
持される。更にまた、上層の表面側に在る絶縁膜は高密
度であるから、高硬度で且つ高薬品耐性をもち、従っ
て、ＣＭＰ（ｃｈｅｍｉｃａｌ ｍｅｃｈａｎｉｃａｌ
ｐｏｌｉｓｈｉｎｇ）を適用してメタル除去を行う際
に損傷され易い低密度絶縁膜の保護膜としての役割を果
たすことができる。By adopting the above means, it is not necessary to use a vapor phase growth film for each insulating film acting as an interlayer insulating film, and a low density insulating film and a high density insulating film are all applied in the same film forming apparatus. It is possible to apply
Since curing that requires a long processing time is also performed collectively, it is possible to form a multilayer structure for realizing multilayer wiring in a short time and at low cost, and moreover, since the laminated films cross-link each other during curing, The adhesion strength between layers is also improved. In addition, in the case of dual damascene processing of the multilayer structure,
When forming the wiring groove in the upper layer, the high-density insulating film existing on the surface side of the lower layer can act as an etching stop layer, and thus it is possible to reduce the roughness of the wiring groove bottom. The barrier metal coverage is maintained well. Furthermore, since the insulating film on the surface side of the upper layer has a high density, it has high hardness and high chemical resistance, and therefore CMP (chemical mechanical) is used.
It can play a role as a protective film for a low density insulating film which is easily damaged when removing metal by applying the polishing.
【００１９】[0019]
【発明の実施の形態】本発明に依る半導体装置に採り入
れた低密度の絶縁膜、並びに、高密度の絶縁膜は、公知
である下記の一般式（１）で記述されるアルコキシシラ
ンの部分加水分解縮合物からなる塗布型低誘電率絶縁膜
形成組成物を用いて形成することができる。BEST MODE FOR CARRYING OUT THE INVENTION A low-density insulating film and a high-density insulating film incorporated in a semiconductor device according to the present invention are known to be partially hydrolyzed alkoxysilane described by the following general formula (1). It can be formed by using a coating type low dielectric constant insulating film forming composition comprising a decomposition condensate.
【００２０】 Ｒ1 l Ｒ2 m Ｒ3 n Ｓｉ（ＯＲ4 ）4-l-m-n ・・・・（１） Ｒ1 、Ｒ2 、Ｒ3 ：Ｈ或いはＣＨ3 基 （Ｒ1 、Ｒ2 、Ｒ3 は異なっていてよい。） Ｏ：酸素原子 Ｒ4 ：アルキル基 ｌ、ｍ、ｎ：０≦ｌ＋ｍ＋ｎ≦３を満たす０〜３の整数R 1 l R 2 m R 3 n Si (OR 4 ) 4-lmn ... (1) R 1 , R 2 , R 3 : H or CH 3 group (R 1 , R 2 , R 3 May be different from each other.) O: oxygen atom R 4 : alkyl group 1, m, n: integer of 0 to 3 satisfying 0 ≦ l + m + n ≦ 3
【００２１】このようなアルコキシシランは、加水分解
縮重合できるものであれば良く、特に限定されることは
ないが、例えば、テトラアルコキシシラン、トリアルコ
キシシラン、ジアルコキシシラン、メチルトリアルコキ
シシラン、ジメチルアルコキシシラン、メチルジアルコ
キシシランなどを用いて良い。[0021] Such an alkoxysilane is not particularly limited as long as it can be hydrolyzed and polycondensed, and examples thereof include tetraalkoxysilane, trialkoxysilane, dialkoxysilane, methyltrialkoxysilane and dimethyl. Alkoxysilane, methyldialkoxysilane, etc. may be used.
【００２２】第１の絶縁膜並びに第２の絶縁膜を成膜す
るには、全て塗布法を適用することが本発明の特徴的な
ところであり、その場合、スピン・コート法を適用する
ことが好ましく、その際の希釈溶剤としてはシロキサン
樹脂を溶解できれば特に限定されることはないが、例え
ば、シクロヘキサン、メチルイソブチルケトン、メチル
エチルケトン、メチルセロソルブ、エチルセロソルブ、
オクタン、デカン、プロピレングリコール、プロピレン
グリコールモノメチルエーテル、プロピレングリコール
モノメチルエーテルアセテート、プロピレングリコール
モノプロピルエーテルなどを用いて良い。It is a feature of the present invention that the coating method is applied to form the first insulating film and the second insulating film, and in that case, the spin coating method is applied. Preferably, the diluent solvent at that time is not particularly limited as long as it can dissolve the siloxane resin, but for example, cyclohexane, methyl isobutyl ketone, methyl ethyl ketone, methyl cellosolve, ethyl cellosolve,
Octane, decane, propylene glycol, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, propylene glycol monopropyl ether, etc. may be used.
【００２３】絶縁膜を多孔質化して低密度絶縁膜とする
には、絶縁膜形成組成物中に所定量の脱離剤樹脂を添加
しておけば良く、例えば、ノボラック系樹脂、エポキシ
系樹脂、アクリル系樹脂、ポリエステル系樹脂、ポリプ
ロピレン系樹脂、フェノール化合物、脂環式化合物、或
いは、これ等の化合物の高分子量体を用いることができ
る。In order to make the insulating film porous to form a low-density insulating film, it is sufficient to add a predetermined amount of the releasing agent resin to the insulating film forming composition. For example, novolac resin or epoxy resin. Acrylic resins, polyester resins, polypropylene resins, phenol compounds, alicyclic compounds, or high molecular weight compounds of these compounds can be used.
【００２４】脱離剤樹脂の添加量は、低密度絶縁膜が所
要の密度になるように選択すれば良く、０．５〜１．２
〔ｇ／ｃｍ3 〕程度が好ましい。この場合、０．５〔ｇ
／ｃｍ3 〕未満では膜の機械的特性が低く、１．２〔ｇ
／ｃｍ3 〕を越えると低誘電率化の効果が小さいだけで
なく、高密度絶縁膜との密度差が小さい為、エッチング
・レートが低下し、加工が困難になる。The amount of the releasing agent resin added may be selected so that the low density insulating film has a required density, and is 0.5 to 1.2.
It is preferably about [g / cm 3 ]. In this case, 0.5 [g
/ Cm 3 ], the mechanical properties of the film are low, and 1.2 [g
/ Cm 3 ], not only the effect of lowering the dielectric constant is small, but also the density difference from the high-density insulating film is small, so that the etching rate is lowered and processing becomes difficult.
【００２５】前記理由から、高密度絶縁膜の形成組成物
には、できるだけ脱離剤樹脂は添加しない方が好まし
く、添加した場合であっても、成膜後の絶縁膜の密度が
１．４〜２．０〔ｇ／ｃｍ3 〕であれば加工性及び保護
性に問題は生じない。For the above reasons, it is preferable that the releasing agent resin is not added to the composition for forming the high-density insulating film as much as possible, and even if it is added, the density of the insulating film after film formation is 1.4. If it is 2.0 to 2.0 [g / cm 3 ], there will be no problem in workability and protection.
【００２６】低誘電率絶縁膜形成組成物を用いる多層構
造体を形成する場合のプロセスとしては、当該組成物を
スピン・コート法を適用して基板上に塗布し、１５０
〔℃〕〜３００〔℃〕の温度でプリベークし、溶剤乾燥
とバインダのゲル化を行い、また、低密度膜を形成する
には、加熱に依って脱離剤の脱離処理、或いは、紫外線
照射に依る脱離処理を行い、多層構造体にした後、３０
０〔℃〕以上の熱処理を加え、シロキサン樹脂を焼成す
ればよい。As a process for forming a multi-layered structure using the low dielectric constant insulating film forming composition, the composition is applied onto a substrate by applying a spin coating method,
Prebaking is performed at a temperature of [° C] to 300 [° C], solvent drying and gelation of the binder are performed, and in order to form a low density film, desorption treatment of the desorbing agent by heating or ultraviolet rays is performed. After desorption treatment by irradiation to form a multilayer structure, 30
The siloxane resin may be baked by applying heat treatment at 0 [° C.] or higher.
【００２７】実施例１
（１）４１．６〔ｇ〕（０．２〔ｍｏｌ〕）のトリエト
キシシラン、３９．６〔ｇ〕のメチルイソブチルケトン
を２００〔ｍｌ〕の反応容器中に仕込んで、１６．２
〔ｇ〕（０．９〔ｍｏｌ〕）の４００〔ｐｐｍ〕硝酸水
を１０〔分〕かけて滴下し、滴下終了後に２〔時間〕の
熟成反応を行う。Example 1 (1) 41.6 [g] (0.2 [mol]) of triethoxysilane and 39.6 [g] of methyl isobutyl ketone were charged into a 200 [ml] reaction vessel. , 16.2
[G] (0.9 [mol]) 400 [ppm] nitric acid water is added dropwise over 10 [minutes], and an aging reaction is performed for 2 [hours] after the completion of the addition.
【００２８】（２）次いで、５〔ｇ〕の硫酸マグネシウ
ムを添加して過剰の水分を除去した後、ロータリ・エバ
ポレータを用いて、副生成物のエタノールを含む溶媒を
反応溶液が５０〔ｍｌ〕になるまで除去し、得られた反
応溶液を高密度絶縁膜形成用塗布液とする。(2) Next, 5 [g] of magnesium sulfate was added to remove excess water, and the solvent containing the by-product ethanol was added to the reaction solution in an amount of 50 [ml] using a rotary evaporator. The resulting reaction solution is used as a coating liquid for forming a high-density insulating film.
【００２９】（３）次いで、高密度絶縁膜形成用塗布液
に１．２５〔ｇ〕のアダマンタンモノフェノールを添加
して、多孔質の低密度膜である第１の絶縁膜形成用塗布
液とする。(3) Next, 1.25 [g] of adamantane monophenol was added to the high density insulating film forming coating solution to obtain a first insulating film forming coating solution which was a porous low density film. To do.
【００３０】（４）次いで、スピン・コート法を適用す
ることに依り、低密度絶縁膜形成用塗布液をシリコン基
板上に塗布する。(4) Next, a low-density insulating film forming coating solution is applied onto the silicon substrate by applying a spin coating method.
【００３１】（５）次いで、ホット・プレートを用い、
３００〔℃〕、３〔分〕間のプリベークを行ってから、
窒素雰囲気中で４００〔℃〕、３０〔分〕間の焼成を行
って、膜厚約２０００〔Å〕の多孔質化された低密度絶
縁膜を形成する。(5) Next, using a hot plate,
After prebaking for 300 [° C] and 3 [min],
Firing is performed for 400 [° C.] and 30 [min] in a nitrogen atmosphere to form a porous low-density insulating film having a film thickness of about 2000 [Å].
【００３２】（６）次いで、低密度絶縁膜上に厚さ１
〔ｍｍ〕の金電極を形成し、容量・電圧特性から誘電率
を産出したところ、低密度絶縁膜に於ける誘電率は２．
２５、密度は１．０８〔ｇ／ｃｍ3 〕であった。(6) Next, a thickness of 1 is formed on the low-density insulating film.
When a gold electrode of [mm] was formed and the dielectric constant was produced from the capacity / voltage characteristics, the dielectric constant of the low density insulating film was 2.
The density was 25 and the density was 1.08 [g / cm 3 ].
【００３３】前記低密度絶縁膜と同様な工程を経て形成
した高密度絶縁膜に於ける誘電率は３．１８、密度は
１．４３〔ｇ／ｃｍ3 〕であり、また、この場合に於け
る標準的なＳｉＯ2 エッチング条件に於ける低密度絶縁
膜及び高密度絶縁膜に於けるエッチング・レートは約
２．３であった。The high-density insulating film formed through the same steps as the low-density insulating film has a dielectric constant of 3.18 and a density of 1.43 [g / cm 3 ], and in this case. The etching rate of the low density insulating film and the high density insulating film under the standard SiO 2 etching conditions was about 2.3.
【００３４】実施例２
図１は本発明に於ける実施例２を説明する為の工程要所
に於ける半導体装置を表す要部切断側面図であり、以
下、図を参照しつつ説明する。Embodiment 2 FIG. 1 is a fragmentary side view showing a semiconductor device in a process step for explaining Embodiment 2 of the present invention, which will be described below with reference to the drawings.
【００３５】図１（Ａ）参照
（１）スピン・コート法を適用することに依り、半導体
基板１上に低密度絶縁膜形成用塗布液を塗布して厚さ２
００〔ｎｍ〕の低密度絶縁膜２を形成してから温度３０
０〔℃〕でプリベークを行い、次に、同じ方法を適用す
ることに依り、低密度絶縁膜２上に高密度絶縁膜形成用
塗布液を塗布して厚さ１５０〔ｎｍ〕の高密度絶縁膜３
を形成してから全体を窒素雰囲気中で温度４００〔℃〕
で時間を３０〔分〕間として焼成を行った。尚、低密度
絶縁膜形成用塗布液及び高密度絶縁膜形成用塗布液は実
施例１に於いて作製したものを用いた。See FIG. 1A. (1) By applying the spin coating method, a coating liquid for forming a low density insulating film is applied on the semiconductor substrate 1 to have a thickness of 2
After forming the low-density insulating film 2 of 00 [nm], the temperature is set to 30
Prebaking is performed at 0 [° C.], and then the same method is applied to apply a high-density insulating film forming coating solution on the low-density insulating film 2 to form a high-density insulating film having a thickness of 150 [nm]. Membrane 3
After forming, the whole was heated to 400 [° C] in a nitrogen atmosphere.
The firing was carried out at a time of 30 [minutes]. The low density insulating film forming coating liquid and the high density insulating film forming coating liquid used in Example 1 were used.
【００３６】（２）リソグラフィ技術に於けるレジスト
・プロセスを適用することに依り、第１層目配線溝形成
予定部分に開口をもつレジスト膜（図示せず）を形成す
る。(2) By applying a resist process in the lithography technique, a resist film (not shown) having an opening is formed in a portion where the first layer wiring groove is to be formed.
【００３７】（３）エッチング・ガスをＣＦ4 ／ＣＨＦ
3 ガスとするＲＩＥ（ｒｅａｃｔｉｖｅｉｏｎ ｅｔｃ
ｈｉｎｇ）法を適用することに依り、前記工程（２）で
形成したレジスト膜をマスクとして高密度絶縁膜３及び
低密度絶縁膜２のエッチングを行って第１層目配線溝を
形成する。(3) Etching gas is CF 4 / CHF
RIE (reactive ion ec) using 3 gases
Hing) method is used to etch the high density insulating film 3 and the low density insulating film 2 using the resist film formed in the step (2) as a mask to form a first-layer wiring groove.
【００３８】（４）スパッタリング法を適用することに
依り、下側に厚さ５０〔ｎｍ〕のＴａＮ層と上側に厚さ
５０〔ｎｍ〕のＣｕ層とを積層したシード層４を形成す
る。(4) By applying the sputtering method, the seed layer 4 is formed by laminating a TaN layer having a thickness of 50 [nm] on the lower side and a Cu layer having a thickness of 50 [nm] on the upper side.
【００３９】（５）電解めっき法を適用することに依
り、シード層４上に厚さ６００〔ｎｍ〕のＣｕ層を形成
する。(5) A Cu layer having a thickness of 600 nm is formed on the seed layer 4 by applying the electroplating method.
【００４０】（６）ＣＭＰ（ｃｈｅｍｉｃａｌ ｍｅｃ
ｈａｎｉｃａｌ ｐｏｌｉｓｈｉｎｇ）法を適用するこ
とに依り、工程（５）及び（４）で形成したＣｕ層及び
シード層４を研磨して第１層目配線５を形成する。(6) CMP (chemical mec)
The Cu layer and the seed layer 4 formed in the steps (5) and (4) are polished to form the first-layer wiring 5 by applying the thermal polishing method.
【００４１】（７）これ以後は、デュアル・ダマシン法
を適用してビアと配線とを同時に形成する工程の説明で
ある。ＣＶＤ（ｃｈｅｍｉｃａｌ ｖａｐｏｕｒ ｄｅ
ｐｏｓｉｔｉｏｎ）法を適用することに依り、全面に厚
さ５０〔ｎｍ〕のＳｉＮからなるＣｕ拡散防止膜６を形
成する。(7) Hereafter, the description will be given of the step of simultaneously forming the via and the wiring by applying the dual damascene method. CVD (chemical vapor de
The Cu diffusion preventing film 6 made of SiN and having a thickness of 50 nm is formed on the entire surface by applying the position method.
【００４２】（８）スピン・コート法を適用することに
依り、Ｃｕ拡散防止膜６上に低密度絶縁膜形成用塗布液
を塗布して厚さ３００〔ｎｍ〕の低密度絶縁膜７を形成
してから温度３００〔℃〕でプリベークを行い、次に、
同じくスピン・コート法を適用することに依り、低密度
絶縁膜７上に高密度絶縁膜形成用塗布液を塗布して厚さ
１００〔ｎｍ〕の高密度絶縁膜８を形成してから温度３
００〔℃〕でプリベークを行い、次に、同じくスピン・
コート法を適用することに依り、高密度絶縁膜８上に厚
さ２００〔ｎｍ〕の低密度絶縁膜９を形成してから温度
３００〔℃〕でプリベークを行い、次に、同じくスピン
・コート法を適用することに依り、低密度絶縁膜９上に
厚さ１５０〔ｎｍ〕の高密度絶縁膜１０を形成してから
全体を窒素雰囲気中にて温度４００〔℃〕で時間を３０
〔分〕間として焼成を行った。(8) By applying the spin coating method, a coating solution for forming a low density insulating film is applied on the Cu diffusion preventing film 6 to form a low density insulating film 7 having a thickness of 300 nm. After that, prebaking is performed at a temperature of 300 [° C], and then
Similarly, by applying the spin coating method, the high-density insulating film forming coating liquid is applied on the low-density insulating film 7 to form the high-density insulating film 8 having a thickness of 100 nm, and then the temperature 3
Pre-bake at 00 [° C], then spin again
By applying the coating method, a low-density insulating film 9 having a thickness of 200 [nm] is formed on the high-density insulating film 8, prebaking is performed at a temperature of 300 [° C.], and then spin coating is also performed. By applying the method, a high density insulating film 10 having a thickness of 150 nm is formed on the low density insulating film 9 and then the whole is placed in a nitrogen atmosphere at a temperature of 400 ° C. for 30 hours.
Firing was performed for [minutes].
【００４３】図１（Ｂ）参照
（９）リソグラフィ技術に於けるレジスト・プロセスを
適用することに依り、ビア形成予定部分に開口をもつレ
ジスト膜（図示せず）を形成する。Referring to FIG. 1B (9), by applying a resist process in the lithography technique, a resist film (not shown) having an opening at a portion where a via is to be formed is formed.
【００４４】（１０）エッチング・ガスをＣＦ4 ／ＣＨ
Ｆ3 ガスとするＲＩＥ法を適用することに依り、高密度
絶縁膜１０、低密度絶縁膜９、高密度絶縁膜８、低密度
絶縁膜７のエッチングを行ってビア・ホール７Ａを形成
する。(10) Etching gas is CF 4 / CH
By applying the RIE method using F 3 gas, the high density insulating film 10, the low density insulating film 9, the high density insulating film 8 and the low density insulating film 7 are etched to form the via holes 7A.
【００４５】（１１）リソグラフィ技術に於けるレジス
ト・プロセスを適用することに依り、第２層目配線溝形
成予定部分に開口をもつレジスト膜（図示せず）を形成
する。(11) By applying a resist process in the lithography technique, a resist film (not shown) having an opening is formed in the portion where the second layer wiring groove is to be formed.
【００４６】（１２）エッチング・ガスをＣＦ4 ／ＣＨ
Ｆ3 ガスとするＲＩＥ法を適用することに依り、高密度
絶縁膜１０、低密度絶縁膜９のエッチングを行って第２
層目配線溝９Ａ及び９Ｂを形成する。尚、第２層目配線
溝９Ａ及び９Ｂのエッチングは高密度絶縁膜８中に於い
て制御性良く停止させることができ、また、第２層目配
線溝９Ａ及び９Ｂの底に於ける平滑性は極めて良好であ
る。(12) Etching gas is CF 4 / CH
By applying the RIE method using F 3 gas, the high density insulating film 10 and the low density insulating film 9 are etched to obtain the second
Layer wiring trenches 9A and 9B are formed. The etching of the second-layer wiring trenches 9A and 9B can be stopped in the high-density insulating film 8 with good controllability, and the smoothness at the bottom of the second-layer wiring trenches 9A and 9B can be improved. Is very good.
【００４７】（１３）ドライ・エッチング法を適用する
ことに依り、ビア・ホール７Ａの底に表出されているＳ
ｉＮからなるＣｕ拡散防止膜６をエッチングして除去し
て第１層目配線５の一部を表出させる。(13) S exposed at the bottom of the via hole 7A by applying the dry etching method.
The Cu diffusion prevention film 6 made of iN is removed by etching to expose a part of the first-layer wiring 5.
【００４８】（１４）スパッタリング法を適用すること
に依り、下側に厚さ５０〔ｎｍ〕のＴａＮ層と上側に厚
さ５０〔ｎｍ〕のＣｕ層とを積層したシード層１１を形
成する。(14) By applying the sputtering method, the seed layer 11 is formed by laminating a TaN layer having a thickness of 50 nm on the lower side and a Cu layer having a thickness of 50 nm on the upper side.
【００４９】（１５）電解めっき法を適用することに依
り、シード層１１上に厚さが１２００〔ｎｍ〕のＣｕ層
を形成する。(15) A Cu layer having a thickness of 1200 nm is formed on the seed layer 11 by applying the electrolytic plating method.
【００５０】（１６）ＣＭＰ法を適用することに依り、
工程（１５）及び（１４）で形成したＣｕ層及びシード
層１１を研磨してビア１２、第２層目配線１３及び１４
を形成する。以下、前記工程を適宜に繰り返すことで、
更に多層化することができる。(16) By applying the CMP method,
The Cu layer and the seed layer 11 formed in the steps (15) and (14) are polished to polish the via 12, the second layer wirings 13 and 14.
To form. Hereinafter, by appropriately repeating the above steps,
Further, it can be multilayered.
【００５１】[0051]
【発明の効果】本発明に依る半導体装置の製造方法に於
いては、半導体基板上に低密度絶縁膜となる低密度絶縁
膜材料を塗布してからプリベークを行い、次いで、低密
度絶縁膜上に高密度絶縁膜となる高密度絶縁膜材料を塗
布してからプリベークを行って積層膜とする工程と、そ
の後、積層膜を一括してキュアすることで多層構造体と
することが基本になっている。In the method of manufacturing a semiconductor device according to the present invention, a low density insulating film material to be a low density insulating film is applied on a semiconductor substrate, prebaking is performed, and then the low density insulating film is formed. The basic procedure is to apply a high-density insulating film material that will become a high-density insulating film on the substrate, then pre-bake it to form a laminated film, and then cure the laminated film collectively to form a multilayer structure. ing.
【００５２】前記構成を採ることに依り、気相成長膜を
用いる必要はなくなり、低密度絶縁膜も高密度絶縁膜も
全て同一成膜装置内で塗布法を適用して積層形成するこ
とができ、長い処理時間を必要とするキュアも一括で行
うから、短時間且つ低コストで多層配線を実現する為の
多層構造体を形成することができ、しかも、キュア時に
積層膜が相互に架橋する為、層間の密着強度も向上す
る。また、多層構造体をデュアル・ダマシン加工する場
合に於いて、上層に配線溝を形成する際、下層の表面側
に在る高密度絶縁膜をエッチング停止層として作用させ
ることができ、従って、配線溝底のラフネスを低減する
ことが可能になり、その結果、バリア・メタルの被覆性
は良好に維持される。更にまた、上層の表面側に在る絶
縁膜は高密度であるから、高硬度で且つ高薬品耐性をも
ち、従って、ＣＭＰ法を適用してメタル除去を行う際に
損傷され易い低密度絶縁膜の保護膜としての役割を果た
すことができる。By adopting the above structure, it is not necessary to use a vapor phase growth film, and both the low density insulating film and the high density insulating film can be laminated by applying the coating method in the same film forming apparatus. Since the curing that requires a long processing time is also performed collectively, it is possible to form a multilayer structure for realizing multilayer wiring in a short time and at low cost, and moreover, because the laminated films cross-link each other during curing. The adhesion strength between layers is also improved. Further, in the case of dual damascene processing of the multilayer structure, when forming the wiring groove in the upper layer, the high-density insulating film on the surface side of the lower layer can be made to act as an etching stop layer. It is possible to reduce the roughness of the groove bottom, and as a result, good coverage of the barrier metal is maintained. Furthermore, since the insulating film on the surface side of the upper layer has a high density, it has a high hardness and a high chemical resistance, and therefore a low density insulating film which is easily damaged when the metal is removed by applying the CMP method. Can play the role of a protective film.
【図１】本発明に於ける実施例２を説明する為の工程要
所に於ける半導体装置を表す要部切断側面図である。FIG. 1 is a fragmentary side view showing a semiconductor device in a process essential part for explaining a second embodiment of the present invention.
１ 半導体基板 ２ 低密度絶縁膜 ３ 高密度絶縁膜 ４ シード層 ５ 第１層目配線 ６ Ｃｕ拡散防止膜 ７ 低密度絶縁膜 ７Ａ ビア・ホール ８ 高密度絶縁膜 ９ 低密度絶縁膜 ９Ａ及び９Ｂ 第２層目配線溝 １０ 高密度絶縁膜 １１ シード層 １２ ビア １３及び１４ 第２層目配線 1 Semiconductor substrate 2 Low density insulating film 3 High-density insulating film 4 Seed layer 5 First layer wiring 6 Cu diffusion prevention film 7 Low density insulating film 7A Beer Hall 8 High-density insulating film 9 Low density insulating film 9A and 9B Second layer wiring groove 10 High-density insulating film 11 Seed layer 12 vias 13 and 14 Second layer wiring
───────────────────────────────────────────────────── フロントページの続き (72)発明者 矢野 映 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 5F033 HH11 HH32 JJ11 JJ32 KK11 KK32 MM01 MM12 MM13 NN06 NN07 QQ09 QQ13 QQ37 QQ48 RR06 RR29 SS22 TT04 XX24 5F058 AA10 AC10 AD05 AF04 AG01 AH02 BA20 BD01 BD07 BF46 BH01 BJ02 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor, Ei Yano 4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 within Fujitsu Limited F term (reference) 5F033 HH11 HH32 JJ11 JJ32 KK11 KK32 MM01 MM12 MM13 NN06 NN07 QQ09 QQ13 QQ37 QQ48 RR06 RR29 SS22 TT04 XX24 5F058 AA10 AC10 AD05 AF04 AG01 AH02 BA20 BD01 BD07 BF46 BH01 BJ02
Claims (3)
絶縁膜材料を塗布してからプリベークを行い、次いで、
低密度絶縁膜上に高密度絶縁膜となる高密度絶縁膜材料
を塗布してからプリベークを行って積層膜とする工程
と、 その後、積層膜を一括してキュアすることで多層構造体
とする工程とが含まれてなることを特徴とする半導体装
置の製造方法。1. A low-density insulating film material for forming a low-density insulating film is applied on a semiconductor substrate, prebaking is performed, and then,
A process of applying a high-density insulating film material to be a high-density insulating film on a low-density insulating film and then performing pre-baking to form a laminated film, and then curing the laminated film collectively to form a multilayer structure. And a step of manufacturing the semiconductor device.
式（１）で表されるアルコキシシランの部分加水分解縮
合物からなる塗布型低誘電率絶縁膜形成組成物を用いて
形成されるものであることを特徴とする請求項１記載の
半導体装置の製造方法。 Ｒ1 l Ｒ2 m Ｒ3 n Ｓｉ（ＯＲ4 ）4-l-m-n ・・・・（１） Ｒ1 、Ｒ2 、Ｒ3 ：Ｈ或いはＣＨ3 基 （Ｒ1 、Ｒ2 、Ｒ3 は異なっていてよい。） Ｏ：酸素原子 Ｒ4 ：アルキル基 ｌ、ｍ、ｎ：０≦ｌ＋ｍ＋ｎ≦３を満たす０〜３の整数2. A low density insulating film and a high density insulating film are formed using a coating type low dielectric constant insulating film forming composition comprising a partial hydrolysis-condensation product of an alkoxysilane represented by the following general formula (1). The method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device. R 1 l R 2 m R 3 n Si (OR 4 ) 4-lmn ... (1) R 1 , R 2 , R 3 : H or CH 3 group (R 1 , R 2 and R 3 are different O: oxygen atom R 4 : alkyl group 1, m, n: an integer of 0 to 3 satisfying 0 ≦ l + m + n ≦ 3.
２〔ｇ／ｃｍ3 〕及び高密度絶縁膜に於ける密度が１．
４〜２．０〔ｇ／ｃｍ3 〕の範囲にあることを特徴とす
る請求項１記載の半導体装置の製造方法。3. The low density insulating film has a density of 0.5 to 1.
2 [g / cm 3 ] and the density in the high density insulating film is 1.
4. The method for manufacturing a semiconductor device according to claim 1, which is in the range of 4 to 2.0 [g / cm 3 ].
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006131863A (en) * | 2004-10-07 | 2006-05-25 | Sumitomo Chemical Co Ltd | Polymer of silane compound, composition for formation of adhesion layer, method for producing adhesion layer, adhesion layer and method for producing substrate having insulating film |
| US8106385B2 (en) | 2004-06-21 | 2012-01-31 | Hitachi Chemical Co., Ltd. | Organic siloxane film, semiconductor device using the same, flat panel display device, and raw material liquid |
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2002
- 2002-02-20 JP JP2002043242A patent/JP3981870B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8106385B2 (en) | 2004-06-21 | 2012-01-31 | Hitachi Chemical Co., Ltd. | Organic siloxane film, semiconductor device using the same, flat panel display device, and raw material liquid |
| JP2006131863A (en) * | 2004-10-07 | 2006-05-25 | Sumitomo Chemical Co Ltd | Polymer of silane compound, composition for formation of adhesion layer, method for producing adhesion layer, adhesion layer and method for producing substrate having insulating film |
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| JP3981870B2 (en) | 2007-09-26 |
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