JP2003241979A - Interruption mask control method and interruption mask control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a level control of mask (or independent control of mask) coexistent with the independent control (or level control) in an interruption mask control method and interruption mask control program for loading a plurality of OS in the same space to control an interruption mask by calculating and setting the logic sum of a mask pattern with interruption occurrence with a mask pattern just before interruption to perform an interruption processing, and reflecting the mask pattern with interruption occurrence at the end of interruption. <P>SOLUTION: This method has a step for reading, in the occurrence of an interruption from a certain OS, a mask pattern corresponding to a designated interruption level or generating a mask pattern in which a designated interruption number is permitted or prohibited, and setting a mask pattern logically added to the present mask pattern to execute the interruption processing; and a step for reflecting the read or generated mask pattern to the present mask pattern to update the present mask pattern. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt mask control method and an interrupt mask control program for loading a plurality of OSs in the same space to control an interrupt mask.

[0002]

2. Description of the Related Art Conventionally, a host OS (for example, real-time OS) and a guest OS (for example, UN having high functions)
IX (registered trademark) or the like is loaded in the same space to perform business processing, so-called hybrid OS has come into use.

[0003]

However, when the above-mentioned host OS sets a mask corresponding to an interrupt level pattern and another guest OS sets a mask individually, one interrupt is interrupted by the other interrupt. There was a problem of permitting / prohibiting the mask and causing it to collapse.

The present invention solves these problems.
Calculates and sets the logical sum of the interrupt-generated mask pattern and the mask pattern immediately before the interrupt, executes the interrupt process, reflects the interrupt-generated mask pattern at the end of the interrupt, and controls the mask level ( Alternatively, the objective is to make the individual control of the mask coexist with the individual control (or level control) without collapsing.

[0005]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG.

In FIG. 1, the guest OS 4 is a host O.
The task 5 is operated by loading it in the same space as S6, and provides the host OS 6 with various functions by the task 5. Here, the mask is individually controlled.

The host OS 6 is loaded in the same space as the guest OS 4 and executes the task 7 to provide various functions (services). Here, the mask level is controlled. The same host OS 6 or guest OS 4 as the individual mask control of the guest OS 4 or the mask level control of the host OS 6 may be provided.

Next, the operation will be described. When an interrupt occurs, a certain OS takes out a mask pattern corresponding to a specified interrupt level, or generates a mask pattern in which a specified interrupt number is permitted or prohibited, and is logically ORed with the current mask pattern. The mask pattern is set to execute the interrupt process, and at the end of the interrupt process, the extracted or generated mask pattern is reflected in the current mask pattern and updated as the current mask pattern.

At this time, as control of interrupts of a plurality of OSs,
Either the mask level control is performed as in the host OS 6 or the individual mask control is performed as in the guest OS 4.

Therefore, the logical sum of the mask pattern of the interrupt occurrence and the mask pattern immediately before the interrupt is calculated and set,
By performing interrupt processing and reflecting the mask pattern of interrupt generation at the end of interrupt, it is possible to coexist with individual control (or level control) without breaking mask level control (or individual mask control). It will be possible.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments and operations of the present invention will be sequentially described in detail with reference to FIGS.

FIG. 1 shows a system configuration diagram of the present invention.
In FIG. 1, the interrupt controller unit 1 takes in an external interrupt and notifies the MPU unit 2 of the like. The external interrupt and a mask bit for masking the interrupt signal from the external interrupt. 11 and the like.

The mask bit 11 is a bit for masking an interrupt signal from each external interrupt (a bit corresponding to a mask pattern).

The MPU unit 2 performs various processes in accordance with the program read from the memory unit 3. Here, the interrupt from the interrupt controller unit 1 is notified to the guest OS 4 and the host OS 6, and is notified. The mask bits (bits corresponding to the mask pattern) are notified to the interrupt controller unit 1 and set.

The memory unit 3 is a storage device for loading and activating a program and performing the various processes shown in the figure. Here, as shown in the figure, the guest OS 4,
It stores a program that operates as the task 5, the host OS 6, the task 7, and the like.

The guest OS 4 is arranged in the same space as the host OS 6, and here, the host OS 6 is made to use various functions (functions executed by the task 5), and individual control of masks and interrupts are performed. It is composed of means 41 and the like.

The interrupting means 41 controls various interrupts in the guest OS 4. Task 5 is guest O
Under the control of S4, various functions (such as an advanced filing function) are executed.

The host OS 6 is arranged in the same space as the guest OS 4 and uses various functions of the guest OS 4, and here, the level control of the mask, the pattern table 61, the interrupt means 62, the interrupt means 62, Inlet means 6
3, the interrupt outlet means 64 and the like.

The pattern table 61 is a table in which mask patterns (mask bits) are preset in association with levels (see FIG. 4B).

The interrupt means 62 controls various interrupts in the host OS 6. The interrupt entrance means 63 is
Various processes are performed at the entrance of the interrupt. Here, as shown in FIG. 2, which will be described later, the current mask pattern is saved, the mask pattern corresponding to the current mask level is taken out from the pattern table, OR the mask pattern with the extracted mask pattern,
The mask pattern obtained by the logical sum is set as a mask pattern to be used.

The interrupt exit means 64 performs various processes at the exit of the interrupt, and here, as shown in FIG. 3 described later, the extracted or generated mask pattern is reflected in the saved mask pattern. Then, the current mask pattern is updated and set.

The task 7 provides various functions (for example, real-time function) under the control of the host OS 6.

Next, the operation of the configuration of FIG. 1 will be described in detail according to the order of the flowchart of FIG.

FIG. 2 is a flowchart (No. 1) for explaining the operation of the present invention. Here, guest OS 4 and host OS
6 is the same as that of the same number in FIG.

In FIG. 2, at S1, control is transferred to the host OS when an interrupt occurs. This transfers control from the guest OS 4 that received the interrupt notification to the host OS 6.

S2 is the host OS whose control has been transferred in S1.
At 6, the host OS 6 (interrupt entrance unit 63) saves the current mask pattern.

In step S3, the mask pattern of the corresponding level is acquired. This acquires the mask pattern corresponding to the current or designated mask level from the pattern table of FIG. 4B described later.

In step S4, a logical sum of the current mask pattern and the mask pattern of the acquired level is calculated to set a new mask pattern.

In step S5, the processor interrupt is changed to the enable state. At S6, interrupt processing is performed. For example, as shown in the figure, if it is a timer interrupt, processing such as counting up the system time is performed.

At step S7, an interrupt exit process is performed. For example,
As shown in the figure, task scheduling of the host OS 6 and restoration processing of registers saved for interrupt recovery are performed.

As described above, if an external interrupt occurs while the guest OS 4 is executing processing, control is transferred to the host OS 6 here, and the host OS 6 saves the current mask pattern,
The mask pattern of the corresponding level is acquired from the pattern table of FIG. 4B, the two are logically ORed and set, and then the interrupt process is performed. Even if an interrupt occurs, it is possible to coexist with the mask level control of the host OS 6 without destroying the individual mask control (or mask level control) of the guest OS 4.

FIG. 3 shows a flowchart (part 2) for explaining the operation of the present invention. In FIG. 3, S11 is a host O
S6 calls the interrupt handler. This is the host OS6
Interrupt processing (interruption means 62) of guest O who received the interrupt
Call the S4 interrupt handler.

In step S12, the interrupt handler of the guest OS 4 called in step S11 sends a mask operation request to the host OS.
Notify the mask processing of No. 6.

In S13, the host O notified in S12
The mask process of S6 performs a mask operation. Then, the completion notification is sent to the interrupt handler of the guest OS 4, and the interrupt processing is requested to the interrupt processing of the host OS in S14.

In step S15, the interrupt processing exit is used to perform task scheduling of the host OS. Step S16 is an interrupt processing exit, which reflects the mask operation operated by the guest OS when the mask is restored. This reflects the contents of the mask operation in S13 described above at the exit of the interrupt processing and sets the current mask pattern. As a result, the contents reflected in the mask pattern in response to the interrupt in S13 are also reflected in the current mask pattern and updated to the new current mask pattern.

In S17, the guest OS 4 is interrupted and returned.
As described above, when an interrupt is generated in the guest OS 4, the mask pattern generated on the host OS 4 side is reflected (logical sum) in the current mask pattern and set, the interrupt process is performed, and the interrupt process ends. By setting a new mask pattern that reflects the mask pattern of this interrupt in the interrupt exit processing at the time, the mask level control (or mask level control) can be performed without breaking individual mask control (or mask level control). Individual control) can be made to coexist.

FIG. 4 shows an interrupt explanatory diagram of the present invention. Figure 4
(A) shows an example of interruption. Here, for example, an interrupt is set as shown below.

Interrupt number External interrupt name 1 Timer 2 HDD 3 Keyboard 4 LAN Here, the interrupt number is for simplifying the description when the interrupt controller unit 1 of FIG. 1 has four external interrupts. Used for.

FIG. 4B shows an example of the pattern table. This shows an example of a mask pattern in which the interrupt number is set to the interrupt permission or the interrupt prohibition corresponding to the level in association with the interrupt number of FIG.
The level is set from 0 to 4 here, and the smaller the number, the higher the interrupt level. In the case of the mask pattern shown in the figure, the interrupt priority is 4, from the left, as shown in the figure.
2, 1, 3 (the higher the number, the higher the priority).

As described above, in association with the interrupt level,
By setting the mask pattern for which external interrupt numbers are permitted or prohibited, as shown in the pattern table in advance, only by specifying the level, the corresponding mask patterns are permitted to interrupt numbers. Alternatively, it is possible to control the prohibition of interrupts (called mask level control). Note that the individual mask control is a control in which an interrupt number is specified, and a mask pattern in which the specified interrupt number is set to enable or disable an interrupt is generated, and it is already described in the interrupt entrance process. It may be logically ORed or reflected in the interrupt exit process.

(Supplementary Note 1) In an interrupt mask control method of loading a plurality of OSs in the same space to control an interrupt mask, when an interrupt occurs from a certain OS, a mask pattern corresponding to a specified interrupt level is extracted. , Or a step of generating a mask pattern in which the specified interrupt number is permitted or prohibited, setting a mask pattern after logically summing with the current mask pattern, and executing the interrupt process, and the above interrupt process completion And a step of updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern.

(Supplementary Note 2) The interrupt mask control method according to Supplementary Note 1, wherein the interrupt control of the plurality of OSs is either mask level control or individual mask control.

(Supplementary note 3) In an interrupt mask control program for loading a plurality of OSs in the same space to control an interrupt mask, when an interrupt occurs from a certain OS, a mask pattern corresponding to a specified interrupt level is taken out. , Or a step of generating a mask pattern in which the specified interrupt number is permitted or prohibited, setting a mask pattern after logically summing with the current mask pattern, and executing the interrupt process, and the above interrupt process completion An interrupt mask control program for causing a computer to function as a step of updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern.

(Supplementary Note 4) In an interrupt mask controller for controlling an interrupt mask by loading a plurality of OSs in the same space, when an interrupt occurs from a certain OS, a mask pattern corresponding to a specified interrupt level is taken out. , Or a means for generating a mask pattern in which a specified interrupt number is permitted or prohibited, and setting a mask pattern after logically summing with the current mask pattern to execute an interrupt process,
A mask control device, comprising means for updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern at the end of the interrupt process.

(Supplementary Note 5) A computer-readable recording medium in which an interrupt mask control program for loading a plurality of OSs in the same space to control an interrupt mask is recorded and which is designated by an OS when an interrupt occurs. The mask pattern corresponding to the specified interrupt level is extracted, or a mask pattern in which the specified interrupt number is permitted or prohibited is generated, and the mask pattern after logical OR with the current mask pattern is set and interrupt processing is performed. And a computer readable program recording a program that functions as a step of updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern at the end of the interrupt processing. recoding media.

[0046]

As described above, according to the present invention,
By adopting a configuration that calculates and sets the logical sum of the mask pattern of the interrupt occurrence and the mask pattern immediately before the interrupt, performs the interrupt processing, and reflects the mask pattern of the interrupt occurrence at the end of the interrupt. Therefore, the level control of the mask (or the individual control of the mask) can be made to coexist with the individual control (or the level control) without being destroyed.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of the present invention.

FIG. 2 is a flowchart (No. 1) for explaining the operation of the present invention.

FIG. 3 is a flowchart (No. 2) for explaining the operation of the present invention.

FIG. 4 is an explanatory diagram of interruption of the present invention.

[Explanation of symbols] 1: Interrupt controller unit 2: MPU unit 3: Memory unit 4: Guest OS 41: Interruption means 5, 7: Task 6: Guest OS 61: Pattern table 62: Interruption means 63: Interrupt entrance means 64: Interrupt exit means

Claims (3)

[Claims] 1. An interrupt mask control method for controlling an interrupt mask by loading a plurality of OSs in the same space, and when an interrupt occurs from a certain OS, a mask pattern corresponding to a specified interrupt level is taken out, or Generate a mask pattern that allows or prohibits the specified interrupt number, set the mask pattern after logical OR with the current mask pattern and execute the interrupt process, and at the end of the interrupt process, And a step of updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern. 2. The interrupt mask control method according to claim 1, wherein the interrupt control of the plurality of OSs is either mask level control or mask individual control. 3. An interrupt mask control program for loading a plurality of OSs in the same space to control an interrupt mask, when an interrupt is generated from a certain OS, a mask pattern corresponding to a specified interrupt level is taken out, or Generate a mask pattern that allows or prohibits the specified interrupt number, set the mask pattern after logical OR with the current mask pattern and execute the interrupt process, and at the end of the interrupt process, An interrupt mask control program for causing a computer to function as a step of updating the current mask pattern by reflecting the extracted or generated mask pattern on the current mask pattern.