JP2003234579A - Method of manufacturing multilayer printed wiring board with chip type resistor built therein - Google Patents
Method of manufacturing multilayer printed wiring board with chip type resistor built thereinInfo
- Publication number
- JP2003234579A JP2003234579A JP2002029167A JP2002029167A JP2003234579A JP 2003234579 A JP2003234579 A JP 2003234579A JP 2002029167 A JP2002029167 A JP 2002029167A JP 2002029167 A JP2002029167 A JP 2002029167A JP 2003234579 A JP2003234579 A JP 2003234579A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- type resistor
- insulating layer
- interlayer insulating
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、内層に抵抗体を備
えた多層プリント配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board having a resistor as an inner layer.
【0002】[0002]
【従来の技術】携帯型の情報端末機器においては小型・
高密度化が益々進み、これによりプリント配線板に搭載
される部品点数は増加の一途を辿り、その反面、小型・
薄型化が要求されていることから、部品をプリント配線
板の表面に実装するだけでは、対応できなくなってき
た。2. Description of the Related Art In portable information terminal equipment,
As the density has increased, the number of components mounted on printed wiring boards has continued to increase.
Since it is required to be thin, it is no longer possible to deal with it only by mounting the components on the surface of the printed wiring board.
【0003】このような状況を回避する方法として、多
層プリント配線板の内部に、印刷法、蒸着法等によって
抵抗体を形成するという方法が既に知られている。しか
し、形成された抵抗体は、所定の抵抗値になるようにト
リミング調整が必要であり、大変手間のかかるものであ
った。また、トリミングで初期抵抗値をある程度の範囲
に納めることができたとしても、経時変化により抵抗値
が安定し難いという問題を有していた。As a method of avoiding such a situation, there is already known a method of forming a resistor inside a multilayer printed wiring board by a printing method, a vapor deposition method or the like. However, the formed resistor requires trimming adjustment so as to have a predetermined resistance value, which is very troublesome. Further, even if the initial resistance value can be set within a certain range by trimming, there is a problem that the resistance value is difficult to stabilize due to a change with time.
【0004】従って、安定した抵抗値を有する抵抗体を
形成するためには、製品として規格化されたチップ型抵
抗体を多層プリント配線板の内部に実装する方法が考え
られる。しかし、部品を実装した後、層間絶縁層を部品
とほぼ等しい収納領域を形成して設けた場合、積層の際
に部品に負荷がかかり、部品が割れてしまうという問題
が発生する。Therefore, in order to form a resistor having a stable resistance value, a method of mounting a chip-type resistor standardized as a product inside a multilayer printed wiring board can be considered. However, when the interlayer insulating layer is formed and provided with a storage area that is substantially equal to that of the component after the component is mounted, a load is applied to the component during stacking, which causes a problem that the component is cracked.
【0005】更に、携帯端末機器に使用される多層プリ
ント配線板は、小型でかつ薄型のものが要求され、絶縁
層の厚みは数十μm程度であり、部品の厚みが数百μm
のチップ型抵抗体を多層プリント配線板の内部に埋設す
ることは不可能であった。Further, a multilayer printed wiring board used for portable terminal equipment is required to be small and thin, the thickness of the insulating layer is about several tens of μm, and the thickness of parts is several hundreds of μm.
It was impossible to embed the chip-type resistor in (1) inside the multilayer printed wiring board.
【0006】[0006]
【発明が解決しようとする課題】そこで、本発明者は、
チップ型抵抗体の構造が、その厚さの大部分を占めるセ
ラミックス等の支持体上に抵抗体が形成されていること
に着目し、本発明を完成するに至った。Therefore, the inventor of the present invention
The present invention has been completed by focusing attention on the structure of the chip-type resistor in which the resistor is formed on a support such as ceramics that occupies most of the thickness.
【0007】本発明の目的は、トリミング等による抵抗
値調整を行うことなく、また、経時変化の少ない安定し
た抵抗値を有する抵抗体を内蔵した多層プリント配線板
を提供することにある。An object of the present invention is to provide a multi-layer printed wiring board having a built-in resistor having a stable resistance value with little change over time, without adjusting the resistance value by trimming or the like.
【0008】[0008]
【課題を解決するための手段】本発明は、チップ型抵抗
体を、その支持体を上側に位置せしめると共に、その抵
抗体をランド側にして内層基板に実装する工程と;前記
実装後の内層基板に層間絶縁層を積層する工程と;前記
積層後の積層板を研磨する工程と;前記研磨後の積層板
に絶縁層を介在せしめて導体層を形成する工程とを有す
ることを特徴とするチップ型抵抗体を内蔵した多層プリ
ント配線板の製造方法により上記目的を達成したもので
ある。According to the present invention, a chip-type resistor is mounted on an inner layer substrate with its support positioned on the upper side and the resistor being the land side; and the inner layer after the mounting. A step of laminating an interlayer insulating layer on the substrate; a step of polishing the laminated plate after the laminating; a step of interposing an insulating layer on the laminated plate after the polishing to form a conductor layer. The above object is achieved by a method of manufacturing a multilayer printed wiring board incorporating a chip-type resistor.
【0009】また、本発明は、特に前記層間絶縁層につ
き、チップ型抵抗体が実装された部分を開口せしめ、か
つ層間絶縁層の高さを実装されたチップ型抵抗体よりも
高くすることにより上記目的を達成したものである。斯
かる構成により積層工程でのプレスの圧力が直接チップ
型抵抗体にかからず実装したチップ型抵抗体が割れるこ
とがない。Further, according to the present invention, in particular, regarding the interlayer insulating layer, the portion where the chip type resistor is mounted is opened, and the height of the interlayer insulating layer is made higher than that of the mounted chip type resistor. The above object is achieved. With such a configuration, the pressure of the press in the laminating process does not directly act on the chip resistor, and the mounted chip resistor is not cracked.
【0010】また、本発明は、特に前記層間絶縁層の積
層につき、部品実装部分に開口部の設けられた少なくと
も2枚以上の色調の異なる絶縁層を積層すると共に、当
該層間絶縁層と開口部を覆う絶縁層を更に積層すること
により上記目的を達成したものである。Further, according to the present invention, in particular, regarding the lamination of the interlayer insulating layer, at least two or more insulating layers having different color tones having an opening portion provided in a component mounting portion are laminated, and the interlayer insulating layer and the opening portion are laminated. The above-mentioned object is achieved by further laminating an insulating layer covering the above.
【0011】また、本発明は、特に前記層間絶縁層を積
層後、色調の異なる層間絶縁層の界面まで実装されたチ
ップ型抵抗体も含め研磨し薄くすることにより上記目的
を達成したものである。In addition, the present invention achieves the above object by laminating the above-mentioned interlayer insulating layer and polishing and thinning the chip type resistor mounted even to the interface of the interlayer insulating layers having different color tones. .
【0012】色調の異なる層間絶縁層を積層し、当該色
調の異なる絶縁層の界面まで実装したチップ型抵抗体を
含め厚みが薄くなるまで研磨することによって、プリン
ト配線板のトータルの厚みを薄くすることができ、ま
た、色調の異なる層間絶縁層を使用することで研磨する
厚みが精度よく加工することが可能になる。The total thickness of the printed wiring board is reduced by laminating interlayer insulating layers having different tones and polishing until the thickness including the chip resistor mounted up to the interface of the insulating layers having different tones becomes thin. Further, by using the interlayer insulating layer having different color tones, the polishing thickness can be processed with high accuracy.
【0013】[0013]
【発明の実施の形態】本発明の実施の形態を図1乃至図
2を用いて説明する。図1は、チップ型抵抗体の実装構
造を説明する断面図で、(a)は従来の実装構造を示
し、(b)は本発明における実装構造を示している。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. 1A and 1B are cross-sectional views illustrating a mounting structure of a chip-type resistor, where FIG. 1A shows a conventional mounting structure and FIG. 1B shows a mounting structure according to the present invention.
【0014】チップ型抵抗体4は、セラミックス基材等
からなる支持体15、当該支持体15上に離間して形成
された導体16、当該離間した導体16の間を接続する
ように形成された抵抗体5、当該抵抗体5を保護するた
めの保護層18、側面に形成された側面電極17からな
り、通常は図1(a)のように支持体15を抵抗体5の
下側、すなわちランド側にして、実装ランド2aと側面
電極17とはんだ6で接続し、当該チップ型抵抗体4を
実装していた。The chip resistor 4 is formed so as to connect the support 15 made of a ceramic base material, the conductors 16 formed on the support 15 with a space therebetween, and the conductors 16 separated from each other. It is composed of a resistor 5, a protective layer 18 for protecting the resistor 5, and a side electrode 17 formed on the side surface. Usually, as shown in FIG. On the land side, the mounting land 2a, the side surface electrode 17, and the solder 6 were connected to each other to mount the chip resistor 4.
【0015】本発明は、図1(b)のように、チップ型
抵抗体4を通常の実装構造と逆に、すなわち、支持体1
5を上側に位置せしめると共に、抵抗体5をランド側に
して実装した後、支持体15を研磨して薄くすることに
よって、当該チップ型抵抗体4の薄型化を計ることでよ
りチップ型抵抗体を多層プリント配線板に内蔵し易くし
たものである。According to the present invention, as shown in FIG. 1 (b), the chip resistor 4 is reversely mounted to the usual mounting structure.
5 is positioned on the upper side, the resistor 5 is mounted on the land side, and then the support 15 is polished and thinned to make the chip resistor 4 thinner. Is easily incorporated in a multilayer printed wiring board.
【0016】また、チップ型抵抗体4を実装後、部品実
装部分に開口部を設けた層間絶縁層を積層する際、実装
した当該チップ型抵抗体4より層間絶縁層の高さが高い
方が、積層プレスで圧着する際、直接チップ型抵抗体4
に圧力がかからないため、実装したチップ型抵抗体4が
破損することがないため有効である。Further, after the chip-type resistor 4 is mounted, when the interlayer insulating layer having the opening provided in the component mounting portion is laminated, the height of the interlayer insulating layer is higher than that of the mounted chip-type resistor 4. , Directly chip-type resistor 4 when crimping with laminated press
Since no pressure is applied to the chip-type resistor 4, the mounted chip-type resistor 4 is not damaged, which is effective.
【0017】更に、チップ型抵抗体を実装した後、部品
実装部分に開口部を設けた2枚以上の色調の異なる層間
絶縁層を重ね、次いで絶縁層で全体を覆い積層し、色調
の異なる絶縁層の界面まで実装部品を含め研磨すること
で薄型化及び厚みを揃えるうえでは有効である。Further, after mounting the chip-type resistor, two or more interlayer insulating layers having different color tones, each having an opening at the component mounting portion, are laminated, and then the whole is covered with an insulating layer to be laminated to form an insulating layer having a different color tone. It is effective to reduce the thickness and make the thickness uniform by polishing the mounted components up to the layer interface.
【0018】図2は本発明の実施の形態を示したもので
ある。まず、図2(a)に示したように、絶縁層1aの
表裏に配線回路2及び実装ランド2aが形成された内層
基板1を、サブトラクティブ法等の常法の加工により得
る。絶縁層1aとしては、ガラス織布、あるいは不織布
にエポキシ樹脂、ポリイミド樹脂、BT(ビスマレイイ
ミド−トリアジン)樹脂、オレフィン樹脂等を含浸した
ものが挙げられ、配線回路2及び実装ランド2aとして
は、一般的な銅等の金属が好ましい。次いで、実装ラン
ド2aを除いた所望のパターンのソルダーレジスト3を
形成した後、はんだペーストを実装ランド2aに印刷す
る。次いで、当該実装ランド2aにチップ型抵抗体4を
図1(b)のように通常とは逆向きに、すなわち、支持
体15を上側に位置せしめると共に、抵抗体5をランド
側にして配置した後、リフロー工程により当該実装ラン
ド2aとチップ型抵抗体4の側面電極17とをはんだ6
で接続する。これにより、図2(a)チップ型抵抗体4
が両面に実装された内層基板1を得る。FIG. 2 shows an embodiment of the present invention. First, as shown in FIG. 2A, the inner layer substrate 1 in which the wiring circuits 2 and the mounting lands 2a are formed on the front and back surfaces of the insulating layer 1a is obtained by a conventional method such as a subtractive method. Examples of the insulating layer 1a include glass woven cloth or non-woven cloth impregnated with epoxy resin, polyimide resin, BT (bismaleimide-triazine) resin, olefin resin, and the like. As the wiring circuit 2 and the mounting land 2a, Common metals such as copper are preferred. Next, after forming the solder resist 3 having a desired pattern excluding the mounting lands 2a, a solder paste is printed on the mounting lands 2a. Next, as shown in FIG. 1B, the chip type resistor 4 is arranged on the mounting land 2a in the direction opposite to the normal direction, that is, the support 15 is positioned on the upper side and the resistor 5 is arranged on the land side. After that, the mounting land 2a and the side surface electrode 17 of the chip type resistor 4 are soldered by a reflow process.
Connect with. As a result, the chip-type resistor 4 shown in FIG.
The inner layer board 1 having the both surfaces mounted is obtained.
【0019】次に、図2(a)の内層基板1の両面に、
7a、7b、7cの3層構造とした層間絶縁層7を図2
(b)のように配置する。層間絶縁層7aは、後にチッ
プ型抵抗体4を薄型化する際の指標となる厚さを有する
層であり、当該チップ型抵抗体4の位置に対応する部位
に開口部8を有するものである。層間絶縁層7bは、当
該層間絶縁層7aと色調が異なり、研磨可能領域を示す
機能を有する層で、層間絶縁層7aと同様の開口部8を
有するものである。層間絶縁層7cは、当該層間絶縁層
7bとは色調が異なり(層間絶縁層7aと同色でも構わ
ない)、当該開口部8の形成によりできた間隙を埋める
と共に、層間絶縁層7aから7cを積層した際に、チッ
プ型抵抗体4が埋まる程度の厚さを有するものである。
確実にチップ型抵抗体4を層間絶縁層で埋めることで、
積層の際の圧力が直接当該チップ型抵抗体4にかからな
いため破損することがなくなり歩留まりが向上する。こ
こで絶縁層7cの色調を絶縁層7bと異なる色調にした
理由は、各層間絶縁層を積層する際、当該絶縁層7aの
開口部内に僅かに層間絶縁層7cの樹脂が流れ込んだ場
合、層間絶縁層7cと7bとが同色であると研磨可能領
域の境界線が不鮮明となるためである。当該層間絶縁層
7aから7cの種類としては、内層基板1の絶縁層1a
と同様なものが挙げられ、層間絶縁層7aは、開口部8
を樹脂で埋める必要があるため、Bステージ(半硬化状
態)のものを使用し、層間絶縁層7bは、層間絶縁層7
aの開口部に層間絶縁層7bの樹脂が入らないようにC
ステージ(硬化済)のものを使用し、層間絶縁層7c
は、層間絶縁層7aと同様のものを用いることができ
る。また、層間絶縁層7a及び7bの開口部8は、金型
によるパンチング、NCドリル、レーザ加工等により形
成できる。以上の層間絶縁層7aから7cの層間絶縁層
をプレスプレート9により積層プレスすることによっ
て、図2(c)の状態の積層板を得る。Next, on both surfaces of the inner layer substrate 1 of FIG.
The interlayer insulating layer 7 having a three-layer structure of 7a, 7b, and 7c is shown in FIG.
Arrange as shown in (b). The interlayer insulating layer 7a is a layer having a thickness that serves as an index when the chip type resistor 4 is thinned later, and has an opening 8 at a position corresponding to the position of the chip type resistor 4. . The interlayer insulating layer 7b is a layer having a color tone different from that of the interlayer insulating layer 7a and having a function of indicating a polishable region, and has an opening 8 similar to that of the interlayer insulating layer 7a. The interlayer insulating layer 7c has a different color tone from the interlayer insulating layer 7b (may be the same color as the interlayer insulating layer 7a), fills the gap formed by the formation of the opening 8, and stacks the interlayer insulating layers 7a to 7c. The thickness is such that the chip-type resistor 4 is buried in the case.
By surely filling the chip resistor 4 with the interlayer insulating layer,
Since the pressure at the time of stacking is not directly applied to the chip type resistor 4, the chip type resistor 4 is not damaged and the yield is improved. The reason why the color tone of the insulating layer 7c is different from that of the insulating layer 7b is that when the resin of the interlayer insulating layer 7c slightly flows into the opening of the insulating layer 7a when the interlayer insulating layers are laminated, This is because if the insulating layers 7c and 7b have the same color, the boundary line of the polishable region becomes unclear. The types of the interlayer insulating layers 7a to 7c include the insulating layer 1a of the inner layer substrate 1.
The interlayer insulating layer 7a may be formed in the opening 8
Since it is necessary to bury it with resin, a B-stage (semi-cured state) is used, and the interlayer insulating layer 7b is
C so that the resin of the interlayer insulating layer 7b does not enter the opening of a.
Interstage insulating layer 7c using the stage (hardened)
The same material as the interlayer insulating layer 7a can be used. The openings 8 in the interlayer insulating layers 7a and 7b can be formed by punching with a die, NC drill, laser processing, or the like. The above-mentioned interlayer insulating layers 7a to 7c are laminated and pressed by the press plate 9 to obtain a laminated plate in the state of FIG. 2 (c).
【0020】次に、図2(c)の積層板をバフ研磨、平
面研磨、マシニングセンター、ベルト研磨等の手段によ
って、層間絶縁層7aの層が露出するまで研磨を行う。
これにより、研磨で薄くなった層間絶縁層7(a)と並
行で、且つ所望の厚さに研磨されたチップ型抵抗体4が
形成された図2(d)の状態の積層板を得る。Next, the laminated plate of FIG. 2 (c) is polished by means such as buff polishing, flat surface polishing, machining center and belt polishing until the layer of the interlayer insulating layer 7a is exposed.
As a result, a laminated plate in the state of FIG. 2D is obtained in which the chip type resistor 4 is formed in parallel with the interlayer insulating layer 7 (a) thinned by polishing and polished to a desired thickness.
【0021】次に、図2(d)の積層板に第二絶縁層1
0及び導体箔11、あるいは両者は予め積層した樹脂付
き銅箔を積層することによって、図2(e)の積層体を
得る。次いで当該導体箔11に回路形成を施し、図2
(a)から図2(e)の工程を繰り返すことによって、
図2(f)に示すようなチップ型抵抗体4が内蔵された
多層プリント配線板12を得る。表裏の導通及び各層間
の導通は、貫通スルーホールを設けたり、各層間をIV
H、BVHで接続し各層の導通を得ても構わない(図示
せず)。Next, the second insulating layer 1 is formed on the laminated plate of FIG.
0 and the conductor foil 11 or both are laminated with a resin-coated copper foil laminated in advance to obtain the laminated body of FIG. Next, a circuit is formed on the conductor foil 11,
By repeating the steps from (a) to FIG. 2 (e),
A multilayer printed wiring board 12 having a built-in chip type resistor 4 as shown in FIG. 2 (f) is obtained. For the conduction between the front and back sides and the conduction between each layer, a through-hole is provided, and each layer is IV
H and BVH may be connected to obtain conduction in each layer (not shown).
【0022】斯かる本発明の実施の形態によれば、層間
絶縁層7の厚みを実装したチップ型抵抗体よりも高くす
ることで、積層時のプレス圧力が直接チップ型抵抗体に
かかることを防ぎ、更に色調の異なった層間絶縁層を研
磨領域として設けているため、チップ型抵抗体4が破損
することなく、精度よく薄型化できる。According to such an embodiment of the present invention, by making the thickness of the interlayer insulating layer 7 higher than that of the mounted chip type resistor, the pressing pressure at the time of lamination is directly applied to the chip type resistor. In addition, since the interlayer insulating layer having a different color tone is provided as the polishing region, the chip resistor 4 can be accurately thinned without being damaged.
【0023】[0023]
【発明の効果】本発明によれば、トリミング等による抵
抗値調整を行うことなく、また、経時変化の少ない安定
した抵抗値を有するチップ型抵抗体を内蔵した多層プリ
ント配線板を得ることができる。According to the present invention, it is possible to obtain a multilayer printed wiring board having a built-in chip-type resistor having a stable resistance value with little change over time without adjusting the resistance value by trimming or the like. .
【図1】チップ型抵抗体の実装構造を説明するための概
略断面図。FIG. 1 is a schematic sectional view for explaining a mounting structure of a chip resistor.
【図2】本発明の実施の形態を説明するための概略断面
工程図。FIG. 2 is a schematic cross-sectional process diagram for explaining the embodiment of the invention.
1:内層基板 2:配線回路 3:ソルダーレジスト 4:チップ型抵抗体 5:抵抗体 6:はんだ 7:層間絶縁層 7a、7b、7c:層間絶縁層 8:開口部 9:プレスプレート 10:第二の絶縁層 11:導体箔 12:多層プリント配線板 1: Inner layer substrate 2: Wiring circuit 3: Solder resist 4: Chip type resistor 5: resistor 6: Solder 7: Interlayer insulation layer 7a, 7b, 7c: interlayer insulating layer 8: opening 9: Press plate 10: Second insulating layer 11: Conductor foil 12: Multilayer printed wiring board
───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E346 AA06 AA12 AA15 AA26 AA38 AA60 BB01 CC02 CC08 CC31 DD02 DD32 EE02 EE06 EE07 EE09 FF45 GG15 GG22 GG28 GG40 HH11 HH24 HH33 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 5E346 AA06 AA12 AA15 AA26 AA38 AA60 BB01 CC02 CC08 CC31 DD02 DD32 EE02 EE06 EE07 EE09 FF45 GG15 GG22 GG28 GG40 HH11 HH24 HH33
Claims (4)
位置せしめると共に、その抵抗体をランド側にして内層
基板に実装する工程と;前記実装後の内層基板に層間絶
縁層を積層する工程と;前記積層後の積層板を研磨する
工程と;前記研磨後の積層板に絶縁層を介在せしめて導
体層を形成する工程とを有することを特徴とするチップ
型抵抗体を内蔵した多層プリント配線板の製造方法。1. A step of mounting a chip-type resistor on an inner layer substrate with its support positioned on the upper side and making the resistor on the land side; laminating an interlayer insulating layer on the inner layer substrate after the mounting. A step of polishing the laminated plate after the lamination; and a step of forming a conductor layer by interposing an insulating layer on the laminated plate after the polishing, Manufacturing method of printed wiring board.
体が実装された部分が開口され、かつ層間絶縁層の高さ
が実装されたチップ型抵抗体よりも高いことを特徴とす
る請求項1記載のチップ型抵抗体を内蔵した多層プリン
ト配線板の製造方法。2. The interlayer insulating layer according to claim 1, wherein a portion where the chip type resistor is mounted is opened, and the height of the interlayer insulating layer is higher than that of the mounted chip type resistor. Item 10. A method for manufacturing a multilayer printed wiring board incorporating the chip-type resistor according to Item 1.
装部分に開口部の設けられた少なくとも2枚以上の色調
の異なる絶縁層を積層すると共に、当該層間絶縁層と開
口部を覆う絶縁層を更に積層することを特徴とする請求
項2記載のチップ型抵抗体を内蔵した多層プリント配線
板の製造方法。3. The lamination of the above-mentioned interlayer insulating layer comprises laminating at least two or more insulating layers having different color tones each having an opening in a component mounting portion and covering the interlayer insulating layer and the opening. The method for manufacturing a multilayer printed wiring board having a built-in chip-type resistor according to claim 2, further comprising stacking layers.
縁層の界面まで実装されたチップ型抵抗体も含め研磨し
薄くすることを特徴とする請求項3記載のチップ型抵抗
体を内蔵したプリント配線板の製造方法。4. The chip-type resistor according to claim 3, wherein the chip-type resistor including the chip-type resistor mounted up to the interface of the interlayer insulating layers having different color tones is polished and thinned. Manufacturing method of printed wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2002029167A JP4015858B2 (en) | 2002-02-06 | 2002-02-06 | A method of manufacturing a multilayer printed wiring board with a built-in chip resistor. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002029167A JP4015858B2 (en) | 2002-02-06 | 2002-02-06 | A method of manufacturing a multilayer printed wiring board with a built-in chip resistor. |
Publications (2)
Publication Number | Publication Date |
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JP2003234579A true JP2003234579A (en) | 2003-08-22 |
JP4015858B2 JP4015858B2 (en) | 2007-11-28 |
Family
ID=27773587
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002029167A Expired - Lifetime JP4015858B2 (en) | 2002-02-06 | 2002-02-06 | A method of manufacturing a multilayer printed wiring board with a built-in chip resistor. |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006093493A (en) * | 2004-09-27 | 2006-04-06 | Cmk Corp | Printed wiring board with built-in part and method of manufacturing the same |
JP2008282882A (en) * | 2007-05-08 | 2008-11-20 | Nec Corp | Component built-in mounting substrate |
JP2009283689A (en) * | 2008-05-22 | 2009-12-03 | Dainippon Printing Co Ltd | Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board |
JP2012248897A (en) * | 2012-09-18 | 2012-12-13 | Dainippon Printing Co Ltd | Manufacturing method of component built-in wiring board, and component built-in wiring board |
-
2002
- 2002-02-06 JP JP2002029167A patent/JP4015858B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006093493A (en) * | 2004-09-27 | 2006-04-06 | Cmk Corp | Printed wiring board with built-in part and method of manufacturing the same |
JP2008282882A (en) * | 2007-05-08 | 2008-11-20 | Nec Corp | Component built-in mounting substrate |
JP2009283689A (en) * | 2008-05-22 | 2009-12-03 | Dainippon Printing Co Ltd | Method for manufacturing of component-incorporating wiring board, and component-incorporating wiring board |
JP2012248897A (en) * | 2012-09-18 | 2012-12-13 | Dainippon Printing Co Ltd | Manufacturing method of component built-in wiring board, and component built-in wiring board |
Also Published As
Publication number | Publication date |
---|---|
JP4015858B2 (en) | 2007-11-28 |
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