JP2003233349A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a liquid crystal display device. <P>SOLUTION: A liquid crystal panel 16 having a plurality of liquid crystal cells 17 arranged in the directions of row and column is provided with a gate driver 22 and a source driver 23. A video signal processing circuit 24 converts video signals into display data processible by the source driver 23, and outputs them to a gradation level detection circuit 26 and the source driver 23. The gradation level detection circuit 26 detects the gradation levels of the display data, and outputs them to a control signal generation circuit 25 as gradation level information. Based on this gradation level information, the control signal generation circuit 25 controls a source output halt signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption of a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, active matrix liquid crystal display devices are often used as display devices for mobile terminals that display color moving images and the like in order to improve image quality by increasing the viewing angle and definition and shorten the response speed. It is used.

A conventional active matrix type liquid crystal display device will be described below.

FIG. 6 is a block diagram of a conventional active matrix type liquid crystal display device. In the figure, reference numeral 1 denotes an active matrix type liquid crystal panel, which is composed of a liquid crystal cell 2, a switching element 3, a scanning signal line 4, a data signal line 5, and a counter electrode 6.

The liquid crystal cells 2 are arranged in a matrix in the row and column directions. The scanning signal lines 4 are scanning signal lines for selecting pixels in the same row direction, and it is assumed that p scanning signal lines 4 are provided along the column direction of the liquid crystal panel 1. The data signal lines 5 are signal lines for transmitting an applied voltage corresponding to display data to pixels in the same column direction, and it is assumed that q data signal lines 5 are provided along the row direction of the liquid crystal panel 1. The switching element 3 transmits the data of the data signal line 5 to the pixels of the liquid crystal cell 2 by the scanning signal from the scanning signal line 4, and is composed of, for example, a TFT. The counter electrode 6 is an electrode for supplying a common voltage to each liquid crystal cell.

The gate driver 7 applies a scanning signal to the scanning signal line 4 in the liquid crystal panel 1. Further, the source driver 10 generates an applied voltage according to display data and outputs it as a pixel signal from the data signal line 5 in the liquid crystal panel 1.
The video signal processing circuit 14 inputs a video signal from the outside, converts the video signal into display data that can be processed by the source driver 10, and outputs the display data to the driver 10. Control signal generation circuit 1
Reference numeral 5 outputs a signal for controlling the gate driver 7, the source driver 10, and the video signal processing circuit 15.

Next, the operation of displaying an image on the liquid crystal panel 1 will be described.

The control signal generation circuit 15 controls the gate driver 7 by a gate drive control signal to control the liquid crystal panel 1.
A scanning signal is applied to the scanning signal line 4 of any row of the. Then, the switching element 3 in that row is turned on, and the data signal line 5 in each column and the liquid crystal cell 2 are electrically connected. The video signal processing circuit 14 previously supplies the source driver 10 with data to be applied to the pixels in each column of the row to which the scanning signal is supplied. Then, the source driver 3 converts the display data into a voltage applied to each liquid crystal cell 2 and outputs it while the switching element 3 is in the ON state. Then, the control signal generation circuit 15 performs sequential scanning from the uppermost row (i = 1) to the lowermost row (i = p) of the liquid crystal panel 1,
Display the image on the full screen.

Here, examples of internal configurations of the gate driver 7 and the source driver 10 are shown in FIGS. 7 and 8, respectively. As shown in FIG. 7, the gate driver 7 is composed of a shift register circuit 8 and an output circuit 9. The shift register circuit 8 is a memory circuit for sequentially scanning the scanning signal lines 4 of each row. The output circuit 9 selects and outputs the voltage at which the switching element 3 is turned on and the voltage at which the switching element 3 is turned off according to the storage state of the shift register circuit 8.

As shown in FIG. 8, the source driver 10 includes a shift register circuit 11, a latch circuit 12, and a digital / analog conversion circuit (hereinafter referred to as a DA conversion circuit) 1.
It consists of 3. The shift register circuit 11 inputs the display data to the liquid crystal cells 2 of each column by the number of pixel columns,
Sequentially shift and store. The latch circuit 12 stores the display data for the liquid crystal cells 2 in each column while the scanning signal is applied to the scanning signal line 4 and the switching element 3 is in the ON state. The DA conversion circuit 13 converts the display data stored in the latch circuit 12 for the pixels in each column into an applied voltage and outputs the applied voltage to the switching element 3. Here, assuming that the display data output from the video signal processing circuit 14 is n bits, the shift register circuit 11 and the latch circuit 12 each store n bits of data.

The shift register circuit 11 sequentially stores the display data for each pixel in the scan row using the start signal in the source drive control signal from the control signal generation circuit 15 and the clock signal. Next, the latch circuit 12 latches the display data stored in the shift register circuit 11 by the load signal in the source drive control signal, and inputs the display data to the DA conversion circuit 13. DA conversion circuit 13
Converts n-bit display data to the liquid crystal cells 2 in each column into an analog voltage according to the characteristics of the liquid crystal cells 2 and supplies the analog voltage to the control input terminal of each switching element 3. Meanwhile, the shift register circuit 11 sequentially stores the display data of the next scan row.

In such a liquid crystal display device, the switching elements 3 of each row are turned on, and the source driver 10 applies a voltage to the data signal lines 5. In one scanning period, the number p of scanning signal lines of the liquid crystal panel 1 and Determined from the image update cycle. When the scanning period of the scanning signal line 4 of each row is longer than the minimum required charging time of the liquid crystal cell determined by the ON characteristic of the switching element 3 and the charging characteristic of the liquid crystal cell 2,
During the application of the voltage to the data signal line 5, the source driver 1
By stopping the output of 0, the power consumption of the source driver can be reduced. Such control is realized by inputting the source output stop signal from the control signal generation circuit 15 to the source driver 10 and stopping the operation of the output stage circuit of the DA conversion circuit 13 in the driver.

FIG. 9 shows the above-mentioned charge characteristic of the liquid crystal cell and the source output stop signal (PS) based on the charge characteristic. Hereinafter, this source output stop signal is changed to PS (Power Sa
ve) signal.

The liquid crystal panel 1 is a normally white type in which white display is performed when the liquid crystal cell 2 is not or hardly charged.

The graph of FIG.
The charging characteristics of the liquid crystal cell 2 when the white level, halftone level, and black level voltages are applied to the liquid crystal cell 2 when bit display data is input are shown. When the display data is n bits, the gray levels of the white level, the halftone level, and the black level are 2 ⁿ , 2 ^n-1 , and 0, respectively. In the figure, T _H is one scanning period during which the source driver 10 applies a voltage to the data signal line 5, and T _W and V _W are when the white level voltage is applied to the liquid crystal cell 2, respectively. Time to complete charging, and charging voltage at that time, T _M ,
V _M, when the voltage of the intermediate tone level is applied, the time until charging is complete, and the charging voltage at that time, T
_B, is V _B, when the voltage of the black level is applied, the time until charging is complete, and the charging voltage at that time. Due to this charging characteristic, when the white level voltage is applied to the liquid crystal cell 2, the output of the source driver 10 can be stopped from T _W to T _H during one scanning period T _H. Similarly, when a voltage of a halftone level and a voltage of a black level are applied, the voltage can be stopped during T _M to T _H and T _B to T _H , respectively.
However, since voltages of various gradation levels are actually applied, it is necessary to sufficiently charge all display data. Therefore, in most cases, the source output suspension period is from T _B to T _H at the black level when the charging time is the longest. That is, regardless of the gradation of the display data, the output of the source driver 10 is stopped while the PS signal in FIG. 9 is at the high level.

FIG. 10 shows an operation timing chart of the conventional liquid crystal display device described above. In the figure, X _i (i = 1,
2, ..., P) are output signals of the gate driver 7, Y _j
(J = 1, 2, ..., Q) are output signals of the source driver 10. Further, V _gon is the voltage of the scanning signal line 4 when the switching element 3 is turned on, and V _goff is the voltage of the element 3
Of the scanning signal line 4 when V is completely turned off, V
_ij (i = 1, 2, ..., P, j = 1, 2, ...
q) indicates a voltage applied by the source driver 10 to the data signal line 5 while the gate driver 2 scans the scanning signal line X _i . T _V is the time required for the liquid crystal display device to sequentially scan the entire screen, T _H is the time for scanning one scanning signal line X _i , T _on is the data which the source driver 10 outputs during one scanning period. During the period in which the output voltage is applied to the signal line 5, T _off is equal to the source driver 10 during one scanning period.
Is a period during which the output to the data signal line 5 is stopped. PS is a signal for stopping the output of the source driver 10, and is at a high level during the above T _off , and stops the output during this period.

Here, the entire screen scanning time T _V is determined depending on the use of each liquid crystal display device, and the scanning time T _H of one scanning signal line is determined from the number of scanning signal lines. Also, due to the characteristics of the liquid crystal cell 2, the output voltage application time T _on of the source driver 10
Then, the output voltage stop time T _off is determined.

[0018]

In the active matrix type liquid crystal display device, the power consumption of the source driver occupies a fraction to one half of the power consumption of the entire device. Therefore, in the case of a battery-operated device such as a portable terminal, it is necessary to reduce the power consumption of the source driver in order to extend the usage time of the terminal.

As described in the above-mentioned conventional technique, the liquid crystal has a property that the charging characteristic varies depending on the gradation of the applied data. That is, in the normally white type liquid crystal panel 1, when the display data is at the white level, the time required for charging becomes shorter, and the charging time becomes longer as the gray level decreases such as halftone and black level. Therefore, the period in which the voltage applied from the source driver 10 to the data signal line 5 is stopped can be longer for higher gradations such as white level and shorter for lower gradations such as black level, thereby reducing the power consumption of the source driver 10. Can be reduced.

However, in the conventional liquid crystal display device, in order to ensure sufficient charging for all display data,
The period in which the voltage applied from the source driver 10 to the data signal line 5 is stopped is the black level, which requires the longest time to charge.
It is fixed at a short length corresponding to low gradation.

For this reason, when the display data of the high gradation to the intermediate gradation is inputted, the applied voltage stop period becomes short in spite of being long, and the source driver 10
Power is wasted in. In view of the above problems, it is an object of the present invention to provide a liquid crystal display device that can reduce power consumption by varying the output suspension period of the source driver according to the grayscale level of display data.

[0022]

In order to solve the above problems, the present invention is a liquid crystal display device for displaying a video signal on a liquid crystal panel, which is arranged in a row direction and a column direction of the liquid crystal panel. A plurality of liquid crystal cells and connected to the liquid crystal cells,
It has a control output end, a first control input end to which a selection scanning signal is input, and a second control input end to which a pixel signal for row-direction scanning is applied, and is arranged in a matrix position of the liquid crystal panel. A plurality of switching elements, a plurality of row-direction signal lines respectively connected to the first control input terminals of the same scanning row of the switching elements, and a second control input terminal of the same column position of the switching elements, respectively. A plurality of column direction signal lines, a row direction drive circuit that sequentially outputs a selection scanning signal to a plurality of row direction signal lines, and a column direction drive circuit that outputs a pixel signal corresponding to display data to a plurality of column direction signal lines A video signal processing circuit for outputting display data to the liquid crystal panel to the column direction driving circuit, a control signal including an operation clock for the row direction driving circuit and the column direction driving circuit, and a control signal for the video signal processing circuit. And a control signal generation circuit for outputting a column direction signal output stop signal for stopping the output of a pixel signal corresponding to the display data to the column direction drive circuit, and detecting and controlling information about the gradation level of the display data. A gradation level detection circuit for outputting the information to the signal generation circuit,
And a control signal generating circuit for controlling the column direction signal output stop signal based on the information about the gradation level.

According to the present invention, the gradation level detecting circuit is
The gradation level of the display data is detected for each output terminal of the column direction drive circuit, and the control signal generation circuit outputs each output of the column direction drive circuit based on the information about the gradation level from the gradation level detection circuit. The liquid crystal display device is characterized in that the output stop signal is controlled for each terminal.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display device of the present invention. The liquid crystal panel 16 is an active matrix type liquid crystal panel, and has p × q liquid crystal cells 17, P scanning signal lines 19 (row direction signal lines), and q data signal lines 20.
(Column-direction signal line), p × q switching elements 18,
It is composed of a common counter electrode 21.

The liquid crystal cells 17 are arranged in a matrix in the row and column directions, and are connected to the drain electrode (control output terminal) when the switching element 18 is a TFT. The scanning signal line 19 is a scanning signal line for selecting pixels in the same direction, and is a gate electrode of the TFT (first control input end).
And p lines are provided along the column direction of the liquid crystal panel. The data signal line 20 is a data signal line for transmitting an applied voltage according to display data to the liquid crystal cells in the same column direction, is connected to the source electrode (second control input terminal) of the TFT, and is in the row direction of the liquid crystal panel. Are provided along with. The switching element 18 is an active element that transmits the data of the data signal line 20 to the liquid crystal cell by a scanning signal, and is composed of a TFT here. The counter electrode 21 is an electrode for supplying a common voltage to each liquid crystal cell 17.

The gate driver 22 is a row-direction drive circuit that sequentially applies scanning signals to the p scanning signal lines 19 in the liquid crystal panel 16. The source driver 23 is a column-direction driving circuit that supplies the data signal line 20 in the liquid crystal panel 16 with an applied voltage according to display data as a pixel signal. The gate driver 22 and the source driver 23 are
The gate driver 7 and the source driver 10 of the conventional example are configured by the same circuits and operate in the same manner.

The video signal processing circuit 24 inputs a video signal from the outside, converts it into display data that can be processed by the source driver 23, and outputs it to the driver 23. The control signal generation circuit 25 supplies a start signal to the gate driver 25 and a gate drive control signal including an operation clock signal to the source driver 23,
The source drive control signal including the operation clock and the load signal and the video circuit control signal are output to the video signal processing circuit 24. Further, a gradation level detection circuit 2 described later
The gradation level information is input from 6 and a source output stop signal based on it is output to the source driver 23. The source output stop signal stops the operation of the output stage circuit of the DA conversion circuit 13 in the source driver 23, and the data signal line 2
The output of the voltage applied to 0 is stopped. Details of the source output stop signal will be described later.

The gate drive control signal is supplied to the gate driver 2
2 control the operation. The source drive control signal controls the operation of the source driver 23. The video circuit control signal controls the video signal processing circuit 24.

The gradation level detection circuit 26 detects information about the gradation level of the display data from the video signal processing circuit 24 and outputs it to the control signal generation circuit 25. The operation will be described below.

FIG. 2 shows the internal structure of the gradation level detection circuit 26, which includes a gradation data detection section 27 and a detection information output section 2.
It is composed of 8. When the display data from the video signal processing circuit 24 to the tone level detection circuit 26 is input, among the display data input during one scanning period T _H of the above in the gradation data detector 27, the lowest gradation Detect data. The data with the lowest gradation is detected in order to secure sufficient charge of the liquid crystal cell 17 for all the display data during T _H. Then, the detection information output unit 28 sets the gradation of the detected data as gradation level information,
Output to the control signal generation circuit 25. If the display data is n bits, there are 2 ⁿ gradation levels. Therefore, 2 ⁿ kinds of gradation level information corresponding to the detected gradation of the data are output to the control signal generating circuit 25. The control signal generation circuit 25 controls the source output stop signal (PS signal) output to the source driver 23 based on this gradation level information. This PS signal is as described below.
Corresponding to 2 ⁿ kinds of gradations, it is assumed that 2 ⁿ kinds of outputs are output.

FIG. 3 shows the charging characteristics of the liquid crystal cell 17 and the PS signal output from the control signal generating circuit 25 to the source driver 23. The liquid crystal panel 16 is a normally white type like the liquid crystal panel 1 in the related art.
Therefore, the graph of the charging characteristic is the same as that of FIG. 9 described in the related art. However, T _N and V _{N in} the figure are the time until the charging of the liquid crystal cell 17 is completed when the voltage between the white level and the halftone level is applied, and the charging voltage at that time. , T _K and V _K are the liquid crystal cell 17
Is the time until the charging of the cell 17 is completed when a voltage between the halftone level and the black level is applied, and the charging voltage at that time. Each signal PS _W under the graph,
PS _N , PS _M , PS _K , and PS _B are gradation level detection circuits 2
6 is a source output stop signal output from the control signal generation circuit 25 to the source driver 23 during one scanning period T _H based on the gradation level information from 6. PS _W is _TH
Gradation all white level of the data in time and which was (tone 2 ^n), PS _M is the tone of the most tone low data in the T _H halftone level (gradation 2 ^n-1) When it was, PS
_B is when the gradation of the most tone low data in the T _H was black level (gradation 0) shows the source output stop signal. Also when PS _N are most tone low gray scale in T _H is between the white level and the gray level, P
S _K is the tone of the most tone low data in the T _H is, when is between black level and the gray level indicates the source output stop signal. These signals, as described above, is output 2 ⁿ as corresponding to the gradation level of the street 2 ^n. Further, the output of the applied voltage from the source driver 23 to the data signal line 20 is stopped while the signals PS _W , PS _N , PS _M , PS _K , and PS _B are at the high level. That is, when the data in one scanning period T _H is all at the white level, the charging of the liquid crystal cell 17 is completed in the period from T _W to T _{H in} FIG. Stop output. Similarly, when the gradation of the lowest gradation data in T _H is the halftone level or the black level, the applied voltage output is stopped during the periods T _M to T _H and T _B to T _H , respectively. When the gradation of the lowest gradation data in T _H is between the white level and the halftone level and between the halftone level and the black level, T _N to T _H and T _K to T _H , respectively. The output of the applied voltage is stopped during the period.

FIG. 4 is a diagram showing the effect of reducing power consumption in the liquid crystal display device according to the embodiment of the present invention. The horizontal axis represents the time when the output of the source driver 23 is stopped, and the vertical axis represents the power consumption of the source driver 23. T _B in FIG. _{', T M', T W} ' , _{respectively, T B' = T H -T} B,
There is a relationship of T _M ′ = T _H −T _M and T _W ′ = T _H −T _W. The source driver 23 in the case where the data in T _H has the lowest gray level of the data, the gray level of the lowest level of the data, the gray level of the lowest level of the data is the intermediate level, and the white level is all. Shows the output stop time of. Also P _B ,
P _M and P _W indicate the power consumption of the source driver 23 in each case. As shown in the figure, the higher the gradation of the display data is, the longer the output stop time of the source driver can be made, and the power consumption can be reduced.

FIG. 5 shows an operation timing chart of the liquid crystal display device of the present invention described above.

In the figure, X _i (i = 1, 2, ..., P) is
The output signal of the gate driver 22, Y _j (j = 1, 2, ...
, Q) are output signals of the source driver 23. Further, V _{go n} is the value when the switching element 18 is turned on,
The voltage of the scanning signal line 19, V _goff, is the voltage of the scanning signal line 19 when the element 18 is completely off, V _ij (i =
, 2, p, j = 1, 2, ..., Q), when the gate driver 22 scans the scanning signal line 19,
The voltage applied by the source driver 23 to the data signal line 20 is shown.

T _V is the time required for the entire liquid crystal device to sequentially scan the entire screen, T _H is the time required to scan one scanning signal line Xi, T _onk (k = 1, 2, ...). p) indicates a period T during which the source driver 23 applies an output voltage to the data signal line 20 during the scanning period T _H when the gate driver 22 scans the scanning signal line X _k.
offk (k = 1, 2, ..., P) is the gate driver 22
Scans the scanning signal line X _k , the scanning period T _H
During this period, the source driver 23 stops applying the output voltage to the data signal line 20. PS is a signal for stopping the output of the source driver 23, which is at a high level during the above-described T _offk , and stops the output during this period.

In the figure, the first line (X₁) Source
Driver output Y_jOutput voltage of (j = 1, 2, ..., q)
V_1j(J = 1, 2, ..., Q) are all white levels.
Suppose. Therefore, the PS signal also corresponds to the white level
PS of 3_WAnd the output voltage of the source driver 23 stops.
Period T to be stopped_off1Is the longest of all gradations. Well
2nd line (X₂) Same output voltage V_2j(J = 1, 2, ...
·, Q) is V_{twenty one}, And V_2qIs the white level, V_{twenty two}, And
And V_{2j '}Is a halftone level, and other output voltages are white
It should be between the bell and the midtone level. At this time T
_HThe lowest gray level is the halftone level. According to
The PS signal is the PS of FIG. 3 corresponding to the halftone level._MTona
The period T during which the output voltage of the source driver 23 is stopped
_off2Is T_{o ff1}Will be shorter than. And the p-1th line
(X_p-1) Source driver output Y_jOutput voltage V
_p-1jIs V_p-11, And V_{p-1j '}Is the white level, V_p-12But
Black level, V_{p -1q}Is a halftone level, other output voltage
Is at the black level or at any other level. This and
T_HThe lowest gray level is the black level. According to
The PS signal is the PS of FIG. 3 corresponding to the black level._BNext to
Period T during which the output voltage of the source driver 23 is stopped
_offp-1Is the shortest of all gradations. Finally, line p
(X _p) Source driver output Y_jOutput voltage V_pjIs V
_p1, And V_pqIs the white level, V_p2Is a halftone level, V
_{pj '}Output between black level and halftone level
Is V_{pj '}It is assumed that the level is higher than that. At this time T_H
The lowest gradation is V_{pj '}It becomes the gradation of. Therefore
The PS signal is the PS of FIG. 3 corresponding to this level._KNext to
Period T during which the output voltage of the source driver 23 is stopped_offp
Is T_offp-1Longer than T_off2Will be shorter than. Sanawa
Chi T_off1, T_off2, T_offp-1, T_offpIn between
_offp-1<T_offp<T_off2<T_off1The relationship is established.

The period of T _offk (k = 1, 2, ..., P) is a period in which the PS signal becomes high level.
The high level period of the signal, that is, the period during which the output voltage of the source driver 23 is stopped is changed for each row according to the gradation level of the display data, and the power consumption of the source driver 23 is reduced.

In the present invention, the gradation level of the display data is detected for each scanning period T _H and the high level period of the PS signal is also changed correspondingly for each T _H. Each output terminal Y _j (j =
, 2, q), and the high level period of PS may be changed for each of these output terminals. In this case, the gradation data detection unit 27 detects the gradation level of the display data for each output terminal of the source driver 23. The detection information output unit 28 outputs 2 ⁿ kinds of gradation level information for each output terminal to the control signal generation circuit 25. Then, the control signal generation circuit 25 outputs 2 ⁿ kinds of PS signals shown in FIG. 3 corresponding to the gradation level information for each output terminal to the source driver 23. The source driver 23 stops the output period for each output terminal based on these PS signals.

In the PS signal control for each scanning period T _H , T _H
It is necessary to secure sufficient charge of the liquid crystal cell 17 for all the display data therein. Therefore, if there is even one black level data in T _H , the source driver output suspension period becomes longer corresponding to the black level data even if the rest is all white level data. On the other hand, in the PS control for each output terminal of the source driver, the output suspension period of each output terminal is controlled by the PS signal corresponding to the gradation of the display data for each output terminal. Thus more precisely than in the one scanning period T _H, it is possible to reduce the power consumption of the source driver 23.

As described above, in the liquid crystal display device according to the embodiment of the present invention, the power consumption of the source driver can be reduced by varying the output suspension period of the source driver 23 according to the gradation level of the display data. It will be possible. In particular, in the active matrix type liquid crystal display device as described above, the power consumption of the source driver occupies a fraction to a half of the entire device, so that the effect is great.

[0042]

As described above, according to the liquid crystal display device of the present invention, the power consumption of the source driver, which occupies most of the entire device, can be reduced according to the gradation level of the display data.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a gradation level detection circuit in a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a diagram showing charge characteristics of liquid crystal and a source driver output stop signal in a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a power consumption reduction effect in a liquid crystal display device according to an embodiment of the present invention.

FIG. 5 is an operation timing chart of the liquid crystal display device according to the embodiment of the present invention.

FIG. 6 is an overall configuration diagram of a conventional liquid crystal display device.

FIG. 7 is a circuit configuration diagram of a gate driver used in a conventional liquid crystal display device.

FIG. 8 is a circuit configuration diagram of a source driver used in a conventional liquid crystal display device.

FIG. 9 is a diagram showing a charge characteristic of liquid crystal and a source driver output stop signal in a conventional liquid crystal display device.

FIG. 10 is an operation timing chart of a conventional liquid crystal display device.

[Explanation of symbols]

16 LCD panel 17 Liquid crystal cell 18 switching elements 19 scanning signal lines 20 data signal lines 21 Counter electrode 22 Gate driver 23 Source Driver 24 Video signal processing circuit 25 Control signal generation circuit 26 gradation level detection circuit 27 gradation data detector 28 Detection information output section

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 641 G09G 3/20 641C (72) Inventor Takashi Tsukada 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F-term (reference) 2H093 NA16 NC13 NC25 NC26 NC34 ND39 ND42 ND49 ND56 NE03 NE07 5C006 AA01 AA16 AC11 AC21 AF42 AF45 AF51 AF52 AF53 AF61 AF69 AF71 BB16 BC11 BF14 BF24 FA47 5C080 AA10 BB05 DD47 JJ05 JJ05 JJ05 JJ05 JJ05

Claims (2)

[Claims] 1. A liquid crystal display device for displaying a video signal on a liquid crystal panel, comprising a plurality of liquid crystal cells arranged in a row direction and a column direction of the liquid crystal panel, and a control output connected to the liquid crystal cell. End and a first control input end to which a selection scanning signal is input and a second control input end to which a pixel signal for row-direction scanning is applied, and a plurality of them are arranged at a matrix position of the liquid crystal panel. Switching elements, a plurality of row-direction signal lines respectively connected to first control input terminals of the same scanning row of the switching elements, and second control input terminals of the same column position of the switching elements, respectively. A plurality of column-direction signal lines, a row-direction drive circuit that sequentially outputs a selection scanning signal to the plurality of row-direction signal lines, and a column that outputs a pixel signal corresponding to display data to the plurality of column-direction signal lines With direction drive circuit A video signal processing circuit for outputting display data to the liquid crystal panel to the column direction drive circuit,
The output of a control signal including an operation clock for the row direction drive circuit and the column direction drive circuit, a control signal for the video signal processing circuit, and a pixel signal corresponding to the display data for the column direction drive circuit is stopped. A column direction signal output stop signal, a control signal generation circuit that outputs the signal, and a gradation level detection circuit that detects information regarding the gradation level of the display data and outputs the information to the control signal generation circuit. The liquid crystal display device, wherein the control signal generation circuit controls the column-direction signal output stop signal based on the information about the gradation level. 2. The liquid crystal display device according to claim 1, wherein the grayscale level detection circuit detects a grayscale level of the display data for each output terminal of the column direction drive circuit, and outputs the control signal. The liquid crystal display device, wherein the generation circuit controls an output stop signal for each output terminal of the column driving circuit based on the information about the gradation level from the gradation level detection circuit.