JP2003229539A - Capacitor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor that can uniformly polish a lower electrode and the surface of an insulating film without causing any recesses, scratches, polishing remainder, and peel-off, and to provide a method for manufacturing the capacitor. <P>SOLUTION: A lower electrode 11 is formed on a semiconductor substrate. The lower electrode is covered for sequentially forming first and second buried insulating films 8 and 9 on an entire surface. The second buried insulating film 9 is flattened by a CMP method, the first buried insulating film 8 is exposed on the lower electrode, the first and the second buried insulating films are polished by the CMP method under conditions where the first buried insulating film is easily polished as compared with the second buried insulating film, and the surface of the lower electrode is exposed. A capacity insulating film 5 is formed so that the lower electrode is covered. Then, an upper electrode 6 is formed so that the capacity insulating film is covered. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element using a ferroelectric as a capacitive insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art Ferroelectric memories use a planar structure in which a lower electrode is larger than an upper electrode and have a width of 1 to 64 kbit.
, Which has a small capacity, has begun to be mass-produced, and the lower electrode has a stack type structure smaller than that of the upper electrode.
The large capacity of Mbit has become the center of development. Realization of this stack-type ferroelectric memory is expected to greatly improve the degree of integration and further improve the characteristics of the nonvolatile memory in terms of reliability.

In a capacitive element, the smaller electrode area of the opposing lower electrode and upper electrode defines the capacitance of the capacitive element. Therefore, when the electrode area of the lower electrode of the lower electrode and the upper electrode facing each other is small, the lower electrode serves as the capacitance defining port of the capacitive element. A conventional ferroelectric memory having a stack type structure in which a lower electrode has a counter electrode area smaller than that of an upper electrode is disclosed in Japanese Patent Laid-Open No. 2000-1383.
As disclosed in Japanese Patent Publication No. 49, the lower electrode is insulated by the CMP method (Chemical Mechanical Polishing) in order to form a ferroelectric film without being affected by the unevenness of the base. By embedding the film in the film and planarizing it, a structure that prevents the weakness of the film thickness variation when forming the ferroelectric film by the spin coating method when there is a step is realized, and a highly reliable ferroelectric memory and The manufacturing method is realized.

The above-mentioned conventional ferroelectric memory will be described below with reference to FIGS.

6 to 7 are process cross-sectional views showing a method of manufacturing a capacitive element for a conventional ferroelectric memory. First, as shown in FIG. 6A, the plug 3 electrically connected to the high-concentration impurity diffusion layer 2 isolated by the isolation region 1 made of an insulating film such as an oxide film is placed in the interlayer insulating film 7. On the formed semiconductor substrate 20, the first conductive film 11 is formed.
(For example, a titanium nitride barrier layer (lower layer) and a platinum film (upper layer) are formed). Next, as shown in FIG. 6B, a resist pattern (not shown) is then formed at a desired position.
Then, the first conductive film 11 to be the lower electrode is patterned by dry etching using the resist pattern as a mask to form the lower electrode 4. Next, as shown in FIG. 6C, a filling insulating film 21 is formed on the entire surface. After that, as shown in FIG. 7D, the embedded insulating film 21 is formed.
The embedded insulating film 21 is polished and planarized by the CMP method until the surface of the lower electrode 4 is exposed.

Subsequently, as shown in FIG. 7E, a ferroelectric film 12 serving as a capacitive insulating film 5 and a second conductive film serving as an upper electrode 6 are formed on the surfaces of the lower electrode 4 and the buried insulating film 21. (For example, a platinum film) 13 is formed. After that, FIG. 7 (f)
As shown in FIG. 3, a resist pattern is formed at a desired position (not shown), and the second conductive film 13 to be the upper electrode 6 is formed by dry etching using the resist pattern as a mask.
The ferroelectric film 12 to be the capacitance insulating film 5 is patterned. After that, the capacitor interlayer insulating film 10 is usually formed, and the wiring process and the protective film forming process (not shown) are completed to complete a series of manufacturing processes.

When the ferroelectric film is formed by using the above structure, it can be formed on a flat substrate without underlying unevenness due to the lower electrode, so that a ferroelectric film having a good ferroelectric film quality is formed. It is possible.

[0008]

However, in the above-mentioned ferroelectric memory, when polishing by the CMP method, it is possible to expose a plurality of lower electrodes uniformly on the entire surface of the wafer.
It was very difficult from the viewpoint of the in-plane uniformity of the above, and therefore, some over-polishing was necessary to prevent polishing residue.

Therefore, in a part of the wafer, a recess is formed around the lower electrode which has been flattened once, that is, the lower electrode has a slight convex shape. That is, the material of the lower electrode is usually P
Noble metals such as t and Au are used. To expose the lower electrode, it is necessary to use a slurry for CMP in which the embedded insulating film 21 of FIG. 6C is polished. With such a CMP slurry for insulating film, noble metal is hard to be polished. Therefore, as described above, when a little over-polishing is performed, the embedded insulating film 21 around the lower electrode is selectively polished, so that the lower electrode has a slight convex shape.

In the lower electrode having the convex shape, as the recess amount of the convex shape increases, the mechanical polishing force acts on the electrode not only from above but also from the lateral direction, and the polishing force is increased. There was a problem that concentration was easy, scratches occurred, and the lower electrode itself peeled off. The above-mentioned polishing residue, peeling of the lower electrode, and scratches cause bit defects in the ferroelectric memory.

Further, since the ferroelectric memory is a non-volatile memory in which certain data is stored for a certain period of time and read out when necessary, it goes without saying that the ferroelectric memory is uniform in all bits. It is preferably made.

From this point of view, not only polishing residue and peeling of the lower electrode, but also variations in the ferroelectric film thickness due to recesses have a great influence on the reliability of data retention, and in some cases, the reliability of the data is reduced. There is a problem of causing deterioration and generation of defective bits. In particular, the variation in the film thickness of the ferroelectric film, which is one of the variations in the shape, greatly affects the characteristics of the ferroelectric memory due to its characteristics.

An object of the present invention is to solve such a problem, and it is a shape-stable and highly reliable structure which is free from polishing residue, recess, and peeling of the lower electrode of the embedded insulating film on the lower electrode. It is to provide a capacitive element suitable as a dielectric memory and a manufacturing method thereof.

[0014]

In order to solve the above-mentioned problems, the capacitive element of the present invention is formed by covering a lower electrode serving as a capacitance defining port formed on a semiconductor substrate and the lower electrode. In a capacitive element having a capacitive insulating film and an upper electrode formed by covering the capacitive insulating film, the lower electrode is embedded in a laminated film of first and second embedded insulating films, The first embedded insulating film is arranged below the second embedded insulating film and in contact with the side surface of the lower electrode, and the first embedded insulating film is the second embedded insulating film. It is characterized by being formed of an insulating film that is more easily polished.

In the capacitive element of the present invention, it is preferable that the first buried insulating film is an insulating film containing a metal element.

Further, in the capacitive element of the present invention, it is preferable that the lower electrode is made of Pt, Ir, Ru or an alloy film containing them, or a conductive material material containing an oxide thereof.

In the capacitive element of the present invention, the first buried insulating film is an insulating film selected from titanium oxide, aluminum oxide or titanium aluminum oxide, and the second buried insulating film is silicon oxide. An insulating film selected from a film or a silicon nitride film is preferable.

In the method of manufacturing a capacitive element according to the present invention, a step of forming a lower electrode on a semiconductor substrate and a step of covering the lower electrode and sequentially forming first and second buried insulating films on the entire surface. And planarizing the second buried insulating film by CMP, and depositing the first buried insulating film on the lower electrode.
The step of exposing the first buried insulating film and the step of polishing the first buried insulating film under the condition that the first buried insulating film is more easily polished than the second buried insulating film by the CMP method. And exposing the surface of the lower electrode, forming a capacitive insulating film so as to cover the lower electrode, and forming an upper electrode so as to cover the capacitive insulating film. Characterize.

In the method of manufacturing a capacitive element of the present invention, the first and second buried insulating films are polished,
It is preferable to further include a step of selectively removing a part of the first embedded insulating film after the step of exposing the surface of the lower electrode.

In the method of manufacturing a capacitive element of the present invention, the step of selectively removing a part of the first buried insulating film is such that the first buried insulating film contacts the side surface of the lower electrode. It is preferable that it is a step of removing at least an upper portion of the portion.

Further, in the method of manufacturing a capacitive element of the present invention, it is preferable that the lower electrode is formed of Pt, Ir, Ru or an alloy film containing them, or a conductive material containing an oxide thereof.

Further, in the method of manufacturing a capacitive element of the present invention, it is preferable that the first embedded insulating film is an insulating film containing a metal element.

In the method of manufacturing a capacitive element according to the present invention, the first buried insulating film is an insulating film selected from titanium oxide, aluminum oxide or titanium aluminum oxide, and the second buried insulating film is Is preferably an insulating film selected from a silicon oxide film or a silicon nitride film.

With such a capacitive element and the manufacturing method thereof, the first embedded insulating film which is easily CMP-polished is disposed on the entire surface of the lower electrode, and the second post-embedded insulating film is formed thereon. As a result, when the lower electrode is embedded in the insulating film by the CMP method and planarized, the insulating film in contact with the lower electrode is formed of the first embedded insulating film that is more easily polished than the second embedded insulating film. Therefore, the first embedded insulating film on the lower electrode is selectively polished as compared with the second embedded insulating film existing around the lower electrode,
It is possible to realize a recess-shaped lower electrode structure that completely prevents the occurrence of polishing residues of the recess and the buried insulating film on the lower electrode. In this way, it is possible to realize highly reliable ferroelectric capacitor characteristics without variation in characteristics from the aspect of shape and to realize a highly reliable capacitive element.

[0025]

1 and 2 are sectional views of steps of a method of manufacturing a capacitive element according to an embodiment of the present invention. FIG. 3 is a sectional view of a capacitive element according to an embodiment of the present invention.

First, as shown in FIG. 1A, an STI isolation region 1 (STI: Shallow Trench Isolation) formed of an insulating film such as an oxide film covered with an interlayer insulating film 7 is formed.
The first conductive film 11 is formed on the entire surface of the semiconductor substrate 20 including the high-concentration impurity diffusion layer 2 and the contact plug 3. The first conductive film is composed of a stack of titanium nitride (lower layer) that serves as a barrier of the contact plug 3 and a platinum film (upper layer). The contact plug 3 is, for example, tungsten (W)
The conductive barrier layer of the first conductive film 11 serves as a barrier layer for preventing the permeation of oxygen in order to prevent the contact plug 3 from being oxidized.
Next, as shown in FIG. 1B, the first conductive film 11 is patterned using a desired mask (not shown) so as to cover the contact plug 3, and the lower electrode 4 is formed by dry etching. To do. Next, as shown in FIG. 1C, the first embedded insulating film 8 (which is easier to polish than the second embedded insulating film on the entire surface where the lower electrode 4 is formed is referred to as “CMP polishing acceleration” below). And a second buried insulating film 9 are formed. Next in FIG.
As shown in (d), planarization is performed by the CMP method so that the first embedded insulating film (CMP polishing promoting layer) 8 on the lower electrode 4 is exposed.

Next, as shown in FIG. 2E, the first buried insulating film (CMP polishing promoting layer) 8 has a polishing selection ratio of 1 or more with respect to the second buried insulating film 9 (first buried insulating film). Under the condition that the insulating film 8 is more easily polished than the second embedded insulating film 9, the first embedded insulating film (CMP polishing promoting layer) 8 and the second embedded insulating film 9 are polished to form the lower electrode 4.
Perform CMP to expose the surface of.

Here, the first embedded insulating film (CMP polishing promoting layer) 8 is polished faster than the peripheral second embedded insulating film 9 and the lower electrode 4 is embedded in a concave shape, so that the lower electrode 4 is convex. Since the polishing force is not concentrated on the lower electrode 4 as compared with the case of being formed in a shape, it has an advantage that scratches are less likely to occur. Further, in the boundary region between the first embedded insulating film (CMP polishing promoting layer) 8 and the second embedded insulating film 9, the second embedded insulating film 9 is also affected by a phenomenon called erosion when two kinds of different films exist. Like the first buried insulating film (CMP polishing accelerating layer) 8, it is possible to prevent abrasion and prevent the occurrence of recesses. That is, in the present invention, the first embedded insulating film (CMP polishing promoting layer) 8
Even when polishing the second embedded insulating film 9, the second embedded insulating film 9 is scraped to some extent, and erosion occurs around the boundary region, so that the occurrence of recesses can be prevented. Even when over-polishing is performed, selective polishing is performed from the first buried insulating film (CMP polishing promoting layer) 8 on the lower electrode 4, and the polishing conditions are set appropriately, for example, the second When the condition that the embedded insulating film 9 is hardly scraped off is set, the second embedded insulating film 9 acts as a stopper function at the time of overpolishing, and the portion where the electrodes of a large number of capacitive elements are concentrated is formed as a whole. It is also possible to suppress the occurrence of a global step due to the phenomenon that polishing becomes difficult.

As an example of the condition in which the second embedded insulating film 9 is hardly scraped, various selections can be made according to the material forming the insulating film and the type of CMP slurry. As an example of forming the capacitive element of the present invention using a combination of materials that are considered to be preferable, use of a slurry for W (tungsten) (composition will be described later), and a polishing pressure of 4 pSi (= 14 kP)
a), ΔP (pressure difference between the surface plate of the CMP device and the carrier) is −
These conditions may be appropriately selected according to the combination of materials, such as the conditions of 0.05 Pa, pad rotation speed of 200 rpm, and slurry liquid amount of 100 ml / min. Here, the surface plate of the CMP device is a rotating jig for polishing a target semiconductor wafer surface which is an object to be polished, and is pressed against the surface to be polished of the semiconductor wafer while rotating with an appropriate pressure. To be The carrier is a rotatable jig that fixes and holds the semiconductor wafer so that the target surface of the semiconductor wafer to be polished is pressed onto the surface plate, and the semiconductor wafer should be polished on the surface plate. The semiconductor wafer is polished by pressing the surface while rotating it at an appropriate pressure.

Next, as shown in FIG. 2F, a ferroelectric film 12 to be the capacitance insulating film 5 and a second conductive film 13 to be the upper electrode 6 are formed on the entire surface. Next, as shown in FIG. 2G, patterning is performed using a desired mask (not shown) so that the lower electrode 4 is covered, and dry etching is performed to form the capacitive insulating film 5 made of the ferroelectric film 12. And upper electrode 6
To form.

Here, the capacitive insulating film 5 and the upper electrode 6 are patterned at the same time, but they may be patterned separately. Furthermore, a series of steps of covering this with the capacitor interlayer insulating film 10 makes it possible to realize a highly reliable ferroelectric memory of the present invention in which the ferroelectric characteristics do not vary.

Here, in FIG. 3, which is a sectional view showing the first embodiment of the capacitive element of the present invention, an insulating layer containing a metal element may be used as the first embedded insulating film (CMP polishing promoting layer) 8. preferable. The second embedded insulating film 9 is usually excellent in insulation between electrodes and capable of CMP polishing, various slurries for CMP have been developed, and CMP polishing conditions can be set appropriately. From the point of
A silicon oxide film or a silicon nitride film is often used, but the slurry for polishing these film types contains silica and alumina as the main components, and uses CMP by using abrasives and physical polishing force. Is. On the other hand, a film type such as an insulating layer containing a metal element such as the first embedded insulating film contains a chemical solution or the like that promotes a surface reaction according to the type of the film to be polished in the slurry, and the chemical reaction on the surface. The CMP is performed by utilizing the chemical reactivity of polishing the part that has been weakened by oxidizing the surface with an oxidizing agent contained in the slurry. is there. With this type of slurry, the second buried insulating film made of the silicon oxide film or the silicon nitride film is hardly polished.

That is, by using an insulating film containing a metal element such as titanium oxide, aluminum oxide or titanium aluminum oxide as the first buried insulating film (CMP polishing promoting layer), in the CMP exposing the lower electrode, Second embedded insulating film (CMP polishing promoting layer)
It is possible to set a condition that the polishing selection ratio with respect to the embedded insulating film is 1 or more.

FIG. 4 shows a W (tungsten) polishing slurry [composition: containing silica particles, ammonia and hydrogen peroxide;
(Abrasive silica particles (average particle size 200 nm or less, maximum particle size 500
μm or less), H ₂ O ₂ concentration of 2 wt%, pH 2.1 to 2.
5)] is used, the relationship between the polishing amounts of the first embedded insulating film (CMP polishing promoting layer) and the second embedded insulating film is shown. Here, the first buried insulating film (CMP polishing promoting layer)
Titanium aluminum oxide [sputtering conditions (power: 6 kW, temperature: room temperature, pressure: 6 Torr (800 P
a), gas: Ar / O ₂ = 1/3 (flow ratio sccm), Ti:
Titanium aluminum oxide formed by oxygen reactive sputtering of 60 atomic% / Al: 40 atomic%], and a silicon oxide film formed by atmospheric pressure CVD is used as the second embedded insulating film. From FIG. 4, by adjusting the polishing pressure to an appropriate value (for example, when the polishing pressure is 2 p
(Eg, pressure range larger than Si), polishing selectivity is 1
It is understood that the above conditions can be set.

As a modified example of this embodiment, the book of FIG.
A cross-sectional view showing a modification of the embodiment of the capacitive element of the invention is shown.
The CMP process to expose the lower electrode 4 (see FIG. 2 (e))
Of the first buried insulating film (CMP polishing promoting layer) 8
It is desirable to add a step of selectively removing only the impurities. Previous
Step of selectively removing a part of the first buried insulating film
As for the first buried insulating film 8 of the lower electrode 4,
It is preferable to remove the upper portion of the portion in contact with the side surface.
The selective removal of a part of the first buried insulating film is described as an example.
For example, it is known for removing particles of metallic elements.
APM (NH _FourOH + H₂O₂+ H₂O), SPM (H₂
SO_Four+ H₂O₂+ H₂O), HPM (HCl + H₂O₂+ H
₂D) Etch with an etching solution such as (O).
And the second embedded insulating film 9 and the lower electrode 4 are dissolved by
Without melting, only the first embedded insulating film 9 is dissolved
Is adopted.

As a result, there is no contact between the capacitive insulating film 5 made of a ferroelectric film and the first buried insulating film (CMP polishing promoting layer) 8, and the ferroelectric property of the first buried insulating film (CMP polishing promoting layer) is reduced. It is possible to completely prevent the influence on the body characteristics. For example, when the first buried insulating film is in contact with the capacitive insulating film made of a ferroelectric film, impurities tend to diffuse into the ferroelectric layer by heat treatment and destroy a part of the crystal structure. When the insulating film containing the metal element is in contact, the tendency may be increased. In addition, when forming a multi-layer structure by depositing crystal layers, it can be generally said that when crystallizing after applying a ferroelectric substance, there is a difference in crystal growth depending on the type of base, so the base type The less the better. From these viewpoints as well, it is preferable that the capacitive insulating film 5 made of a ferroelectric film and the first embedded insulating film (CMP polishing promoting layer) 8 are not in contact with each other (see the second embodiment of FIG. 5). ). In other words, by adopting such an aspect, it becomes possible to select the CMP polishing promoting layer only from the viewpoint of the polishing selectivity (that is, it becomes possible to use a material that affects the ferroelectric film), and it is possible to further select a material. The degree of freedom is improved.

As the lower electrode, it is desirable to use Pt, Ir, Ru, or an alloy film containing them, or a conductive film containing at least part of their oxides.

As a result, it is possible to obtain a ferroelectric memory having a capacitor insulating film 5 made of a ferroelectric film and a stable lower electrode that does not react even when heat-treated at a high temperature, and a manufacturing method thereof.

The material of the upper electrode is not particularly limited, but it is preferable to use the same material as the lower electrode.

As the first buried insulating film (CMP polishing promoting layer), it is preferable to use an insulating layer containing a metal element, for example, titanium oxide, aluminum oxide or titanium aluminum oxide, a metal such as Ti or Al. An insulating layer containing an element as its constituent element is preferably used. That is, it is preferable to use, as the CMP slurry, a material having a composition that is easily polished with respect to a slurry that utilizes chemical reactivity including a chemical solution that promotes a surface reaction.

As the material of the second buried insulating film 9, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is used. That is, the CMP slurry is hardly polished with respect to a slurry that utilizes chemical reactivity including a chemical solution that promotes a surface reaction, and an abrasive containing silica, alumina (Al ₂ O ₃ ) or the like as a main component is used. It is preferable to use a material that can be polished with a CMP slurry that performs CMP using physical polishing power.

As a ferroelectric film used for the capacitance insulating film 5,
Is not particularly limited, but PZT (PbZr
_XTi_(1-X)O₃However, 0 <X <1), SBT (SrBi₂
Ta ₂O₉), SrBi₂(Ta_XNb_(1-X))₂O₉(However,
0 ≦ X ≦ 1) and the like.

At the stage of FIG. 1D, the second buried insulating film is formed.
9 is flattened and the first embedding is performed on the lower electrode 4.
CMP slurry used in the process of exposing the insulating film 8 only
For Lee, the physical polishing power is mainly
An example is a CMP slurry that performs CMP using it.
High-purity fumed silica of about 10-15 wt%
With an aggregate particle size of 100-200 nm
KOH or NH_FourPut in OH (pH around 10)
Used in the state. As other abrasive grains, CeO ₂, Zr
O₂, Mn₂O₃Also used.

The first and second embedded insulating films are polished by the CMP method under the condition that the first embedded insulating film 8 is more easily polished than the second embedded insulating film 9, and the lower electrode is polished. Examples of the CMP slurry used in the step of exposing the surface of No. 4 include slurries that mainly utilize chemical reactivity, including chemicals that accelerate the surface reaction. ,
It is characterized in that it contains an oxidizing agent, and the Al ₂ O ₃ abrasive grains are used in any one of Fe (NO ₃ ) ₂ , H ₂ O ₂ and KIO ₃ (pH 2 to 4). . As abrasive grain, M
nO ₂ and silica are also used.

The material of the interlayer insulating film 7 is not particularly limited, but the conventional lower electrode has a counter electrode area smaller than that of the upper electrode. The material used for the insulating film can be used, and for example, BPSG (SiO ₂ doped with boron and phosphorus), PSG (Si doped with phosphorus)
O ₂ ), SiO _{2 and the} like, and the capacitor interlayer insulating film 10 is not particularly limited, but may be used as a corresponding capacitor interlayer insulating film of a conventional ferroelectric memory having a stack type structure. It is possible to use a material that has a material such as BPSG, PSG, and SiO ₂ .

[0046]

As described above, according to the capacitive element and the method of manufacturing the same of the present invention, the lower electrode and the insulating film can be over-polished without the occurrence of recesses, and polishing residue can be prevented. It is possible to provide a capacitive element that can realize highly reliable ferroelectric capacitor characteristics without variations in characteristics and a manufacturing method thereof. In addition, the second by the CMP method
Of the buried insulating film is flattened, and the first insulating film is formed on the lower electrode.
The step of exposing the first buried insulating film and the step of polishing the first buried insulating film under the condition that the first buried insulating film is more easily polished than the second buried insulating film by the CMP method. However, it is preferable that the polishing including the step of exposing the surface of the lower electrode is divided into two steps and the polishing is performed according to the use, because the occurrence of a global step can be prevented.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view of a method of manufacturing a capacitive element showing an embodiment of the present invention.

FIG. 2 is a process cross-sectional view of a method of manufacturing a capacitive element showing an embodiment of the present invention (continuation of the process of FIG. 1).

FIG. 3 is a cross-sectional view showing an embodiment of a capacitive element of the present invention.

FIG. 4 is a graph showing a relationship between polishing amounts of a first embedded insulating film (CMP polishing promoting layer) and a second embedded insulating film when a W slurry is used.

FIG. 5 is a cross-sectional view showing a modified example of the embodiment of the capacitive element of the present invention.

FIG. 6 is a cross-sectional view showing a method of manufacturing a capacitive element related to a ferroelectric memory of a conventional example.

FIG. 7 is a cross-sectional view showing a method of manufacturing a capacitive element for a ferroelectric memory of a conventional example (sequential to the step of FIG. 6).

[Explanation of symbols]

1 Separation area 2 High concentration impurity diffusion layer 3 contact plugs 4 Lower electrode 5 Capacitance insulating film 6 Upper electrode 7 Interlayer insulation film 8 First buried insulating film (CMP polishing promoting layer) 9 Second embedded insulating film 10 Capacitor interlayer insulation film 11 First conductive film 12 Ferroelectric film 13 Second conductive film 20 Semiconductor substrate 21 Embedded insulating film

Continued front page    (72) Inventor Shinya Natsume             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5F083 FR02 JA15 JA17 JA38 JA39                       JA40 JA43 MA06 MA17 NA01                       NA08 PR40

Claims (10)

[Claims] 1. A lower electrode formed on a semiconductor substrate to serve as a capacitance defining port, a capacitive insulating film formed by covering the lower electrode, and an upper electrode formed by covering the capacitive insulating film. In the capacitive element having, the lower electrode is embedded in a laminated film of first and second embedded insulating films, and the first embedded insulating film is a layer lower than the second embedded insulating film and The capacitor is arranged to be a layer in contact with the side surface of the lower electrode, and the first embedded insulating film is formed of an insulating film that is more easily polished than the second embedded insulating film. element. 2. The capacitive element according to claim 1, wherein the first embedded insulating film is an insulating film containing a metal element. 3. The capacitive element according to claim 1, wherein the lower electrode is formed of Pt, Ir, Ru or an alloy film containing them, or a conductive material containing an oxide thereof. . 4. The first embedded insulating film is an insulating film selected from titanium oxide, aluminum oxide or titanium aluminum oxide, and the second embedded insulating film is selected from a silicon oxide film or a silicon nitride film. The capacitive element according to claim 1, which is an insulating film. 5. A step of forming a lower electrode on a semiconductor substrate, a step of sequentially covering the lower electrode with first and second buried insulating films, and a step of forming the second buried layer by a CMP method. Under the conditions of planarizing the insulating film and exposing the first buried insulating film on the lower electrode, and under the condition that the first buried insulating film is more easily polished than the second buried insulating film by CMP. ,
Polishing the first and second buried insulating films to expose the surface of the lower electrode, forming a capacitive insulating film so as to cover the lower electrode, and covering the capacitive insulating film And a step of forming an upper electrode as described above. 6. A step of selectively removing a part of the first buried insulating film after the step of polishing the first and second buried insulating films to expose the surface of the lower electrode. The method for manufacturing a capacitive element according to claim 5, further comprising: 7. The step of selectively removing a part of the first embedded insulating film is a step of removing at least an upper portion of a portion of the first embedded insulating film in contact with a side surface of the lower electrode. The method for manufacturing a capacitive element according to claim 6. 8. The manufacturing of the capacitor element according to claim 5, wherein the lower electrode is formed of Pt, Ir, Ru or an alloy film containing them, or a conductive material containing an oxide thereof. Method. 9. The method of manufacturing a capacitive element according to claim 5, wherein the first embedded insulating film is an insulating film containing a metal element. 10. The first buried insulating film is an insulating film selected from titanium oxide, aluminum oxide or titanium aluminum aluminum oxide, and the second buried insulating film is selected from a silicon oxide film or a silicon nitride film. It is an insulating film, The manufacturing method of the capacitive element in any one of Claims 5-9.