JP2003229411A - Manufacturing method of thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stabilize the etching speed of a silicon oxide film and eliminate the reduction of an yield due to the remaining etching of the silicon oxide film upon forming a contact hole in the silicon oxide film on a silicon layer, in the manufacturing method of a thin film transistor. <P>SOLUTION: The manufacturing method of the thin film transistor comprises a process of forming the silicon oxide film on an active layer consisting of silicon, and a dry etching process of etching the silicon oxide film employing etching gas consisting of a first gas containing fluorine as well as carbon and second gas containing hydrogen while applying plasma discharge to form the contact hole for exposing part of the active layer in the silicon oxide film. The condition of etching is specified upon starting the plasma discharge in the dry etching process so that the producing amount of fluorocarbon is reduced compared with the stabilizing time of plasma discharge. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art In recent years, in liquid crystal display devices and the like, a thin film transistor using high-mobility polycrystalline silicon as an active layer has been used instead of a transistor using amorphous silicon as an active layer. This thin film transistor is shown in FIG. An active layer 13 made of polycrystalline silicon is formed on the glass substrate 11. The active layer 13 includes source / drain regions 13b and 13d and a channel region 13c. A gate insulating film 14 made of a silicon oxide film is formed on the active layer 13. This gate insulating film 1
4, a gate electrode 15 is formed on a part of the gate electrode 15, and the interlayer insulating film 1 made of a silicon oxide film is formed on the gate electrode 15.
6 is formed. Contact holes are formed in the silicon oxide films 16 and 14 by etching,
The electrode 17 is formed through this contact hole. The active layer 13 is usually formed by forming amorphous silicon on the substrate 11 and then polycrystallizing it by beam annealing. Therefore, the active layer 13 is formed into a thin film having a thickness of about 50 nm so that the beam annealing is easy.

In the formation of the contact hole of the above transistor, since the active layer (polycrystalline silicon layer) 13 made of polycrystalline silicon is a thin film, the etching rate for the insulating films (silicon oxide films) 16 and 14 is high and the active layer is It is necessary to perform selective etching, which has a low etching rate for 13. Dry etching is used for this selective etching. The etching gas is a gas containing carbon and fluorine (CHF ₃ , C
₄ F ₈ , C ₂ HF ₅ , etc.) and H ₂ mixed gas is used. When these gases are used, the reaction proceeds due to a competitive reaction between etching by the fluorine ions generated by plasma and deposition by the carbon-based polymer film. Here, during the etching of the silicon oxide films 16 and 14, most of the carbon-based polymerized film is combined with oxygen and becomes a gas such as carbon dioxide due to the supply of oxygen from the film. For this reason, the deposition is unlikely to proceed and the etching rate is increased. On the other hand, while the silicon of the polycrystalline silicon layer 13 is being etched, since the oxygen is not supplied from the film, the carbon-based polymer film is deposited as it is. Therefore, the deposition becomes dominant and the etching rate becomes slow. In this way, selective etching is performed in which the etching rate for the active layer 13 is slow and the etching rate for the silicon oxide films 16 and 14 is fast.

[0004]

However, the above-mentioned method using selective etching has a problem that the contact resistance varies greatly, the contact resistance increases, and the yield of thin film transistors decreases. Then, according to the experiment by the present inventor, the decrease in the yield was large, especially when a large substrate was used. That is, according to an experiment by the present inventor, for example, 400 mm ×
When a large substrate of about 500 mm was used, the contact resistance between the electrode 17 and the active layer 13 was likely to increase.

While investigating the cause of such an increase in the contact resistance of the thin film transistor, the present inventor found that the etching rate became unstable when the contact holes were formed in the silicon oxide films 16 and 14 by dry etching. It is also known that the in-plane distribution of the etching rate may become large. Further, it was found that the etching residue of the silicon oxide films 16 and 14 was generated in the portion where the etching rate was low, which increased the contact resistance.

Therefore, the present inventor repeated various experiments in order to elucidate the reason why the etching rate becomes unstable as described above. As a result, the inventors have independently found that if the time until the plasma discharge stabilizes in the initial stage of dry etching becomes long, the above etching residue is likely to occur.

However, it is actually extremely difficult to make the time from the start of plasma discharge to the stabilization stable for each discharge and to completely eliminate the in-plane distribution. That is, there are various causes that contribute to the time required for starting the discharge and stabilizing the discharge, and all of them cannot be artificially controlled. For example, in the dry etching process, a matching circuit that adjusts the impedance of the supplied RF power and plasma is provided, but the mechanical variable capacitor or variable inductor used in this matching circuit has mechanical play. Therefore, the above impetence cannot be perfectly matched. For this reason, for example, the time from the start of plasma discharge to the stabilization cannot be constant.

The present invention has been made on the basis of the recognition of the above-mentioned problems, and its purpose is to prevent the insulating film 1 from irrespective of the time from the start of plasma discharge to the stabilization, which is extremely difficult to control.
It is intended to stabilize the etching rates of Nos. 6 and 14 and to eliminate the decrease in yield due to the remaining insulating film.

[0009]

A method of manufacturing a transistor according to the present invention comprises a step of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, and a second gas containing hydrogen. And a dry etching step of forming a contact hole that exposes a part of the active layer in the silicon oxide film by using plasma discharge with the gas of FIG. , The ratio of the flow rate of the first gas at the start of plasma discharge divided by the flow rate of the second gas,
It is characterized in that the flow rate of the first gas when the plasma discharge is stable is made larger than the ratio obtained by dividing the flow rate of the second gas.

Further, the method of manufacturing a transistor of the present invention comprises a step of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, a second gas containing hydrogen, As an etching gas, plasma discharge is used to etch the silicon oxide film,
A dry etching step of forming a contact hole exposing a part of the active layer in the silicon oxide film, the total flow rate of the etching gas at the time of plasma discharge start in the dry etching step, The total flow rate of the etching gas is less than the total flow rate.

In addition to the first gas and the second gas, an inert gas such as argon may be used as the diluent gas. In this case, the diluent gas is not included in the etching gas.

Further, the method for manufacturing a transistor of the present invention comprises a step of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, and a second gas containing hydrogen. As an etching gas, plasma discharge is used to etch the silicon oxide film,
A dry etching step of forming a contact hole in the silicon oxide film to expose a part of the active layer, and the pressure at the start of plasma discharge in the dry etching step is made lower than the pressure at the time of stable plasma discharge. It is characterized by

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The present embodiment relates to a method of manufacturing a thin film transistor used for a switching element of a flat panel display device such as a liquid crystal display device. One of the features of the transistor manufacturing method of the present embodiment is that, in the step of forming a contact hole in a silicon oxide film by dry etching, the etching condition at the start of plasma discharge is set so that the amount of fluorocarbon produced is greater than that at the stable plasma discharge. The point is that the etching conditions are reduced. In this embodiment, this makes it possible to prevent an increase in contact resistance and increase the yield. Hereinafter, three examples will be specifically described.

(First Embodiment) FIGS. 1 (a) to 1 (d) and FIG.
(a)-(d) is a figure which shows the manufacturing method of the thin-film transistor of the 1st Embodiment of this invention. One of the features of the method of manufacturing the thin film transistor of the present embodiment is that the dry etching process of the silicon oxide films (insulating films) 4 and 6 is focused as shown in FIG. Before describing the etching process in detail, first, the entire method of manufacturing a transistor will be briefly described with reference to FIGS. 1 and 2. In this manufacturing method, 400 mm ×
Many thin film transistors are manufactured on a large substrate of 500 mm, and FIGS. 1 and 2 are enlarged cross-sectional views of one of the thin film transistors.

(1) First, as shown in FIG. 1A, an amorphous semiconductor thin film 2 is deposited on an insulating substrate 1. The amorphous semiconductor thin film 2 has a thickness of 50 nm.

(2) Next, as shown in FIG. 1 (b), the amorphous semiconductor thin film 2 is melted and crystallized by irradiating it with an energy beam such as excimer laser light to obtain a polycrystalline thin film 3a.

(3) Next, as shown in FIG. 1C, the polycrystalline thin film 3a is patterned to obtain an active layer (polycrystalline silicon layer) 3.

(4) Next, as shown in FIG. 1D, a gate insulating film (silicon oxide film) 4 is deposited.

(5) Next, a metal layer is formed on the gate insulating film 4 and, as shown in FIG. 2A, this is patterned to form the gate electrode 5. Then, using the gate electrode 5 as a mask, p-type or n-type impurities are implanted into the active layer 3 at a high concentration to form a central channel region 3c and source / drain regions 3b and 3d on both sides thereof.

(6) Next, after annealing is performed to activate the impurities, an interlayer insulating film (silicon oxide film) 6 is formed as shown in FIG. 2 (b). Then, a resist R having an opening H having a predetermined shape is formed on the interlayer insulating film 6.

(7) Next, as shown in FIG. 2 (c), a first gas containing fluorine and carbon and a second gas containing hydrogen are used as etching gases by using plasma discharge,
The silicon oxide films 4 and 6 are dry-etched through the openings H. In this embodiment, C ₂ HF ₅ containing carbon and fluorine was used as the first gas, and H ₂ was used as the second gas. Using this etching gas, the silicon oxide films 4 and 6,
Under the condition that the etching selection ratio of the active layer 3 is high,
Perform dry etching. Then, by this dry etching, a contact hole CH exposing a part of the active layer 3 is formed in the silicon oxide films 4 and 6.

(8) Next, the resist R is removed, and FIG.
As shown in (d), the source / drain electrodes 7 are formed so as to be in contact with the active layer 3 through the contact holes CH,
The transistor is completed.

In the method of manufacturing a thin film transistor described above, dry etching is used to form the contact holes CH in the silicon oxide films 4 and 6 as shown in FIG. 2 (c). The present embodiment focuses on this dry etching method. Therefore, a method of manufacturing the contact hole CH by this dry etching will be described in detail below.

FIG. 3 is a schematic view of a dry etching apparatus used for forming the contact hole CH of the transistor of this embodiment. Further, FIG. 4 is a diagram showing a sequence at the time of forming the contact hole CH of the transistor of this embodiment. A method of manufacturing the contact hole of the transistor of this embodiment will be described below with reference to FIGS.

(1) First, the substrate 1 is set on the substrate stage 12 of the reaction container 11 of the inductively coupled RIE apparatus shown in FIG. 3 and evacuated to vacuum.

(2) Next, C ₂ HF ₅ as the first etching gas and H 2 as the second etching gas
₂ and ₂ are introduced into the chamber from the gas nozzle 13 (t ₁ ). Here, the flow rate of H ₂ is 70 sccm, which is lower than that at the time of stable plasma discharge (t ₄ ) (FIG. 4C).
t _{1 to} t ₂ ). The flow rate of C ₂ HF ₅ is 100 sccm, which is higher than that at the time of stable plasma discharge (t ₄ ) (FIG. 4).
_{(d), t 1 ~t 2} ).

(3) Next, the pressure control valve 14 provided at the exhaust port 14 with the gas flowing.
By adjusting A, the pressure in the reaction vessel is adjusted to 12 mTorr (FIG. 4 (a) t _{1 to} t ₂ ).

(4) Next, from the coil power supply 15 to the coil 1
RF power is applied to 6 to generate plasma in the reaction container through the dielectric window 17 (FIG. 4 (b), t ₂ ). At the same time, RF power is also applied from the bias power supply 18. R
The power of the F power is 0.
9 W / cm ³ . This state is maintained for 3 seconds, and during this period, the matching circuit 19 is adjusted so that 95% or more of the applied RF power is consumed by the plasma. As described above, the time from the adjustment of the matching circuit 19 to the stabilization of the plasma discharge is not constant.

(5) Next, after the discharge is stabilized, the flow rate of C ₂ HF ₅ is reduced to 80 sccm and the flow rate of H ₂ is 90 sccc while keeping the total gas flow rate at 170 sccm.
increase to m (t ₃ ). In this state, H ₂ / (C
₂ HF ₅ + H ₂ ) = 0.53. Thus, H ₂
Assuming that / (C ₂ HF ₅ + H ₂ ) = 0.53, as shown in FIG. 5, the etching rate of the active layer (polycrystalline silicon layer) 3 (FIG. 5B) is different from that of the silicon oxide film 4. , 6 the etching rate (FIG. 5 (a)) increases, and the etching selection ratio increases.

(6) Next, in the state where the selection ratio is high, the discharge is continued until the predetermined contact hole CH is formed (t ₄ ).

(7) Next, the RF power and the etching gas are stopped, and the etching is completed (t ₅ ).

In the method of manufacturing the contact hole CH of the transistor of the present embodiment described above, as described above,
The ratio of C ₂ HF ₅ / H ₂ at the time of stable plasma discharge (t ₄ ) is set as the condition that the etching selectivity becomes high.
Further, in the present embodiment, as can be seen from FIG. 4C and FIG. 4D, C ₂ HF at the start of plasma discharge (t ₂ ).
The ratio of ₅ / H ₂ is defined as C when the plasma discharge is stable (t ₄ ).
It is made larger than the ratio of ₂ HF ₅ / H ₂ . That is, the flow rate of C ₂ HF ₅ (first gas containing carbon and hydrogen) at the start of plasma discharge (t ₂ ) is set to H ₂ ( _second gas containing hydrogen).
The ratio of the gas divided by the flow rate of the
_It is larger than the ratio in ₄ ). By doing so, it is possible to prevent generation of etching residue of the silicon oxide films 4 and 6. The reason for this is when the plasma discharge starts
It is analyzed that even if the time from (t ₂ ) to the stabilization of the plasma discharge becomes long, the amount of fluorocarbon generated in the initial stage of the plasma discharge can be reduced. Hereinafter, this will be described with reference to FIG. 7 in comparison with FIG. 6 showing a sequence of another manufacturing method of the present inventor.

FIG. 6 is a sequence chart of another manufacturing method of the present inventor.
FIG. In the manufacturing method of FIG.
When electricity is stable (t_FourH in ’)_TwoFlow rate (Fig. 6 (c)) and
And C _TwoHF₅Flow rate (Figure 6 (d))
90sccm and 80sc for higher
cm, at the start of plasma discharge (t_Two’) Has the same flow rate
ing.

In the sequence of FIG. 4 and the sequence of FIG. 6, as described above, at the start of plasma discharge (t ₂ , t
It is actually extremely difficult to make the time from ₂ ') to the plasma discharge stable completely constant for each discharge and to completely eliminate the in-plane distribution. This is because there are various causes that contribute to the time required for starting discharge and stabilizing the discharge, and all of them cannot be artificially controlled. Therefore, in the initial etching process (t ₂ , t ₂ ′),
The time when the RF power is low increases or decreases with each discharge. However, with the silicon oxide films 4 and 6,
If the RF power is lowered under the condition that the selection ratio is high, the deposition reaction is likely to occur and the fluorocarbon is deposited on the silicon oxide films 4 and 6. This can be understood from the data of FIG. 7, for example. That is, FIG. 7 corresponds to FIG.
When the plasma discharge is stable in the sequence of FIG. 6 (t ₄ , t ₄ ′)
FIG. 6 is a diagram showing a change in etching rate when the coil RF power is changed under the condition of FIG. As shown in FIG. 7, when the coil RF power is lowered, the etching rate of the silicon oxide films 4 and 6 (FIG. 7A) is different from the etching rate of the polycrystalline silicon layer 3 (FIG. 7B). Falls sharply. This is because in the silicon oxide films 4 and 6, the amount of fluorocarbon deposition increases as the RF power decreases. This Figure 7
As can be seen from the above, in the silicon oxide films 4 and 6, if the RF power is lowered under the condition that the selection ratio is high, the fluorocarbon deposition reaction is likely to occur. Therefore, in the sequence of FIG. 6, which is a condition that the selection ratio is high even in the initial etching process (t ₂ ′), the initial etching process
When the RF power is low for a long time at (t ₂ ′), fluorocarbon is deposited on the silicon oxide film 6. And, due to this fluorocarbon, when the discharge is stable (t ₄ ')
The etching of the silicon oxide films 6 and 4 does not proceed,
Etching residue occurs. On the other hand, in the sequence of FIG. 4, C at the start of plasma discharge (t ₂ ).
The ₂ HF ₅ / _{H 2} ratio is made larger than the ratio of _{C 2 HF} 5 / _H 2 at the time of plasma discharge stability _{(t 4).} As described above, under the condition that the ratio of C ₂ HF ₅ / H ₂ is large, even if the coil RF power of the plasma discharge becomes low, the fluorocarbon does not easily deposit. That is, in the sequence of FIG.
When plasma discharge starts rather than when plasma discharge is stable (t ₄ ).
(t ₂ ) is a condition in which the deposition of fluorocarbon is small. Therefore, in the sequence shown in FIG. 4, the amount of fluorocarbon deposited on the silicon oxide film 6 can be suppressed even if the RF power is low for a long time in the initial stage of plasma discharge (t ₂ ).

As described above, the sequence shown in FIG.
At the start of plasma discharge (t _Two’)
The coil RF power is low because the time until electrical stabilization is unstable
Reduces the amount of fluorocarbon deposited even when the time becomes long
be able to. As a result, in this embodiment, the control
The time from the start of a difficult and difficult plasma discharge to its stabilization
First, stabilize the etching rate of the silicon oxide film,
The yield will not decrease due to the etching residue of the conoxide film.
Can be smoldered.

In the manufacturing method of the sequence of FIG. 4 explained above, the occurrence of etching residue was almost 0%. On the other hand, in the manufacturing method of the sequence of FIG. 6, etching residue was generated in about 23% of the processed substrate.

(Second Embodiment) In the method of manufacturing a thin film transistor according to the second embodiment, as can be seen from FIG. 8, the first sequence is the sequence when the contact hole CH is formed (FIG. 2C). (FIG. 4). Other manufacturing methods are the same as those in the first embodiment, and detailed description thereof will be omitted.

FIG. 8 is a diagram showing a sequence at the time of forming the contact hole CH of the thin film transistor according to the second embodiment of the present invention. The flow rate of H ₂ at the start of plasma discharge (t ₂ ) and the flow rate of C ₂ HF ₅ are 67.5, respectively.
sccm (FIG. 8 (c)), 60 sccm (FIG. 8 (d)),
Is. After the plasma discharge _stability, while maintaining a ratio of C ₂ HF 5 / _{H 2,} the flow rate of _{H 2} to 90 _sccm, C 2 HF
₅ flow rate up to 80 sccm (t
₃ ).

As described above, in the second embodiment,
At the start of plasma discharge (t_Two) C_TwoHF ₅And H_TwoTotal flow with
When the plasma discharge is stable (t_Four) C_TwoHF₅And H_Two
And less than the total flow rate. Do this
When the plasma discharge is stable, as in the first embodiment.
(t_Four), At the start of plasma discharge (t_Two) Is better
It is a condition that there is little deposition of carbon dioxide. This conclusion
As a result, the second embodiment is similar to the first embodiment.
Moreover, it is stable from the start of plasma discharge, which is extremely difficult to control.
The etching rate of the silicon oxide film, regardless of the
Stabilization and yield due to etching residue of silicon oxide film
It is possible to eliminate the deterioration of the ball.

(Third Embodiment) In the method of manufacturing a thin film transistor according to the third embodiment, as can be seen from FIG. 9, the sequence of forming the contact hole CH (FIG. 2C) is first performed. (FIG. 4). Other manufacturing methods are the same as those in the first embodiment, and detailed description thereof will be omitted.

FIG. 9 is a diagram showing a sequence at the time of forming the contact hole CH of the thin film transistor according to the third embodiment of the present invention. The pressure at the start of plasma discharge (t ₂ ) is 8 mTorr (FIG. 9A). After the plasma discharge is stabilized, this pressure is increased to 12 mTorr (FIG. 9A, t ₃ ).

As described above, in the third embodiment, the pressure at the start of plasma discharge (t ₂ ) is set lower than the pressure at the time of stable plasma discharge (t ₄ ). In this way, when the plasma discharge is stable, as in the first embodiment.
The condition is that the deposition of fluorocarbon is smaller at the start of plasma discharge (t ₂ ) than at (t ₄ ). As a result, in the third embodiment, as in the first embodiment, the etching rate of the silicon oxide film is stabilized regardless of the time from the start of plasma discharge to the stabilization, which is extremely difficult to control, and the silicon oxide film is stabilized. It is possible to eliminate a decrease in yield due to etching residue of the oxide film.

In the manufacturing method of FIG. 9 described above, the pressure at the start of plasma discharge (t ₂ ) is set to 8 mTorr and the pressure at the time of plasma discharge stabilization (t ₄ ) is set to 12 mTorr, but other values may be used. Is also possible. For example, if the pressure at the start of plasma discharge (t ₂ ) is 6 to 8 mTorr and the pressure at the time of stable plasma discharge (t ₄ ) is 12 to 15 mTorr, the effect of this embodiment can be easily obtained.

In the above-described embodiment of the present invention, the etching condition at the start of plasma discharge in the dry etching process is set so that the production amount of fluorocarbon is smaller than that at the time of stable plasma discharge. This is normal two-step etching, that is, the first etching in which the etching rate is increased by ignoring the selection ratio,
This is a method different from the second etching in which the etching rate is ignored and the selection ratio is increased, and the two-step etching. That is, the manufacturing method of the present embodiment is the same as the above-described two-step etching in that the second-step etching is an etching with a high selection ratio, but the first-step etching is not a condition that the etching rate is high. The conditions are such that the amount of fluorocarbon deposited is reduced.

Further, in the embodiment described above, in the dry etching process, the etching condition at the time of starting the plasma discharge is set so that the production amount of fluorocarbon is smaller than that at the time of stable plasma discharge. Specifically, in the first embodiment, the ratio of the flow rate of C ₂ HF ₅ (first gas) at the start of plasma discharge divided by the flow rate of H ₂ (second gas) is the plasma discharge stabilization. Greater than the ratio at time. In addition, in the second embodiment, the total flow rate of etching gas at the start of plasma discharge is set to be lower than the total flow rate of etching gas at the time of stable plasma discharge. Further, in the third embodiment, the pressure at the start of plasma discharge is set lower than the pressure at the time of stable plasma discharge. As described above, in each embodiment, the flow rate ratio, the total flow rate, and the pressure are changed separately, but it is also possible to change at least two of the flow rate ratio, the total flow rate, and the pressure by appropriately combining them. is there.

The method of the above-described embodiment is
This is particularly effective when the active layer 3 made of polycrystalline silicon is a thin film having a thickness of 100 nm or less. That is, when the active layer 3 is a thin film, it is necessary to particularly increase the selection ratio between the active layer 3 and the silicon oxide films 4 and 6. Then, using the condition of increasing the selection ratio, as described above, the silicon oxide film 4,
The etching rate of 6 becomes unstable. Therefore, the present invention is particularly effective when the active layer 3 is a thin film having a thickness of 100 nm or less.

In the embodiment described above, C ₂ HF is used as the first gas containing fluorine and carbon in the dry etching process for forming the contact hole CH.
₅ was used, but instead of this, another HF such as CHF ₃ was used.
It is also possible to use a C-type gas. In addition, C ₄ F ₈ and C
Gases of PFCs such as ₃ F ₆ can also be used.

[0048]

According to the method of manufacturing a thin film transistor of the present invention, in the dry etching step of forming a contact hole in a silicon oxide film on a silicon layer by using plasma discharge, the etching conditions at the start of plasma discharge are Since the etching conditions are such that the amount of fluorocarbon produced is smaller than that in the stable state, it is possible to prevent a decrease in yield due to etching residue.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall method of manufacturing a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the entire method of manufacturing the thin film transistor according to the first embodiment of the present invention, which is a diagram subsequent to FIG.

FIG. 3 is a diagram showing an outline of a dry etching apparatus used for forming a contact hole of the thin film transistor according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a sequence of forming a contact hole in the method of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between a flow rate ratio of an etching gas and an etching rate in a dry etching process for forming a contact hole.

FIG. 6 is a diagram showing a sequence of forming a contact hole in another thin film transistor manufacturing method of the present inventor.

FIG. 7 is a diagram showing a relationship between a coil RF power and an etching rate in a dry etching process for forming a contact hole.

FIG. 8 is a view showing a sequence at the time of forming a contact hole in the method of manufacturing the thin film transistor according to the second embodiment of the present invention.

FIG. 9 is a diagram showing a sequence at the time of forming a contact hole in the method of manufacturing the thin film transistor according to the third embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a polycrystalline silicon thin film transistor.

[Explanation of symbols]

1 substrate 3 Active layer (semiconductor thin film) 4 Gate insulating film (silicon oxide film) 6 Interlayer insulation film (silicon oxide film) CH contact hole

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akihiro Takami             2 shares, 1-9-1 Harara-cho, Fukaya City, Saitama Prefecture             Company Toshiba Fukaya Factory F-term (reference) 2H092 JA25 JA34 JA37 JA46 JB57                       KA04 KA12 KB25 MA13 MA18                       NA29                 5F004 AA05 BA20 CA02 CA07 CA08                       DA00 DA16 DA24 DA30 DB03                       EA28 EB01 EB03                 5F110 BB01 CC02 FF02 GG02 GG13                       GG25 HJ23 HL14 PP03 QQ04                       QQ11

Claims (4)

[Claims] 1. A plasma discharge using a step of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, and a second gas containing hydrogen as etching gases. And a dry etching step of etching the silicon oxide film to form a contact hole exposing a part of the active layer in the silicon oxide film, the flow rate of the first gas at the start of plasma discharge. Is larger than the ratio obtained by dividing the flow rate of the first gas by the flow rate of the second gas when the plasma discharge is stable. Method. 2. A plasma discharge using a step of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, and a second gas containing hydrogen as etching gases. A dry etching step of etching the silicon oxide film to form a contact hole exposing a part of the active layer in the silicon oxide film, the etching at the time of starting plasma discharge in the dry etching step. A method of manufacturing a thin film transistor, characterized in that the total flow rate of the gas is made lower than the total flow rate of the etching gas when the plasma discharge is stable. 3. A process of forming a silicon oxide film on an active layer made of silicon, a first gas containing fluorine and carbon, and a second gas containing hydrogen are used as etching gases, and plasma discharge is used. And a dry etching step of etching the silicon oxide film to form a contact hole exposing a part of the active layer in the silicon oxide film, the pressure at the start of plasma discharge in the dry etching step. A method of manufacturing a thin film transistor, which is characterized in that the pressure is lower than the pressure when the plasma discharge is stable. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the active layer is a thin film having a film thickness of 100 nm or less.