JP2003229366A - Semiconductor laminated structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a half-insulative compound semiconductor layer having a resistivity of 1×10<SP>7</SP>Ω.cm or larger in a semiconductor laminated structure that is formed by performing the epitaxy growth of compound semiconductors on an Si wafer. <P>SOLUTION: The semiconductor laminated structure including impurities 16, where a group III-V compound crystal layer 17 is one or a plurality of Fe (iron), Cr (chromium), Mn (manganese), V (vanadium), C (carbon), O (oxygen) or B (boron). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laminated structure in which an insulating or semi-insulating group III-V semiconductor crystal layer is formed and installed on a Si substrate by epitaxy and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, gallium arsenide (G) is formed on a Si substrate.
aAs) and indium phosphide (InP)
Investigations for forming III-V group compound semiconductors have been conducted in various research institutions. GaAs substrate and InP
Compound semiconductors such as substrates are faster and have higher power efficiency than devices formed on substrates made of only Si.
In addition, it has properties very suitable for forming high-performance electronic devices and light-emitting devices with less noise.

However, it is very difficult to manufacture a single crystal ingot of a size necessary for forming a large-sized substrate exceeding 6 inches, and its manufacturing cost is several times or more that of Si. Therefore, it is very difficult to manufacture a device with high cost for Si.

By the way, an attempt is made to form a compound semiconductor substrate by a method different from the most common method for producing a substrate, namely, "a method for producing a compound semiconductor single crystal ingot and then slicing this to obtain a compound semiconductor substrate wafer". There is an attempt to do. That is, a compound semiconductor crystal layer such as GaAs having a sufficient thickness is epitaxially grown on a large-area and low-cost Si substrate, and only the surface portion of each wafer is used as a compound semiconductor crystal layer. Is a method of realizing. For example, the compound semiconductor is G
In the case of aAs, this is “GaAs on Si
(Garihiso on silicon) technology ", and the substrate prepared by the method is called" GaAs on Si (Garihiso on silicon) substrate ". If this technique is used and the properties of the compound semiconductor layer are equivalent to those of a substrate prepared by cutting out a single crystal ingot of a bulk compound semiconductor, a significant cost reduction can be achieved as a method for manufacturing a large area compound semiconductor substrate. It is expected to be possible. It is also expected that it will be possible to form a high-performance element that could not be achieved by an element formed on a substrate made of only Si.

In the case of manufacturing an element based on a Si semiconductor on a Si substrate, a Si layer having a high insulating property of 1 × 10 ⁷ Ωcm or more is obtained without adding p-type or n-type impurities. Is impossible to obtain. Further, it is impossible to form an element represented by a transistor, a diode, a capacitor, an inductor, a resistor, a wiring, or the like thereon without performing individual element isolation. This is because the intrinsic carrier concentration in the Si crystal is about 1.5 × 10 ¹⁵ / cm ³ at room temperature, and as a result, the intrinsic resistivity is 2.5 × 10 ³ Ωcm without adding impurities and the current is This is because it is relatively easy to flow. Therefore, element isolation is incomplete without taking any measures, parasitic resistance occurs, and parasitic elements are also formed.

Therefore, when an element using a Si semiconductor is to be formed on a substrate having a high insulating property, SiO is formed in a portion having a depth of several tens nm or more from the surface of the Si substrate on which the element is formed.
Installation of an insulator layer consisting of _two is under way. In order to realize this, for example, a large amount of oxygen is ion-implanted at a certain depth in the Si substrate, and this is annealed at a high temperature to form a SiO ₂ layer at a certain depth from the surface of the Si substrate. Then, there is a method of forming a Si / SiO ₂ / Si laminated structure substrate. There is also a method of forming a Si / SiO ₂ / Si laminated structure substrate by bonding an extremely thin conductive Si substrate onto a Si substrate having SiO ₂ formed on its surface. SOI (Silicon on Insulato)
r) Called the substrate. In this SOI substrate, it is possible to facilitate element isolation by utilizing a high resistance layer made of SiO ₂ and reduce the parasitic capacitance with the substrate side in an electronic circuit that operates at high speed. It is possible to realize a power circuit.

[0007]

However, the following problems also exist in these laminated structures.

First, the manufacturing cost of an SOI substrate is very high due to its special manufacturing method.
When the SI is formed, its manufacturing cost becomes too high as compared with the circuit made using the conventional Si substrate.
As a result, it was not possible to make products with market competitiveness. In addition, its performance is also from the viewpoint of high integration,
For applications such as high speed and high efficiency, GaA
The cost performance with the device formed on the compound semiconductor substrate such as s was not reached.

In a "laminated substrate formed by epitaxially growing a compound semiconductor on a Si substrate" typified by, for example, GaAs on silicon, it occurs between a compound semiconductor layer such as a GaAs layer and a Si substrate. Due to the occurrence of defects and strain, the crystallinity of the formed compound semiconductor layer is
It was still insufficient to form a high performance device.
This is not limited to GaAs, but InP, GaP, InG
The same applies to other compound semiconductors such as aAs. Strains and defects generated at this time are not only strains caused by the difference in lattice constant between Si crystal and GaAs crystal, but also defects such as point defects, line defects, and stacking faults. Strains and defects caused by the difference in expansion coefficient. Furthermore, there is also a phase defect (anti-phase) caused by epitaxially growing GaAs, which is a polar crystal, on a non-polar Si crystal and laminating it. When elements such as light emitting elements, electronic elements, resistors, inductors, capacitors, and wirings are formed on a GaAs layer containing a large amount of these defects and strains, the performance of each individual device is
It is significantly inferior to that on a substrate produced by cutting out from s crystal. In addition, the time-dependent deterioration caused by the operation of the device
The reliability of the device cannot be sufficiently obtained earlier than that of the bulk. Therefore, the study of "a substrate formed by epitaxially growing a compound semiconductor on a Si substrate" such as GaAs-on-silicon has been conducted with great attention paid to the formation of crystals with high crystallinity and few defects and distortions. I've been told. The formation of an element having high performance on the GaAs-on-silicon substrate has been the object of many studies. As a result, the GaAs layer formed by epitaxy on the GaAs-on-silicon substrate is either undoped or n-type or p-type doped with impurities, and its resistivity is 1 × 10 ³ Ωcm or less. It had a relatively low resistance.

The undoped GaAs crystal originally has a very high resistivity, and its intrinsic resistivity is considered to be close to 1 × 10 ⁶ Ωcm. However, in a thin film GaAs layer that is epitaxially grown and laminated on some substrate, carriers are generated due to impurities, strains, and defects mixed in during the growth, and even if it is an undoped crystal layer in which no impurities are intentionally added. Regardless, the resistivity is 1 × 10 ⁵ Ω
(Sulfur S or carbon C adhering to the jig used for crystal growth, or carbon S supplied from air or silicon S emitted from the jig itself such as quartz as impurities.
i etc.). This undoped epitaxially grown GaA
When a transistor is formed on the s crystal layer, electrical isolation between adjacent elements is not sufficiently achieved. As a result, an unintended leak current is generated, which significantly increases the power consumption of the device. As a result, work efficiency with respect to the input electric power is significantly reduced. In addition, parasitic capacitance is generated in various parts and they are charged when the device is in operation, so that the speed of the device is significantly reduced. In addition, there is a problem that unintended circuit connection occurs due to the occurrence of such leakage and parasitic capacitance, and the initially intended operation cannot be performed stably and correctly. These are not limited to GaAs, and other compound semiconductors can be used as Si.
The same applies when the film is formed by epitaxy growth on any substrate including the substrate and its compound semiconductor itself.

The crystal systems of GaAs crystal and Si crystal are very similar between the zinc blende type and the diamond type, but the difference in lattice constant (lattice mismatch rate) is as large as about 4%. Also Ga
The linear thermal expansion coefficient of As is 5.5 × 10 ⁻⁶ , while Si
Has a coefficient of linear thermal expansion of 2.33 × 10 ⁻⁶ . In addition, the Si crystal is a crystal composed of only Si element, and there is no bias in the charge between adjacent atoms, whereas in the GaAs crystal, the distribution of the electrons is biased toward As rather than Ga. As a result, in the GaAs crystal, Ga and As are alternately arranged to form a crystal. In other words, in the GaAs crystal of zinc blende, if the (001) plane is a horizontal plane and Ga is arranged first, a plane composed of As is always stacked immediately above that plane. Then, a layer made of Ga is laminated thereon, and crystals are formed in a form in which Ga and As are alternately laminated endlessly. When such a GaAs crystal is laminated on the (001) plane of Si having a diamond structure, Ga is formed at the interface with Si.
There are two cases, one is a layer consisting only of A and the other is a layer consisting only of As. That is, when a Ga raw material and an As raw material are simultaneously supplied onto the Si (001) surface, a portion where Ga contacts Si and an As
Is distributed two-dimensionally in two cases. As a result, when the thickness of the GaAs layer was increased, the crystal part that started when Ga contacted Si and A
The two domains of the crystal part starting from s in contact with Si become a kind of polycrystalline state in which the two domains are distributed in the spots. Therefore, a crystal grain boundary is generated at the boundary of those crystal grains. This is called a phase boundary or antiphase. Each area divided by this antiphase is called an antiphase domain. The antiphase is a defect because the atoms in the crystal are displaced from the original arrangement. That is, in GaAs arranged on Si, a large number of defects due to antiphase will be introduced. Also G
There is also a method in which the raw material a and the raw material As are not simultaneously supplied, but either one is supplied first, and then the respective raw materials are alternately supplied so that the antiphase is not generated. However, even in this case, it is difficult because the outermost surface of the Si crystal is not a perfectly smooth surface. For example, even if the surface just above the Si outermost surface starts only with As, due to the step difference of one atom that is two-dimensionally distributed on the outermost Si surface, the arrangement order of the atoms is also deviated and the antiphase occurs.

In the attempts of GaAs on silicon performed so far, for example, the following is performed to suppress the occurrence of antiphase. That is, a substrate called an "off substrate" is used in which the Si substrate is tilted several degrees from the (001) plane. This makes it possible to align the steps generated on the Si substrate. For example, when the off angle is set to 2 to 5 degrees, steps of two layers of Si atoms will appear evenly on the Si substrate (the appearing interval changes depending on the angle). As a result, most of the steps generated on the Si surface, which have been generated in various ways, can be converted into steps corresponding to two atomic layers. In this state, either Ga or As is first supplied to coat the Si outermost surface with the atoms, and if a film is formed, a crystal lattice formed by alternately superposing two atomic species of Ga and As is formed. The same repetition will occur regardless of the step, and as a result, the antiphase will not occur.

By the way, if it is possible to propagate the lattice information of the Si crystal to the compound semiconductor layer between the compound semiconductor layer such as a GaAs layer epitaxially grown on the Si substrate and the Si substrate, the compound in question can be transmitted. Even semiconductors are Si
Nonetheless, a layer of another substance may be inserted.
This insertion of another layer may cause a bad influence that causes defects and strains such as a difference in lattice constant and a coefficient of thermal expansion between the compound semiconductor layer and the Si substrate, or polarity and surface roughness. One or several can be mitigated or their effects reduced. As a result, the compound semiconductor layer having no anti-phase can be provided above the Si substrate without providing the off-angle with respect to the (001) plane of the Si substrate surface. This is because the Si-side interface and the open-side surface of the inserted layer are automatically determined, and even if the repeating order of atoms generated due to the step generated by the roughness of the Si surface at the Si-side interface is deviated. The reason is that the anti-phase is eliminated while the insertion layer is being formed. The layer inserted for such a purpose is generally called a buffer layer. In addition, SrTiO ₃ , BaSrTiO ₃ , BiTiO _{3 and the} like are known as substances that form a buffer layer in a compound semiconductor laminated substrate on a Si substrate. An example of this technique is European Patent Publication “EP1043426A1” issued from Motorola.

In the case of a substrate formed by cutting a bulk compound semiconductor single crystal, it has been intentionally made to have a high resistance in order to solve this problem. There are several ways to do that. As one of them, for example, when GaAs is considered as a compound semiconductor, different elements are added as impurities when forming a GaAs single crystal from a melted GaAs material. Unlike the impurities that reduce the resistance to p-type or n-type, this impurity acts to increase the resistivity of the GaAs crystal. The impurities include, for example, oxygen (O) and chromium (Cr). These impurities are GaA
Unlike impurities that change s to p-type or n-type, it has a function of forming a deep energy level of about several hundred meV in the forbidden band of a GaAs crystal and trapping carriers such as electrons and holes to immobilize it. . That is, O and Cr compensate for impurities such as C and Si that promote resistance reduction. As a result, the resistivity of the GaAs crystal is increased and the semi-insulating property of 1 × 10 ⁷ Ωcm or more can be obtained. In addition to the method of adding such impurities, there is a method of forming a semi-insulating GaAs crystal. LEC which is a typical example
In an undoped GaAs single crystal formed by the (Liquid Encapsulated CZ) method, a semi-insulating property is achieved by covering a GaAs melt with a cap made of boron oxide (B ₂ O ₃ ) that withstands high temperature and pulling it up. ing. Although the principle has not been completely clarified yet, a deep level called EL2, which is considered to be generated in relation to excess As in GaAs, compensates for impurities such as C and Si to reach 1 × 10 ⁸ Ωcm. It is considered that the resistance is increased as described above.

An object of the present invention is to realize a semi-insulating compound semiconductor layer having a high resistivity of 1 × 10 ⁷ Ωcm or more in a semiconductor laminated structure formed by epitaxially growing a compound semiconductor on a Si substrate. This makes it possible to perform sufficient element isolation among a plurality of devices formed on this compound semiconductor layer, and eliminates the occurrence of unintended parasitic capacitance and circuits. Further, it becomes possible to increase the area of the substrate at low cost. As a result, a high speed and low power consumption element can be realized at low cost.

[0016]

In the epitaxial growth of a compound semiconductor layer above a Si substrate, Fe or Cr is used.
Or one of Mn, V, O or B,
Alternatively, it has been considered that the compound semiconductor layer is made to have a high resistance by adding some of them as impurities to form a compound semiconductor laminated substrate on Si in which a semi-insulating compound semiconductor layer is provided above the Si substrate.

In the compound semiconductor laminated substrate on Si, the compound semiconductor layer is epitaxially grown above the Si substrate. Liquid phase epitaxy growth (LPE: Liquid)
Phase Epitaxy method, molecular beam epitaxy growth (MBE: Molecular Beam Epi)
ta × y) method and metal-organic vapor phase epitaxy (MOVPE: Met)
al Organic Vapor Phase Ep
ita × y) method, metalorganic chemical vapor deposition (MOCVD: Me)
tal Organic chemical vapor
ization deposition method and the like (the MOVPE method and the MOCVD method are similar techniques and may be used without distinction). Both are methods of growing a crystal layer on a substrate by using the substrate as a seed crystal. For example, in the MBE method when the compound semiconductor layer is GaAs, Ga metal and A are used as raw materials for the GaAs layer.
The s metal is vaporized by resistance heating, and is epitaxially grown and deposited on the Si substrate. At this time, the GaAs layer uses the Si substrate as a seed crystal to form a crystal structure following the seed crystal to grow crystals. During the formation of this GaAs film, one or more of Fe metal, Cr metal, Mn metal, V metal, C or B metal is heated and vaporized and supplied simultaneously with Ga metal and As metal. When the vapor pressure is high, it is heated and vaporized by using a Knudsen cell (K-cell). When the temperature is low, the electron beam (EB) is used for heating and vaporization. As a result, those impurities are added to the epitaxially grown GaAs layer.

In the MOVPE method or the MOCVD method when the compound semiconductor layer is GaAs, Ga (CH ₃ ) ₃ (TMG: tri-m) is used as a raw material of the GaAs layer.
Ethyl garium) and AsH ₃ (arsine: A
r sine) is used. These are vaporized with a carrier gas such as Ar or nitrogen by bubbling,
When flowing over the substrate placed in the reaction tube, each gas is thermally decomposed on the substrate heated by the heating mechanism to cause a chemical reaction, and epitaxy grows and deposits on the substrate. At the time of film formation of this GaAs, F
One or some of the organic metals of e, Cr, Mn, V, and B are supplied. As a result, those impurities are added to the epitaxially grown GaAs layer. When it is desired to add O, it can be performed by mixing oxygen with a carrier gas and flowing it. In addition, Ga, As
It is also possible to introduce oxygen into each of the source gases or the organic complex of the impurity element to be added and to add the oxygen to the GaAs layer by selecting the film formation conditions.

The present invention derived from the above consideration will be described below.

According to the present invention, the III-V group compound crystal layer provided by epitaxy growth on the Si substrate is Fe.
(Iron) or Cr (chromium) or Mn (manganese) or V (vanadium) or C (carbon) or O (oxygen) or B (boron), or a semiconductor laminate characterized by containing one or more of them. The structure.

According to the present invention, the III-V group compound crystal layer disposed by epitaxy growth on the Si substrate is one of Fe, Cr, Mn, V, C, O or B of an appropriate concentration. By including a plurality of them, the semiconductor laminated structure is characterized in that the resistivity of the III-V group compound thin film crystal layer is 1 × 10 ⁷ Ωcm or more and exhibits semi-insulating properties.

Further, according to the present invention, in a semi-insulating group III-V compound crystal layer disposed by epitaxy growth on a Si substrate, epitaxy is performed on the upper part or the lower part or both of the semi-insulating group III-V compound crystal layer. A semiconductor laminated structure is provided in which a grown undoped III-V compound crystal layer is provided.

In the present invention, a III-V compound crystal layer exhibiting n-type or p-type conductivity is provided above a semi-insulating III-V compound crystal layer arranged by epitaxy growth on a Si substrate. The semiconductor laminated structure is characterized by the above.

Further, according to the present invention, in the III-V group compound crystal layer arranged by epitaxy growth above the Si substrate, the film thickness of the semi-insulating III-V group compound thin film crystal layer is 1 μm or more. A characteristic semiconductor laminated structure.

In the present invention, in the III-V group compound crystal layer arranged by epitaxy growth above the Si substrate, the undoped III-V is provided by epitaxy growth above or below the semi-insulating layer or both. The semiconductor laminated structure is characterized in that the compound semiconductor crystal layer has a film thickness of 50 nm or more.

Further, the present invention uses a semiconductor laminated structure including a semi-insulating layer composed of a III-V group compound crystal layer arranged by epitaxy growth on a Si substrate, and using it as a substrate, a transistor, a diode, a resistor and a capacitor. ,
A semiconductor element characterized by integrating elements such as an inductor and wiring.

In the present invention, in the process of epitaxially growing a III-V group compound crystal layer on a Si substrate, II
A method for forming a semiconductor laminated structure is characterized in that one or a plurality of Fe, Cr, Mn, V, C, O, or B is supplied together with a group I element raw material and a group V element raw material.

The present invention also provides a method for forming a semiconductor substrate in which a III-V group compound crystal layer is epitaxially grown on a Si substrate, at a concentration of 10 ^-6 Torr (1 Torr = 133.
322 Pa) or less using an MBE apparatus capable of decompressing to an ultra-high vacuum, in addition to the III-V group compound material metal of the group III element raw material and group V element raw material, Fe raw material, Cr raw material, Mn raw material, V raw material, or One or more metals of the C raw material or the B raw material are supplied, and the supply method by resistance heating using a Knudsen cell or filament cell, or an electron beam (EB: El
Electron Beam) A method of forming a semiconductor laminated structure characterized by using a supply method by heating or introducing oxygen gas.

Further, the present invention is a method of forming a semiconductor substrate in which a III-V group compound crystal layer is epitaxially grown above a Si substrate, using an MBE apparatus capable of reducing the pressure to an ultrahigh vacuum of 10 ^-6 Torr or less, III- In addition to the metal of the group III element raw material and the group V element raw material which are the constituent materials of the group V compound semiconductor, the O raw material is supplied, and the supply method is N ₂ O (nitrous oxide) or O ₃ (ozone). A method for forming a semiconductor laminated structure is characterized in that a highly oxidizing gas is used or the O ₂ gas is excited into a state of higher reactivity than the O ₂ gas itself by exciting the O ₂ gas into plasma or the like.

The present invention also provides a method for forming a semiconductor substrate in which a III-V group compound crystal layer is epitaxially grown on a Si substrate, using a metal-organic vapor phase epitaxy method to form a group III metal alkyl compound and a group V hydride III. Semi-insulating III-V by forming a film by adding one or more of Fe, Cr, Mn, V, C, or B, or a plurality of organometallic compounds or complexes thereof in addition to the -V compound constituent material A method for forming a semiconductor laminated structure, comprising forming a group compound thin film crystal layer above a crystalline substrate.

Further, according to the present invention, Fe, Cr, Mn, or V is formed on an undoped III-V compound thin film crystal layer arranged by epitaxy growth on a Si substrate.
Alternatively, by ion-implanting one of C, O, or B, or a plurality of elements or compounds thereof, the resistivity of the III-V group compound thin film crystal layer formed above the Si substrate is set to 1 × 10 ^7. A method for forming a semiconductor laminated structure is characterized in that it has a semi-insulating property with Ωcm or more.

According to the present invention, in the semiconductor laminated structure in which the III-V group compound crystal layer is epitaxially grown above the Si substrate, the III-V group compound is any one of Ga, In, and Al group III elements. A plurality of them and As (arsenic) or P (phosphorus) or N (nitrogen)
The semiconductor laminated structure is characterized in that it is a compound of any one of the group V elements or a plurality thereof.

The present invention also provides a method of forming a semiconductor substrate in which a III-V group compound crystal layer is epitaxially grown on a Si substrate, wherein the III-V group compound is Ga or I.
One or more of n or Al group III elements and As (arsenic), P (phosphorus), or N
A method for forming a semiconductor laminated structure is characterized in that it is a compound of any one or more of group V elements of (nitrogen).

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a III-V group compound semiconductor laminated structure including a semi-insulating layer provided by epitaxy growth above a Si substrate according to the present invention, a method for forming the same, and a device formed thereby. Will be described with reference to the drawings.

(First Embodiment) First, S in the present invention
A first example of a film forming method for forming a III-V group compound semiconductor laminated structure including a semi-insulating layer provided by epitaxy growth on an i substrate will be described.

FIG. 1 schematically shows an apparatus for a molecular beam epitaxy (MBE) growth method which is one of the methods for forming a semiconductor laminated structure according to the present invention.

Now, in the semiconductor laminated structure to be formed, Si
III-V installed by epitaxy growth above the substrate
The group compound semiconductor is GaAs for simplicity.
In addition, in the III-V group compound semiconductor, a group III element, V
The elements of the group elements are Ga, In, Al and As, respectively.
Any one of P and N may be provided, or a plurality thereof may be provided.

The vacuum chamber 1 is the main body of the MBE growth apparatus used in the MBE growth method, and the inside is 1 × 10.
It is a vacuum container that can maintain a highly airtight state of ^-7 Torr or less. The substrate 2 on which the semiconductor laminated structure is formed is introduced and installed in the vacuum chamber 1, and is heated and maintained at a desired temperature by the substrate heating device 3. The first state before the semiconductor laminated structure is formed on the substrate 2 is Si. Further, a Si (001) plane is exposed on the surface. The vacuum chamber 1 is evacuated by the vacuum pump 4, whereby a high vacuum state can be achieved. The vacuum chamber 1 is provided with a substrate introducing chamber 5, and the substrate 2 is first cleaned into the substrate introducing chamber 5 and then introduced into the vacuum chamber 1. The substrate introducing chamber 5 is usually evacuated separately from the vacuum chamber 1 by a vacuum pump, and is often separated from the vacuum chamber 1 by a highly airtight partition wall (gate) that can be opened and closed. . As a result, the vacuum chamber 1 can be prevented from coming into direct contact with the atmosphere, and the vacuum degree of the vacuum chamber 1 can be kept high. III in MBE growth now
Ga metal is used as a raw material of the group element, and this is filled in K-cell (Knudsen cell) 6 for use. K-cell 6
The Ga metal filled by resistance heating is heated and evaporated to be supplied to the substrate 2. A as a raw material for group V elements
The s metal is used, and this is used by filling the K-cell 7.
Like Ga metal, it is evaporated by heating and supplied to the substrate 2. When forming a compound other than GaAs, K-
The cells 6 and K-cells 7 may be filled with the constituent Group III and V elements, respectively, and when a plurality of elements are used for each, the number of K-cells may be added and used. good.

When only the raw materials of the constituent elements of the III-V compound semiconductor are supplied to the substrate 2, an undoped GaAs layer in which impurities are not intentionally added is formed, but formation of a semi-insulating layer or In order to form the p-type or n-type layer, it is necessary to supply additional dopant. It is a solid of dopant (impurity) and its evaporation temperature is 13
When the temperature is below 00 ° C, K-cell 8 is used as in the case of Ga and As.
Is brought in. If it exceeds 1300 ° C, EB
The (electron beam) heating device 9 is used. When the dopant is a gas at room temperature, the gas cell 10 is used.
The gas cell 10 can supply the gas to the substrate 2 while controlling the flow rate of the gas supplied from the outside of the chamber 1, and supplies the gas in a highly excited state by heating (cracking) or RF (radio frequency) plasma excitation. You can Similarly, when a buffer layer, which is a layer having a different structure, is inserted between the Si substrate and the GaAs layer, the K-cell, the EB, or the like depending on the evaporation temperature or the presence of gas.
Add a heating device and gas cell.

FIG. 2 is a drawing schematically showing the step of forming a semiconductor laminated structure in the first embodiment according to the present invention along with the step.

FIG. 2A shows the Si substrate 11 in the initial state of forming a semiconductor laminated structure, and in this case, the buffer layer 12 is further laminated and exposed on the surface thereof. For the buffer layer, for example, SrTiO ₃ or BaSrTi
Examples include O ₃ and BiTiO ₃ . The buffer layer is made of these Si
The strain due to the difference in the lattice constant and the difference in the coefficient of thermal expansion between the substrate and the GaAs layer is relaxed, and the effects of suppressing the occurrence of defects and suppressing the occurrence of antiphase are provided. The buffer layer may not be used in the step shown in FIG. 2 described below. In that case, the GaAs layer is directly laminated on the Si substrate 11.

In FIG. 2B, K- is formed on the buffer layer 12.
It shows how the Ga raw material and the As raw material, which have been heated and vaporized by the cell, arrive. The Si substrate 11 including the buffer layer 12 is subjected to G by the substrate heating device 3 in the MBE chamber 1.
It is kept at the most suitable temperature for epitaxy growth of the aAs layer, which is usually between 450 ° C and 680 ° C. In addition, prior to the supply of the Ga raw material and the As raw material, either of the raw materials is often supplied first to the surface of the buffer layer 12. In this case, the As raw material is supplied onto the buffer layer 12 first, and the surface thereof is It is coated with As raw material.
The As raw material is heated and evaporated by the K-cell 7 and is supplied to the substrate 2 in a gas state. However, the form of the gas is not only As atoms, but rather molecules of As ₂ to As ₈ having a plurality of As bonded. It is believed to be the main steam. Therefore, the As raw material 13 reaching the substrate is also As
It is considered to include not only single atoms but also a state in which a plurality of As are bonded. It is also considered that bonds are formed with atoms of the buffer layer at the interface in contact with the buffer layer. Note that the surface of the buffer layer 12 may be first coated with a Ga raw material instead of the As raw material. In this case, it is considered that the Ga raw material is supplied in a state of almost Ga atoms, and Ga atoms on the surface of the buffer layer 12 or those in which Ga atoms form bonds with atoms on the surface of the buffer layer 12 are considered. It seems to exist.

By supplying the Ga raw material and the As raw material to the surface of the buffer layer 12 coated with the As raw material or the Ga raw material, a GaAs layer is formed as shown in FIG. 2C. At this time, only Ga raw material and As raw material are supplied to the surface of the buffer layer. Therefore, the GaAs layer 15 formed
Is undoped GaA with no impurities added
It is the s layer.

FIG. 2D shows the Si substrate 11 and the buffer layer 1.
Undoped GaAs layer 1 epitaxially grown above 2
5 shows how a semi-insulating GaAs layer is formed on the substrate 5. That is, the As raw material 1 is formed on the undoped GaAs layer 15.
3. The impurities 16 for achieving the insulating property are supplied together with the Ga raw material 14. The impurities 16 supplied to achieve the insulating layer are Fe, Cr, Mn, or V.
Alternatively, there are C, O, or B, and here, for example, Cr is used.

FIG. 2 (e) shows the result of film formation in FIG. 2 (d).
An undoped GaAs layer showing the formed laminated structure
Semi-insulating GaAs layer 1 containing Cr as an impurity on 15
7 are formed. At this time, the semi-insulating GaAs layer 17
Cr concentration is about 5 × 10 ¹⁵cm^-3From 5 × 10¹⁶c
m^-3Is in between.

FIG. 2F shows the second undoped GaAs layer 18 on the semi-insulating GaAs layer 17 through the same process.
And a state in which an n-type or p-type impurity is added to form a GaAs layer 19 which has become an n-type or p-type semiconductor. Here, the GaAs layer 1 which is an electrically semiconductor
For example, an n-type GaAs layer is considered as 9, and the added impurity 20 is Si which is one of the n-type impurities.

The undoped GaAs layer 15, the semi-insulating layer 17, and the second undoped layer 18 can be formed in any thickness according to the purpose. However, when considering the integration of various devices on the formed laminated semiconductor structure, there is an appropriate thickness. First
When the thickness of the undoped layer 15 is the thickness a, the thickness of the semi-insulating layer 17 is the thickness b, and the thickness of the second undoped layer 18 is the thickness c, each thickness is 50 nm. Or more, 1 μm or more,
It is 50 nm or more.

The semi-insulating layer 17 has a resistivity of 1 × 10 ⁷
Since it is Ωcm or more, it has a sufficient resistivity to electrically separate two or more elements in an integrated circuit. Its thickness is the breakdown withstand voltage and the amount of leak current between the Si substrate 11 and the element on the integrated circuit which is installed above the semi-insulating layer 17 exclusively.
And the capacitance. Now 50 μm
If a square metal electrode of 50 μm is directly placed on the semi-insulating layer 17 and a voltage is applied between it and the Si substrate 11, its resistance is 4 × 10 ⁷ Ω when the film thickness is 1 μm. Therefore, even when a voltage of 10 V is applied, the leakage current amount is
Very low, 2.5 × 10 ⁻⁷ A / cm ² . The electric field strength becomes 10 kV / cm when the film thickness is 1 μm, and Ga
It is sufficiently smaller than the breakdown voltage of As itself and is very stable electrically. However, its capacitance is 2.5
It becomes 4 × 10 ⁻¹³ F, which is sufficiently small, but when it is larger than this, the effect of reducing the operation speed of the element becomes conspicuous. Therefore, it is desirable that the semi-insulating layer 17 has a thickness of 1 μm or more in order to make the integrated circuit formed by utilizing this very stable, high speed operation and low power consumption.

For the GaAs crystal of the semi-insulating layer 17, S
Si, which is a constituent material of the i substrate, is an n-type impurity. Further, when diffused into the GaAs crystal layer in the buffer layer, Sr, Ba, etc. also act as n-type impurities. Therefore, the resistivity of the semi-insulating layer 17 may decrease due to the diffusion of atoms from the Si substrate 11, the buffer layer 12, or the n-type doping layer 19 formed above. So around the semi-insulating layer 17 the undoped layers 15 and 1
Install 8. This prevents Si in the Si substrate, Sr in the buffer layer, Si in n-type GaAs, or the like from penetrating into the semi-insulating substrate and deteriorating the insulating property. For that purpose, the thickness of the undoped layer must be 50 nm or more.

(Second Embodiment) Next, S in the present invention
A second example of a film forming method for forming a III-V compound semiconductor laminated structure including a semi-insulating layer provided by epitaxy growth on an i substrate will be described.

Now, in the semiconductor laminated structure to be formed, Si
III-V installed by epitaxy growth above the substrate
The group compound semiconductor is GaAs for simplicity.
In addition, in the III-V group compound semiconductor, a group III element, V
The elements of the group elements are Ga, In, Al and As, respectively.
Any one of P and N may be provided, or a plurality thereof may be provided.

FIG. 3 is a drawing schematically showing a MOVPE apparatus used for epitaxy growth in the second embodiment. The reaction tube 21 is a container corresponding to an airtight state from a low vacuum to a low pressure state so that MOVPE growth can be performed therein. Usually, quartz or the like is used, but it is often made of stainless steel. The substrate 22 is introduced into the reaction tube 21 and installed on the substrate holding device 23. A heating mechanism is often added to this substrate holding device, whereby the substrate can be heated and held at a temperature suitable for epitaxy growth. In another case, the substrate holding device may not be provided with a heating mechanism, and a high frequency coil may be installed around the reaction tube 21 to directly heat the substrate by high frequency. The reaction tube 21 is evacuated by a pump 24, and the excess gas that has flowed for epitaxy growth and has not reacted is evacuated to a pipe 25 connected to the gas decomposition tower. In this reaction tube 21, piping 2
A raw material gas is introduced through 6. The introduced gas includes, for example, N ₂ (nitrogen) and H ₂ (hydrogen) as the carrier gas 27, and for forming a GaAs film as the source gas 28, for example, Ga source TMG (Al (C
H _{3) 3),} there is such as arsine (ArH _3). Further, as the impurity raw material 29, for example, ferrocene which is a raw material of Fe introduced to achieve semi-insulating property, silane (SiH ₄ ) which is a raw material of Si of an n-type dopant, and DMZ (Zn (CH ₃ ) ₂ ) etc.

FIG. 4 is a drawing schematically showing the step of forming a semiconductor laminated structure in the second embodiment according to the present invention along with the step.

FIG. 4A shows the Si substrate 30 in the initial state of forming a semiconductor laminated structure. In this case, the buffer layer 31 is further laminated on the surface and exposed. For the buffer layer, for example, SrT is used as in the first embodiment.
iO ₃ and BaSrTiO _3, BiTiO ₃ include, the same applies to the work. In some cases, this buffer layer may not be used in the step in FIG. 4 described below. In that case Ga
The As layer will be directly laminated on the Si substrate 30.

FIG. 4B shows the reaction tube 21 of the MOVPE apparatus.
The figure shows a state in which the arsine 32 as the As raw material supplied onto the buffer layer 31 on the surface of the substrate 22 installed therein reaches. The Si substrate 30 including the buffer layer 31 is kept at a temperature most suitable for the epitaxial growth of the GaAs layer by the heating mechanism of the substrate holding device 23 in the reaction tube 21, and the temperature is usually 500 ° C. to 900 ° C.
Between Prior to supplying the Ga raw material and the As raw material, either raw material is often supplied first to the surface of the buffer layer 31, and in this case, the arsine 32 which is the As raw material is supplied to the buffer layer 12 first. , Its surface is A
It is covered with s34.

FIG. 4 (b) shows the reaction state of the supplied arsine 32. Arsine 32, which is a hydride of arsenic, reaches the surface of the buffer layer 31 and is adsorbed to form a transition state 33 in which the bonding state with hydrogen is weakened. Further, the heat of the substrate 22 completely breaks the bond with hydrogen, and hydrogen is released into the atmosphere. As a result, arsenic atoms 34 are solely adsorbed on the surface of the buffer layer.

FIG. 4 (c) shows the reaction state of the supplied TMG35. TMG35, which is an alkyl compound of gallium, is a buffer layer 31 covered with arsenic atoms 34.
Reaches and is adsorbed on the surface of the, and forms a transition state 36 in which the bonding state with the alkyl group is weakened. Further, the heat of the substrate 22 completely separates the bond with the alkyl group,
The alkyl molecules 38 are released into the atmosphere. As a result, the arsenic atoms 34 and Ga atoms 3 covering the buffer layer 31
4 reacts to form a GaAs compound.

Note that the surface of the buffer layer 31 may be first supplied with the Ga source TMG 35 instead of the source Arsine 32 and coated therewith.

The GaAs layer is formed by supplying the Ga raw material and the As raw material to the surface of the buffer layer 31 covered with the As raw material or the Ga raw material. At this time, only Ga raw material and As raw material are supplied to the surface of the buffer layer. Therefore, the formed GaAs layer is an undoped GaAs layer to which no impurities are added.

FIG. 4D shows the grown undoped GaAs.
A state of forming a semi-insulating GaAs layer on the layer 39 is shown. That is, on the undoped GaAs layer 39, the arsine 32 and the TMG 35 are supplied together with the impurity 40 which is an impurity for achieving insulation. Impurity 40 supplied to achieve the insulating layer is Fe, Cr, or Mn.
Alternatively, there is V, C, O, or B, and here, for example, Fe is used. Also MOVP
Since the metal cannot be used as it is in the E growth, the alkyl compound is used for the metal. That is, in this case, ferrocene 40, which is one of Fe alkyl compounds, is used as the impurity 40 for achieving the semi-insulating property.

Ferrocene 40 is arsine 32 or TMG3
After reaching and adsorbing to the outermost growth surface as in No. 5, the alkyl group portion 42 is finally favored and the Fe atom 41 is incorporated into the GaAs crystal through a transition state in which a weak bond is formed with the outermost surface atom. Becomes

FIG. 4 (e) shows the result of the film formation in FIG. 4 (d).
An undoped GaAs layer showing the formed laminated structure
Semi-insulating GaAs layer 4 containing Fe as an impurity on 39
3 is formed. At this time, the semi-insulating GaAs layer 43
Fe concentration is about 5 × 10 ¹⁵cm^-3From 5 × 10¹⁶c
m^-3Is in between.

On the latter half insulating GaAs layer 43, the first
As in the above embodiment, an undoped GaAs layer or a GaAs semiconductor layer having n-type or p-type conductivity may be laminated. The structure, the film thickness and the like are the same as those in the first embodiment, and therefore the description thereof is omitted here.

(Third Embodiment) Next, S in the present invention
Regarding the film forming method for forming the III-V group compound semiconductor laminated structure including the semi-insulating layer provided by epitaxy growth above the i substrate, the ion implantation method as the third embodiment was used. The method will be described.

Now, in the semiconductor laminated structure to be formed, Si
III-V installed by epitaxy growth above the substrate
The group compound semiconductor is GaAs for simplicity.
In addition, in the III-V group compound semiconductor, a group III element, V
The elements of the group elements are Ga, In, Al and As, respectively.
Any one of P and N may be provided, or a plurality thereof may be provided.

FIG. 5 is a drawing schematically showing the step of forming a semiconductor laminated structure in the third embodiment according to the present invention along with its stage.

FIG. 5A shows a state in which an undoped GaAs layer 46 is laminated on the buffer layer 45 on the Si substrate 44 by using the same method as in the first and second embodiments. There is. Details thereof are the same as those of the both, and therefore will be omitted here.

FIG. 5 (b) is a schematic view of the non-deposited structure formed in FIG. 5 (a).
A semi-insulating property is achieved in the GaAs layer using an ion implanter.
Showing the state of implanting impurities 47 to form
There is. In this example, Cr atoms are used as impurities.
In the ion implantation method, the distribution depth of Cr atoms depends on the conditions.
And the concentration can be set within a certain range. No do now
Charge / separation from the interface between the GaAs layer 46 and the buffer layer 45
So that it penetrates only up to a certain distance (eg 50 nm)
Set the injection conditions. Moreover, the concentration is set to 5 × 10. ¹⁵cm^-3
From 5 × 10¹⁶cm^-3To be set. But
However, the semi-insulating property is achieved only by injecting Cr atoms.
I can't. It is only implanted with Cr atoms that are GaAs
It only exists at a position that is deviated from the lattice position of the crystal
This is because it does not exert its ability as an impurity.

FIG. 5C schematically shows this state.
Is. Therefore, the implanted substrate is annealed at a high temperature. As a result, Cr atoms move and enter the lattice position of the GaAs crystal, so that semi-insulating property is exhibited. The conditions of this annealing differ depending on the constituent elements of the III-V compound semiconductor, but in the case of GaAs crystal, for example, 500 ° C to 7 ° C.
00 ° C, 15 minutes, arsine atmosphere or Si ₃ N ₄ film
It is performed with the aAs surface protected.

FIG. 5D is a diagram schematically showing the state after annealing in FIG. 5C. The Cr atoms, which were not in the lattice position in FIG. 5C, enter the lattice position of the GaAs crystal and are evenly diffused and uniformly distributed with a certain width. As a result, an undoped layer 49 which is an undoped region and a semi-insulating layer 50 which is a semi-insulating region are formed.

At this time, the thickness a of the undoped layer 49 and the thickness b of the semi-insulating layer 50 are preferably 50 nm or more and 1 μm or more, respectively.

(Fourth Embodiment) Next, in the present invention, S
A structure of a semiconductor device in which semiconductor elements are integrated using a III-V group compound semiconductor laminated structure including a semi-insulating layer provided by epitaxy growth above an i substrate as a substrate will be described.

Now, the structure of the III-V group compound semiconductor provided by epitaxy growth above the Si substrate is GaAs for simplicity. The composition of the group III element and the group V element in this III-V group compound semiconductor is G
Any one of a, In, Al and As, P, N may be provided, or a plurality thereof may be provided.

FIG. 6 shows a semiconductor device integrated on the semiconductor laminated structure according to the fourth embodiment of the present invention. Specifically, S according to the fourth embodiment of the present invention
FIG. 2 is a schematic cross-sectional view of a structure in which elements such as a transistor, a diode, a resistor, a capacitor, an inductor, and a wiring are integrated using a compound semiconductor layer including a semi-insulating layer epitaxially grown above an i substrate as a substrate.

FIG. 6A shows a structure in which a semiconductor laminated structure according to the present invention is used and a light emitting element and a light receiving element are integrated using this as a substrate. That is, the Si substrate 5
An undoped layer 53 is laminated on the first layer via a buffer layer 52, and a semi-insulating layer 54 is laminated thereon.
Further, an n-type AlGaAs layer 56 is laminated via an undoped layer 54. The n-type AlGaAs layer 56 is processed by etching, and the n-side electrode metal 59 is deposited on the lower side of the step. A GaAs layer 57 called an active layer is laminated on the upper side of the step. Normally, the undoped GaAs active layer 57 is used. A p-type AlGaAs layer 58 is laminated on it. The n-type AlGaAs layer 56 and the p-type AlGaAs layer 58 function as a clad layer of a laser diode or a light emitting diode which is a light emitting element, and confine the current supplied from the electrode metal and the light generated by the element itself in the active layer. , Has the function of emitting light efficiently. Al
GaAs has a lower valence band, a higher conduction band, and a larger band gap than GaAs. As a result, the electrons supplied from the n-type AlGaAs 56 are undoped Ga on the conduction band side.
It falls into the As active layer 57 and does not flow into the p-type AlGaAs 58. The holes supplied from p-type AlGaAs 58 are also undoped GaAs on the valence band side.
It falls into the active layer 57 and does not flow out into the n-type AlGaAs 56. Therefore, electrons and holes are efficiently undoped Ga
The As active layer 57 is confined by a direct transition to cause recombination and emits light corresponding to the band gap. AlGaAs has a slightly smaller refractive index than GaAs. Now, considering the distribution of the refractive index in the direction perpendicular to the laminated structure, the active layer 57 has the highest refractive index, and the n-type AlGaAs layer 56 and the p-type AlGaAs called the clad layer
Small in layer 58. Of the light generated in the active layer according to Snell's law, the light traveling at a narrow angle with respect to the laminated structure is totally reflected at the interface between the active layer 57 and the cladding layers 56 and 58, and is confined in the active layer 57. Become. Therefore, the probability of further stimulated emission by the generated light is increased, and the efficiency of light emission is increased. p-type AlGaAs cladding layer 5
A p-side electrode metal 59 is vapor-deposited on the surface 8.

A p-type GaAs layer 60 is laminated on the second undoped layer 48 on the same substrate. An undoped GaAs layer 61 is laminated on this, and an n-type GaAs layer 62 is further laminated thereon. A step is formed in the p-type GaAs layer 60 by etching, and a p-side electrode metal 59 is formed below the step and an n-type Ga above the step is formed.
An n-side electrode metal 59 is vapor-deposited on the As layer 62.
In this portion, when light is applied to the surface of the n-type GaAs layer 62, a current is generated between the p-side and n-side electrodes, and this serves as a light receiving element.

These light emitting element and light receiving element are separated by a groove structure (trench) 63 formed by etching or the like.
The semi-insulating layer 54 supporting both of them has a very high resistance, so that the two elements can be kept electrically completely separated from each other, and the two elements are not electrically influenced by each other.

FIG. 6B shows a field effect transistor 6 using the semiconductor laminated structure of the present invention as a substrate.
7 and pn junction diode 68, metal wiring, inductor 69 and MIS type capacitor 70 using the same
It shows the structure that integrates such elements. That is, the undoped layer 66 is laminated on the Si substrate 64 via the buffer layer 65, and the semi-insulating layer 67 is laminated thereon. Ions are partially implanted into the semi-insulating layer 67 to form a p-type implantation region 61 and an n-type implantation region 62.
To form. The p-type injection region 61 becomes a p-type conduction semiconductor and the n-type injection region 62 becomes an n-type conduction semiconductor. By selecting the ion implantation conditions, the semi-insulating layer 67 once made to be p-type can also be made an n-type conductive semiconductor layer by n-type implantation. Further, the gate stack structure 63 and the insulating film 64 are partially formed using a mask. In some cases, the gate stack structure 63 is formed of only a refractory metal,
In some cases, it has a laminated structure of an insulating film and a metal. On the p-type implantation region 61, the n-type implantation region 62, the gate stack 63, the insulating film 64 and the semi-insulating GaAs layer 60, the electrode metal 65 and the wiring and the inductor 66 are partially formed using a mask. As a result, a field effect transistor is formed in the region 67, a pn junction diode is formed in the region 68, a wiring and an inductor are formed in the region 69, and a MIS type capacitor is formed in the region 70.

Since the semi-insulating GaAs layer 60 has a very high resistance, the transistor 67 including the wiring and the inductor 69, the diode 68, and the capacitor 70 are completely separated from other elements and may be electrically affected. There is nothing to give.

[0080]

INDUSTRIAL APPLICABILITY In the present invention, III-
In the epitaxial growth of the group V compound semiconductor layer, one of Fe, Cr, Mn, V, O or B, or some of them is added as an impurity to increase the resistance of the compound semiconductor layer, so that the semiconductor layer above the Si substrate has a high resistance. On Si on which an insulating compound semiconductor layer is provided III
It is feasible to form a group V compound semiconductor laminated substrate. As a result, a semi-insulating III-V group compound semiconductor epitaxial growth substrate using a Si substrate which has never existed until now can be realized, and a large-area semi-insulating III-V group compound semiconductor substrate exceeding 8 inches at low cost can be realized. Will be realized. Further, by integrating elements on this, a high-speed and low-power-consumption semiconductor device can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a molecular beam epitaxy apparatus according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing stepwise a process of epitaxy growth of a compound semiconductor layer including a semi-insulating layer above a Si substrate according to the first embodiment of the present invention.

FIG. 3 is a schematic sectional view of a metal-organic vapor phase epitaxy apparatus according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram showing stepwise a process of epitaxy growth of a compound semiconductor layer including a semi-insulating layer above a Si substrate according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram showing stepwise a process of epitaxy growth of a compound semiconductor layer including a semi-insulating layer above a Si substrate according to a third embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a structure in which elements such as transistors are integrated using a compound semiconductor layer including a semi-insulating layer epitaxially grown above a Si substrate according to a fourth embodiment of the present invention as a substrate.

[Explanation of symbols]

11 Si substrate 12 buffer layers 13 As raw material 14 Ga raw material 15 Undoped GaAs layer 16 impurities 17 Semi-insulating GaAs layer 18 Second undoped GaAs layer 19 GaAs layer 20 impurities

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4G077 AA03 AB06 BE13 BE15 BE43                       BE44 BE46 BE47 BE48 DA04                       DA05 EA07 EB01 EB05 ED06                       HA06 SA04 SA07 SC02 SC12                 5F045 AA05 AB10 AD08 AD09 AD10                       AD11 AF03 BB16 CA09 DA53                       DA57

Claims (14)

[Claims] 1. A III-V group compound crystal layer provided by epitaxy growth on a Si substrate, wherein Fe (iron), Cr (chromium), Mn (manganese), V (vanadium), C (carbon) or A semiconductor laminated structure comprising at least one of O (oxygen) and B (boron). 2. The semiconductor laminated structure according to claim 1, wherein the III-V compound thin film crystal layer has a specific resistance of 1 × 10 ⁷ Ωcm or more and exhibits a semi-insulating property. 3. A semi-insulating III-V compound crystal layer is provided with an epitaxy-grown undoped III-V compound crystal layer above or below or both. The semiconductor laminated structure according to. 4. A III-V compound crystal layer exhibiting n-type or p-type conductivity is provided by epitaxy above the semi-insulating layer III-V compound crystal layer. Item 4. The semiconductor laminated structure according to item 2 or 3. 5. The semiconductor laminated structure according to claim 2, wherein the semi-insulating group III-V compound crystal layer has a film thickness of 1 μm or more. 6. The semiconductor laminated structure according to claim 3, wherein the film thickness of the undoped III-V compound semiconductor crystal layer is 50 nm or more. 7. A semiconductor element, wherein elements such as a transistor, a diode, a resistor, a capacitor, an inductor, and a wiring are integrated with the semiconductor laminated structure according to claim 1 as a substrate. 8. In the process of epitaxially growing a III-V group compound semiconductor crystal layer above a Si substrate, Fe, Cr, Mn, V, C, O or B in addition to the group III element raw material and the group V element raw material. At least one of the above is supplied, The manufacturing method of the semiconductor laminated structure characterized by the above-mentioned. 9. 10 ⁻⁶ Torr (1 Torr = 133.
322 Pa) or less using an MBE device capable of decompressing, III
In addition to the group III element raw material and the group V element raw material metal, which are constituent materials of the group V compound semiconductor, a Fe raw material or C
One or more metals of r raw material, Mn raw material, V raw material, C raw material or B raw material are supplied,
In addition, the supply method may be a resistance heating method using a Knudsen cell (K-cell) or a filament cell, or an electron beam (EB: Electron Bea).
m) The method for manufacturing a semiconductor laminated structure according to claim 8, wherein a supplying method by heating is used. 10. MB capable of reducing the pressure to 10 ⁻⁶ Torr or less
Using the E apparatus, in addition to the metal of the group III element raw material and the group V element raw material which are the constituent materials of the III-V group compound semiconductor,
O raw material is supplied and the supply method is N ₂ O (nitrous oxide)
A highly oxidative gas such as or O ₃ (ozone) is used, or the O ₂ gas is made into a state of higher reactivity than the O ₂ gas itself by exciting the O ₂ gas by plasma or the like. 8. The method for manufacturing a semiconductor laminated structure according to item 8. 11. Any one of Fe, Cr, Mn, V, C, and B in addition to the III-V group compound material of the III-group metal alkyl compound and the V-group hydride by using the metal organic chemical vapor deposition method. 9. The semi-insulating group III-V compound semiconductor crystal layer is formed above the Si substrate by adding a plurality of organic metal compounds or their complexes to form a film. Manufacturing method of semiconductor laminated structure. 12. Fe, Cr, Mn, V, or C in an undoped III-V compound thin film crystal layer provided by epitaxy growth above a Si substrate.
Alternatively, by ion-implanting one of O or B, or a plurality of elements or compounds thereof, S
The resistivity of the entire III-V compound thin film crystal layer formed on the i substrate or a predetermined film thickness portion is 1 × 10 ⁷ Ω.
A method for manufacturing a semiconductor laminated structure, characterized by having a semi-insulating property with a height of cm or more. 13. The III-V group compound is Ga or In.
Alternatively, it is a compound composed of any one or more of group III elements of Al and one or more of group V elements of As (arsenic), P (phosphorus) or N (nitrogen). Claim 1 characterized by the above.
7. The semiconductor laminated structure according to any one of 1 to 6. 14. The III-V group compound is Ga or In.
Alternatively, it is a compound composed of any one or more of the group III elements of Al and one or more of the group V elements of As (arsenic), P (phosphorus) or N (nitrogen). 9. The method according to claim 8, wherein
14. The method for manufacturing a semiconductor laminated structure according to any one of 1 to 13.