JP2003223478A5 - - Google Patents
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- Publication number
- JP2003223478A5 JP2003223478A5 JP2002342700A JP2002342700A JP2003223478A5 JP 2003223478 A5 JP2003223478 A5 JP 2003223478A5 JP 2002342700 A JP2002342700 A JP 2002342700A JP 2002342700 A JP2002342700 A JP 2002342700A JP 2003223478 A5 JP2003223478 A5 JP 2003223478A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/998,174 | 2001-12-03 | ||
| US09/998,174 US20030106030A1 (en) | 2001-12-03 | 2001-12-03 | Method and program product for compressing an electronic circuit model |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003223478A JP2003223478A (ja) | 2003-08-08 |
| JP2003223478A5 true JP2003223478A5 (ja) | 2005-12-22 |
Family
ID=25544878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002342700A Withdrawn JP2003223478A (ja) | 2001-12-03 | 2002-11-26 | 集積回路モデルの圧縮方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20030106030A1 (ja) |
| JP (1) | JP2003223478A (ja) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7127688B2 (en) * | 2003-10-03 | 2006-10-24 | Cadence Design Systems, Inc. | Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit |
| US8312879B2 (en) * | 2006-10-16 | 2012-11-20 | General Electric Company | Method and apparatus for airway compensation control |
| KR100895260B1 (ko) * | 2007-02-27 | 2009-04-29 | 포항공과대학교 산학협력단 | 회로 모델 축소 해석 방법 |
| US8479131B2 (en) | 2011-03-02 | 2013-07-02 | International Business Machines Corporation | Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts |
| US10402532B1 (en) * | 2016-04-07 | 2019-09-03 | Cadence Design Systems, Inc. | Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components |
| US10002220B2 (en) * | 2016-04-27 | 2018-06-19 | International Business Machines Corporation | On the fly netlist compression in power analysis |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2136235B (en) * | 1983-02-22 | 1986-07-09 | Philips Electronic Associated | Rc active filter device |
| US4916627A (en) * | 1987-12-02 | 1990-04-10 | International Business Machines Corporation | Logic path length reduction using boolean minimization |
| US5696694A (en) * | 1994-06-03 | 1997-12-09 | Synopsys, Inc. | Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist |
| US5568395A (en) * | 1994-06-29 | 1996-10-22 | Lsi Logic Corporation | Modeling and estimating crosstalk noise and detecting false logic |
| US5903469A (en) * | 1994-11-08 | 1999-05-11 | Synopsys, Inc. | Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach |
| US5896300A (en) * | 1996-08-30 | 1999-04-20 | Avant| Corporation | Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets |
| US5878053A (en) * | 1997-06-09 | 1999-03-02 | Synopsys, Inc. | Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs |
| JP4153095B2 (ja) * | 1998-08-07 | 2008-09-17 | 富士通株式会社 | レイアウトデータ作成方法、レイアウトデータ作成装置、及び記録媒体 |
| US6405348B1 (en) * | 1999-10-27 | 2002-06-11 | Synopsys, Inc. | Deep sub-micron static timing analysis in the presence of crosstalk |
| US6536024B1 (en) * | 2000-07-14 | 2003-03-18 | International Business Machines Corporation | Method for making integrated circuits having gated clock trees |
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2001
- 2001-12-03 US US09/998,174 patent/US20030106030A1/en not_active Abandoned
-
2002
- 2002-11-26 JP JP2002342700A patent/JP2003223478A/ja not_active Withdrawn