JP2003223474A - Bs cluster test diagnosis rate improving system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a PT board design wherein the diagnostic rate of a test for the PT board using BS function is set to become a prescribed value or more so as to reduce a test cost and improve the quality of shipping products; however, the diagnostic rate in the PT board test using the BS function and calculated by a manual selection result of the cluster requires a lot of manhour. <P>SOLUTION: This BS cluster test diagnosis rate improving system is provided with a means for setting a set of simple net states differentiated for cluster identification such as test signal impression, power impression, clock impression, constant voltage impression, and instable states in each net for determining whether or not a test signal is propagated, determining a combination of the net states in an input side in each circuit, changing the net in an output side to the test signal impression state, when the test signal can be propagated, selecting the net system whose net state from a BS driving point to a BS observing point becomes the test signal impression state, and calculating the diagnostic rate along with the selected whole cluster. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention utilizes a boundary scan (hereinafter referred to as BS) to mount a BS mounted on a printed board (hereinafter referred to as PT board) (BS part). The present invention relates to a BS cluster test diagnostic rate improvement system for calculating a diagnostic rate and presenting an improvement of the diagnostic rate when testing other parts and circuit networks (net), and particularly, for pins of connectors and BS chains of BS parts. If the constituent pins are BS driving points or BS observing points, and a simple test pattern sequence is applied to a set of multiple BS driving points and the effect can be observed at the BS observing points, the net sequence used for the signal path in the middle ( A set of nets, pins, and circuits) is used as a testable cluster (hereinafter referred to as a cluster), and all cluster areas are automatically recognized to obtain a diagnostic rate. How can add BS driving point and BS observation point PT board of preparative interest for the most effective BS cluster test diagnostic factor correction system calculates how can a larger cluster area.

In this specification, the term "BS driving point" refers to a terminal capable of directly driving a test signal by a tester. Further, in this specification, the term "BS observation point" refers to a terminal capable of directly observing a signal with a tester.

[0003]

2. Description of the Related Art A PT board test method using a BS function has been standardized (IEEE 1149.1) and is in widespread use for the purpose of automating a functional test of a PT board and fault tracking.
The BS function is a function that allows the tester to directly drive or observe the external pin group of the LSI mounted on the PT board.

FIG. 14 shows a structural example of a BS function test of a PT board. As shown in this figure, not all logic elements mounted on an actual PT board can be configured with BS components, and many components (non-BS components) other than BS components are also mounted.

The PT board including the non-BS parts has more undetectable failures and lowers the failure detection rate as compared with the case where all the PT boards are composed of the BS parts, and at the same time, the failure location can be automatically diagnosed. The diagnosis rate will also decrease.

Therefore, in designing the PT board, it is necessary to reduce the test cost of the PT board and improve the quality of shipped products by considering that the diagnostic rate of the PT board test using the BS function is equal to or higher than a predetermined value. I have to.

[0007]

However, extraction of a testable cluster, for example, a region surrounded by a broken line in FIG. 14, in the test of the PT board using the BS function is performed manually. There is a problem in that it takes a lot of man-hours to calculate the diagnostic rate.

If a BS observation point is provided at the location of arrow A in FIG. 14, the area surrounded by the thick line of arrow B can be expanded as a cluster. There has been a problem that it is very difficult to manually find out whether the cluster area can be most effectively expanded and the diagnosis rate can be increased by adding a BS drive point or a BS observation point to the part. The present invention is intended to solve such a problem.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and uses BS to test parts other than BS parts mounted on a printed board and a circuit network. In this case, in a BS cluster test diagnostic rate improvement system that calculates the diagnostic rate and presents a method for improving the diagnostic rate, in order to determine whether a test signal can be propagated, a test signal is applied, a power source is applied, a clock signal is applied to each net. Set a net state consisting of 5 states such as applied, constant voltage applied, and undefined, judge the combination of net states on the input side in each circuit, and apply the test signal to the net on the output side if the test signal can be propagated. The net system from the BS drive point to the BS observation point is extracted as a cluster, and the diagnostic rate is calculated based on all the extracted clusters. The means for providing. This gives P
The diagnostic rate in the T-plate BS cluster test can be calculated easily and easily.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION (1) When a component other than a BS component mounted on a printed board or a circuit network is tested using a BS, calculation of the diagnostic rate and presentation of a method of improving the diagnostic rate are required. In the BS cluster test diagnostic rate improvement system to be performed, the circuit master of the PT board that is the target of the BS cluster test, the BS mounted component that mounts the BS function, the connector component, and the input side such as the resistor, capacitor, SSI, and MSI are easy. It is classified into controllable non-BS parts that can drive the output side to a desired value by giving a simple test pattern series and black box parts that cannot drive the output side to a desired value by giving a simple test pattern series to the input side. Parts classification information, and a parts library in which the pin function information of parts is provided with BS function control enable / disable information, and the part attributes defined in the parts library The additional control information file that stores the information for redefining the information and all the nets connected to the controllable non-BS parts for the controllable non-BS parts have the test pattern from the input side to the output side. A predetermined net such as a test signal application state (O), a power supply application state (G), a clock signal application state (C), a constant voltage application state (W), and an indefinite state (X) to determine whether the signal is propagated to the After setting the states and initializing all net states in these states, for all controllable non-BS parts, the undefined state (X) must be included in the net state combinations connected to the input side. For example, assuming that the test pattern is propagated from the input side to the output side, the net state of the net connected to the output side is set to the test signal applied state (O) or the clock signal applied state (C) to control the non-BS section. Propagate until the net state of all nets connected to is no longer changed, and use the BS for the net system in which the net state of the net system connecting from the BS observation point to the BS drive point is the test signal applied state (O). A cluster calculating means for calculating all the calculated clusters as a cluster area, and outputting the ratio of the number of component pins included in the calculated cluster area to the number of component pins of the entire printed board as a diagnostic rate. And. By this, BS of PT board
The diagnostic rate in the cluster test can be calculated easily and easily.

(2) In the BS cluster test diagnosis rate improvement system described in (1), additional mounting information (remodeling method, BS) of a BS function capable of expanding the cluster area most effectively
A cluster expansion means for presenting the expansion position) is provided. As a result, it becomes possible to easily acquire the additional mounting information of the BS function that effectively expands the cluster area most.

(3) In the BS cluster test diagnosis rate improvement system according to (2), a means for making the most effective modification candidate from the plurality of modification candidates for which the method of additionally mounting the BS function is different, as additional mounting information. To provide. As a result, it becomes possible to easily acquire the additional mounting information of the BS function that effectively expands the cluster area most.

(4) In the BS cluster test diagnostic rate improvement system described in (3), all the paths whose net state is interrupted by the test signal applied state (O) are extracted, and BS observation points are added to the vertices. A means for calculating the increase rate of the diagnosis rate at this time and making the route showing the maximum increase rate a candidate for remodeling is provided. As a result, it is possible to acquire additional mounting information of the BS function that can be effectively expanded in the cluster area with a small number of modifications.

(5) In the BS cluster test diagnostic rate improvement system described in (3), the net state is a path having an indefinite state (X), and all circuits included in the path have an indefinite state (X) in the input pin group. ) Extract all routes with a configuration that has only one pin connected to the net, add the BS drive point to the start point of the extracted route, and the increase rate of the diagnostic rate when adding the BS observation point to the end point. A means for calculating and showing the route showing the maximum increase rate as a candidate for remodeling is provided. As a result, it is possible to acquire additional mounting information of the BS function that can be effectively expanded in the cluster area with a small number of modifications.

(6) In the BS cluster test diagnostic rate improvement system described in (3), the net state is a path having an indefinite state (X), and all circuits included in the path have an indefinite state (X) in the input pin group. ), All the routes with the configuration that only one pin is connected to the net are extracted, and the nets at the vertices of the routes are connected to the same circuit from the extracted routes, and the input side of the connected circuit A route whose net state of the other net is a state other than the indeterminate state (X), and BS driving points are set at a plurality of start points of the extracted route.
A means is provided for calculating an increase rate of the diagnostic rate when a BS observation point is added to the end point and making a route showing the maximum increase rate a remodeling candidate. As a result, it is possible to acquire additional mounting information of the BS function that can be effectively expanded in the cluster area with a small number of modifications.

(7) In the BS cluster test diagnosis rate improvement system described in (2), the additional mounting information of the BS function is rearranged in the descending order of the increase rate of the diagnosis rate, and the additional mounting of a predetermined increase rate or more is performed. Information or additional mounting information in which the number of additional BS functions to be mounted is within a predetermined number of modifications is extracted, and the extracted additional mounting information is used as a modification list to modify the circuit master, and the diagnosis rate and cluster list after modification are displayed. A means for outputting is provided. As a result, it is possible to automatically modify the increase rate of the diagnostic rate to a predetermined value or more or the number of additional BS functions to be mounted within the predetermined value, and easily improve the diagnostic rate in the BS cluster test of the PT board. It becomes possible.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the cluster calculation processing in the BS cluster test diagnostic rate improvement system of the present invention will be described. FIG. 1 is a schematic explanatory diagram of the cluster calculation processing of the present invention, which is composed of a connector, a buffer, an AND, a transmitter, an FF, a BS mounted component, a BS unmounted component, etc. as shown in the upper portion of FIG. Description will be made using a part of the circuit of the PT board.

First, a net state (a part of net attributes) for determining whether or not a test pattern is propagated from the input side to the output side is set in each net constituting this circuit.

The net state includes five states: a test signal applied state (O), a power source applied state (G), a clock signal applied state (C), a constant voltage applied state (W), and an undefined state (X).

The test signal application state (O) is a net state given as an initial value to the BS driving point, and thereafter spreads by the propagation operation. This models the actual test pattern propagating from the pin at the BS drive point to the pin at the BS observation point.

In the power-applied state (G), among the component pins, pins which are determined on the assumption that they are allocated to supply power, so-called power sources, and nets connected to GND pins are fixed in this state from the beginning.

The clock signal application state (C) is a net state given as an initial value to a clock signal pin of a component such as an oscillator or a clock driver, and then spreads by a propagation operation. The net series transmitting the clock signal is considered to be the environment of the propagation path of the test waveform.

In the constant voltage application state (W), when one of the resistors is connected to the net in the power supply state and the other is still in the indefinite state (X), the constant voltage application state is caused by the propagation of the test signal and the clock signal. Updated to (W). afterwards,
Unless a stronger driving factor is generated by propagation, the net in the constant voltage application state (W) is treated as a constant voltage or a constant logic level source.

The indefinite state (X) is a net state given as an initial value to a net other than the net connected to the BS drive point, the clock signal generation point, the power supply pin, etc., and is tested by the propagation of the test signal and the clock signal. The signal application state (O), the clock signal application state (C), or the constant voltage application state (W) is updated. The meaning of the setting of the indefinite state (X) means that the net in this state is not supplied with power and a constant logic level, and the clock signal and the test signal are not propagated.

When the net state defined in this way is set in the upper circuit of FIG. 1, the net connected to the connector serving as the BS component is in the test signal applied state (O) and one of the nets connected to the oscillator is in the test signal applied state (O). The net is in the power applied state (G),
The other net is set to the clock signal applied state (C), and the other nets are set to the undefined state (X).

Next, how the net state thus set is updated by the propagation of the test signal and the clock signal is shown in the lower part of FIG. In the testable net system configuration indicated by arrow A, the test signal is propagated from the input side to the output side of each component, and the test signal is propagated from the BS drive point connector to the BS observation point BS mounted component. , The net state of that path becomes the test signal applied state (O).

On the other hand, the untestable net system structure indicated by the arrow B is a non-BS component that is a non-BS component that cannot drive the output side to a desired value even if a simple test pattern sequence is given to the input side. Therefore, the test signal is not propagated after the net connected to the BS-unmounted component, and the net state remains the undefined state (X).

In this way, the net state is set for the nets that form the circuit, and it is determined whether the test signal and the clock signal are propagated to the output side according to the net state connected to the input side in each component, and the test signal And if the clock signal is propagated, the net state on the output side is updated, and the net system in which the test signal is propagated from the BS drive point to the BS observation point is extracted as a cluster area. The cluster can be easily calculated. Then, it is possible to easily calculate the diagnosis rate by using all of the calculated clusters as the cluster area and using the ratio of the number of component pins included in the calculated cluster area to the number of the component pins of the entire printed board as the diagnosis rate. .

When the net connected to the input side of each component is in the test signal applied state (O) and the clock signal applied state (C), that is, when the test signal and the clock signal are applied to the input side, Whether the test signal and the clock signal are propagated to the output side is determined by the classification information (controllable non-BS parts) set in the parts library.

It is assumed that whether the pin connected to the net is the BS drive point or the BS observation point is set in the pin information of the parts library.

FIG. 2 is a block diagram showing an example of the configuration of the BS cluster test diagnostic rate calculation improving system of the present invention.

In the figure, 1 is a circuit master of a PT board which is a target of the BS cluster test, 2 is a BS mounting component for mounting a BS function, a connector component, a resistor, a capacitor, and SS.
Controllable non-BS parts that can input a simple test pattern sequence to the input side such as I and MSI to drive the output side to a desired value and a simple test pattern sequence to the input side to drive the output side to a desired value A component library in which component classification information that is classified into a black box component that cannot be classified and BS function control enable / disable information is provided in component pin information, and 3 is redefined attribute information of the component that is defined in the component library 2. It is an additional control information file in which information for performing is stored.

Reference numeral 4 refers to the circuit master 1, the component library 2, and the additional control information file 3 to control the non-controllable non-BS components included in the PT board which is the target of the BS cluster test. A test signal application state (O), a power supply application state (G), and a clock signal application state (C) for determining whether the test pattern is propagated from the input side to the output side in all nets connected to the BS component. , Set constant voltage application state (W), indeterminate state (X), and other predetermined net states, and after all net states are initialized in these states, input to all controllable non-BS parts If the undefined state (X) is not included in the combination of net states connected to the output side, it is assumed that the test pattern is propagated from the input side to the output side, and the net state of the net connected to the output side is a test signal. Addition state (O) or clock signal application state (C) is performed until the net states of all nets connected to the controllable non-BS parts do not change, and the net system is connected from the BS observation point to the BS drive point. Is a cluster calculation unit that calculates a net system whose net state is the test signal applied state (O) as a cluster that can be tested using BS.

Further, the cluster calculation unit 4 includes a circuit list including a calculated cluster list which is a route list of all the calculated clusters, a diagnostic rate obtained from the calculated clusters, and a net state set and updated to calculate the clusters. Is output.

Reference numeral 5 denotes a cluster expansion unit that refers to the circuit master output from the cluster calculation unit and outputs additional mounting information (modification method, BS extension position) of the BS function that can most effectively expand the cluster area. is there.

Further, the cluster expansion unit 5 includes a modification list which is additional mounting information of the BS function capable of expanding the cluster area most effectively, a circuit master modified according to the modification list, a cluster list after modification and diagnosis. Output the rate.

FIG. 3 shows a structural example of the parts library. In this component library, in addition to the information provided in general component libraries, such as the number of groups of circuits that make up a component, the number of circuits in the group, circuits, and pin information, the cluster test net state is propagated from the input to the output of the circuit. There is provided classification information used to determine whether or not to allow.

In this example, as the classification information, a BS component is a component whose entire component can be used as a BS driving point or a BS observation point by a tester, and the BS component is a component having a BS function. Are classified as connector parts.

In addition, non-BS parts other than BS parts are used, and the non-BS parts are further controlled such that a simple test pattern sequence such as resistance, capacitor, SSI, MSI can be given to the input side to drive the output side to a desired value. It is classified into a BS component and a black box component (for example, a BS-uninstalled LSI that cannot be easily controlled) in which a simple test pattern sequence cannot be given to the input side to drive the output side to a desired value.
In addition, it is pointed out from the test generation software and the PT board test development group whether or not the control can be easily performed.

In this example, BS function information (BS driving point and BS observation point) is provided in the pin information.

FIG. 4 shows an embodiment of the additional control information file. FIG. 4A is an example in which the pin information is redefined with the pin 1 of the component XX1 (for example, the issuing diode) as the BS observation point. In addition, FIG. 4B is an example in which the frequency input to the clock pin of the component XX2 (for example, a flip-flop) is redefined.

4 (c) to 4 (e) show examples in which the propagating property of the test signal by the clock signal in the component having the clock is different. FIG. 4C shows the case where the clock signal can be controlled by the tester, and the test signal on the input side can be reliably propagated to the output side.

Further, FIG. 4D shows the case where a clock having a cycle sufficiently shorter than the tester cycle is input to the clock signal and a test signal is input to the circuit in the same row as the clock, and the test signal on the input side is sure. It is an example that can be propagated to the output side.

FIG. 4 (e) shows a case where a clock signal having a period slower than the tester period is input to the clock signal, or the state of the circuit changes frequently in the tester period.
In this example, the state on the output side cannot be predicted and the test signal on the input side cannot propagate to the output side.

The operation of the cluster calculator will be described with reference to FIGS. FIG. 5 is a processing flowchart of an embodiment of the cluster calculating unit, FIG. 6 is an explanatory diagram (1) of the cluster calculating method, and FIG. 7 is an explanatory diagram (2) of the cluster calculating method.

The operation will be described below according to the flow of FIG.

Step 501: The circuit master including the BS information, the component library, and the additional control information file are read.

Step 502: Initialize the net states of all the nets of the PT board based on the predefined net states. Note that, for example, in the case of the net configuration shown in FIG. 6A, the net state is initialized as shown in FIG. 6B. It should be noted that this state corresponds to the state immediately after the PT plate is powered on. Further, the definition of the net state is the same as that explained in FIG.

Step 503: For all the controllable non-BS component circuits of the PT board, if all of its input pins are not connected to the net in the indeterminate state (X), the nets connected to its output pins are connected. The state is set to the test signal application state (O). By this processing, as shown in FIG. 6C, the test signal application state (O) of the net connected to the BS drive point is propagated to the output side of the AND circuit. Then, by repeating this processing, the test signal applied state (O) is propagated to the BS connected to the BS observation point or the net connected to the black box component.

Step 504: It is judged whether there is a net whose net state has changed. If there is a changed net, the process returns to step S503, and if there is no changed net, the process proceeds to step S505.

Step 505: Change the net state of the net connected to the BS observation point to the testable state (T). By this processing, the net state of the net connected to the BS observation point is changed as shown in the upper part of FIG.

Step 506: For all the circuits connected to the net in the testable state (T), if the net connected to the input side is the test signal applied state (O), test the net state of the net. Change to possible state (T). By this processing, the net state of the input side of the buffer connected to the net in the testable state (T) is changed to the testable state (T). By repeating this process, the net state of the net up to the BS driving point becomes the testable state (T) as shown in the lower part of FIG. 7D.

Step 507: It is judged whether there is a net whose net state has changed. If there is a changed net, the process returns to step S506, and if there is no changed net, the process proceeds to step S508.

Step 508: Using the BS, the net system in which the net state is in the testable state (T) (the net system in which the net state connecting from the BS observation point to the BS driving point is the test signal applied state (O)) is used. All clusters are calculated as testable clusters and the cluster list is output. Further, all of the calculated clusters are set as cluster areas, and the ratio of the number of component pins included in the calculated cluster area to the number of component pins of the entire printed board is output as a diagnosis rate.

Step 509: Output the circuit master to which the net state is set, that is, the cluster information is added. Then, the process ends.

The operation of the cluster expansion unit will be described with reference to FIGS. 8 is a processing flowchart (1) of an embodiment of the cluster expansion unit, FIG. 9 is a processing flowchart (2) of an embodiment of the cluster expansion unit, FIG. 10 is an explanatory diagram (1) of the cluster expansion method, and FIG. 12 is an explanatory diagram (2) of the cluster expansion method, FIG. 12 is an explanatory diagram (3) of the cluster expansion method, and FIG. 13 is an explanatory diagram (4) of the cluster expansion method.

The operation will be described below with reference to the flow charts of FIGS.

Step S801: The circuit master with cluster information output from the cluster calculator is read.

Step S802: The net system is interrupted by the test signal application state (O) (see FIG. 10).
(Corresponds to a net system like (a)) (FIG. 10)
(Corresponding to the arrow A part in (b)) As a modification method of adding BS observation points, the net state is a net system that is interrupted by the test signal application state (O) and is included in the net system. Calculate the net system with the largest total number of pins (pins that can be newly tested). By adopting this modification method, the net in the test signal applied state (O) of FIG. 10B becomes a net in the testable state (T) as shown in FIG. 10C, that is, the cluster. Can be expanded as.

Step S803: The total number of pins included in the calculated net system is calculated as the expansion effect value A.

Step S804: In the net system in which the net state is indefinite (X), all the circuits located between the constituent nets have only one connection to the net in the indefinite state (X) in the input pin group. A net system (Fig. 11
The BS observation point is located at the apex (corresponding to the part of arrow B in FIG. 11B) corresponding to the net system indicated by arrow C in FIG. 11A, and the foot of the net system (arrow in FIG. 11B). (Corresponding to the part A)), a modification is made to add a BS drive point, and all the circuits located between the constituent nets in the net system in which the net state is indefinite (X) are indefinite in the input pin group. A net system having a configuration having only one connection to the net (X) and having the largest total number of pins (new testable pins) included in the net system is calculated. By adopting this modification method, the nets in the indefinite state (X) in the area indicated by the arrow C in FIG. 11 (b) become all nets in the testable state (T) as shown in FIG. 11 (c). That is, it becomes possible to expand as a cluster.

Step S805: (the calculated total number of pins included in the net system / 2) is calculated as the expansion effect value B. Here, 2 means the number of modifications.

Step S806: It is determined whether the expansion effect value A and the expansion effect value B are both 0. If both are 0, the process proceeds to step S901, and if not 0, step S80.
Proceed to 7.

Step S807: It is determined whether the expansion effect value A is larger than the expansion effect B. If it is larger, the process proceeds to step S808, and if it is not larger, the process proceeds to step S809.

Step S808: The diagnosis rate in the case of adopting the modification method of the expansion effect value A is calculated, and the modification method (the position of the BS terminal to be expanded), the expansion effect value, the diagnosis rate, etc. are stored in the temporary storage section. In this example, the modified data recorded in the temporary storage unit has the structure shown in FIG. Then, the process returns to step S802.

Step S809: The method of modifying the extension effect value B is stored in the temporary storage section. In this example, the modified data recorded in the temporary storage unit has the structure shown in FIG. Then, the process returns to step S802.

Step S901: The modification data stored in the temporary storage section is sorted in the descending order of the expansion effect value, and data having an expansion effect value equal to or higher than a predetermined value is modified. Until the number reaches the maximum, the extraction method will be selected in descending order of increasing effect value.

Step S902: The extracted modification method is output as a modification list.

Step S903: All modifications are made to the circuit master according to the modification list.

Step S904: A cluster calculation process (process of the cluster calculation unit shown in FIG. 5) is performed for the modified circuit master, and a cluster list and a diagnostic rate are output. Then, the process ends.

In this example, the remodeling method having the large addition effect value is selected from the two remodeling methods of step S802 and step S804, but the remodeling method having the large addition effect value is selected from the two or more remodeling methods. You may make it select.

For example, when the net system indicated by the arrow C in FIG. 11 (a) is a single X net system, the input in a circuit in which two single X net systems are connected as shown in FIG. 13 (a). When the net state other than the single X net system connected to the side is the test signal applied state (O), the output side (arrow shown in FIG. 13B) of the circuit to which the two single X net systems are connected is indicated by the arrow. A modification method is adopted in which a BS observation point is added to B) and a BS driving point is added to the input side (arrow A) of two single X net systems. By this modification method, the net system indicated by the arrow D in FIG. 13C becomes a testable net (T), and cluster expansion with a high expansion effect value can be performed.

[0073]

The present invention is carried out in the form as described above and has the following effects.

A model for determining whether or not the test signal can propagate in the circuit is constructed for the diagnostic rate in the test of the PT board using the BS function, and the net series connecting from the BS observation point to the BS drive point is calculated as a cluster. And PT
The ratio of the total number of pins in the cluster to the total number of pins on the plate is calculated as the diagnostic rate. As a result, P using the BS function
It is possible to easily and easily calculate the diagnostic rate of the T-plate test.

It should be noted that the calculated diagnostic rate matches the diagnostic rate with the cluster route group based on the result of manual cluster extraction that has conventionally required a great deal of man-hours.

Further, this cluster calculating means is simple and efficient, and can be sufficiently realistically adapted to a recent PT board including a large number of LSIs having a huge gate scale.

Further, it becomes possible to specifically present the most effective additional mounting information of the BS function which could not be grasped manually by the cluster expanding means.

Further, since the cluster list calculated by the cluster calculating means and the cluster expanding means can be utilized as basic information for creating the test program for the PT board, it is possible to greatly save the test program creating process. Becomes

The modification list calculated by the cluster expanding means can be used as it is for changing the PT board design data, and the PT board DFT (design for easy test) can be used.
It is possible to significantly shorten the process.

At the same time, the cost reduction and the high quality design of the PT plate at the upstream can be realized.

[Brief description of drawings]

FIG. 1 is a schematic explanatory diagram of a cluster calculation process of the present invention.

FIG. 2 is a configuration block diagram of a BS cluster test diagnostic rate improvement system of the present invention.

FIG. 3 is a diagram showing a configuration example of a parts library.

FIG. 4 is a diagram showing an example of an additional control information file.

FIG. 5 is a processing flowchart of an embodiment of a cluster calculation unit.

FIG. 6 is an explanatory diagram (1) of a cluster calculation method.

FIG. 7 is an explanatory diagram (2) of the cluster calculation method.

FIG. 8 is a processing flowchart (1) of one embodiment of the cluster expansion unit.

FIG. 9 is a processing flowchart (2) of an embodiment of the cluster expansion unit.

FIG. 10 is an explanatory diagram (1) of a cluster expansion method.

FIG. 11 is an explanatory diagram (2) of the cluster expansion method.

FIG. 12 is an explanatory diagram (3) of the cluster expansion method.

FIG. 13 is an explanatory diagram (4) of the cluster expansion method.

FIG. 14 is a diagram showing a configuration example of a BS function test of a PT board.

[Explanation of symbols]

1 circuit master 2 parts library 3 Additional control information file 4 Cluster calculator 5 Cluster extension

Claims (7)

[Claims] 1. A BS cluster test diagnostic for calculating a diagnostic rate and presenting a method for improving the diagnostic rate when testing a component or a circuit network other than a BS component mounted on a printed circuit board using a BS. In the rate improvement system, the circuit master (1) of the PT board that is the target of the BS cluster test, the BS mounting component equipped with the BS function, the connector component,
Controllable non-BS parts that can input a simple test pattern series such as resistors, capacitors, SSI and MSI to drive the output side to a desired value, and a simple test pattern series to the input side to output the desired side The component library (2) that includes component classification information that is classified as a black box component that cannot be driven to the value of, and pin function information that indicates whether or not the BS function can be controlled, and a component library that is defined in the component library. Additional control information file (3) that stores information for redefining attribute information
Then, for the controllable non-BS parts, the test signal application state (O) is applied to determine whether the test pattern is propagated from the input side to the output side for all nets connected to the controllable non-BS parts. , Predetermined power supply state (G), clock signal application state (C), constant voltage application state (W), indeterminate state (X), etc. are set, and all net states are initially set in these states. After being controlled, all controllable non-BS
If the undefined state (X) is not included in the combination of the net states connected to the input side for the part, the test pattern is propagated from the input side to the output side, and the net state of the net connected to the output side is changed. It can be controlled by setting the test signal application state (O) or clock signal application state (C).
Propagate until the net states of all the nets connected to the S component have stopped changing, and the net state of the net system connecting from the BS observation point to the BS drive point is the test signal applied state (O). A cluster that calculates as a cluster that can be tested by using, calculates all clusters as the cluster area, and outputs the ratio of the number of component pins included in the calculated cluster area to the total number of component pins as the diagnostic rate. A BS cluster test diagnosis rate improvement system, characterized in that a calculation means is provided. 2. The BS cluster test diagnostic rate improvement system according to claim 1, further comprising cluster expansion means for presenting additional mounting information of a BS function capable of expanding the cluster area most effectively. Diagnostic rate improvement system. 3. The BS cluster test diagnostic rate improvement system according to claim 2, further comprising means for selecting the most effective remodeling candidate as the additional mounting information from a plurality of remodeling candidates having different methods for additionally mounting the BS function. A BS cluster test diagnostic rate improvement system characterized by being provided. 4. The BS cluster test diagnostic rate improvement system according to claim 3, wherein all the paths whose net state is interrupted by the test signal applied state (O) are extracted, and BS observation points are added to the vertices. BS which is characterized in that means for calculating the rate of increase in the diagnostic rate of the
Cluster test diagnosis rate improvement system. 5. The BS cluster test diagnostic rate improvement system according to claim 3, wherein the net state is a path having an indefinite state (X), and all circuits included in the path have an indefinite state (X) in the input pin group. Extracts all routes with a configuration that has only one pin connected to the net, and BS at the start point of the extracted route.
A BS cluster test diagnostic rate improvement system, characterized in that means for calculating an increasing rate of a diagnostic rate when a BS observation point is added to a driving point and an end point and providing a route showing the maximum increasing rate as a candidate for remodeling. 6. The BS cluster test diagnostic rate improvement system according to claim 3, wherein the net state is a path having an undefined state (X), and all circuits included in the path have an undefined state (X) in the input pin group. All the routes with the configuration that only one pin is connected to the net are extracted, the nets at the vertices of the routes are connected to the same circuit from the extracted routes, and the input side of the connected circuit is The increase rate of the diagnostic rate when a route whose other net state is other than the undefined state (X) is extracted and BS driving points are added to a plurality of start points of the extracted routes and BS observation points are added to the end points BS provided with means for calculating and showing a route showing the maximum increase rate as a candidate for remodeling
Cluster test diagnosis rate improvement system. 7. The BS cluster test diagnostic rate improvement system according to claim 2, wherein the additional mounting information of the BS function is rearranged in the descending order of increasing rate of the diagnostic rate, and the additional mounting information equal to or higher than a preset predetermined increasing rate. , Or the number of additional mountings of the BS function is extracted within the predetermined number of modifications, the extracted additional mounting information is used as a modification list to modify the circuit master, and the diagnosis rate and cluster list after modification are output. BS cluster test diagnostic rate improvement system, characterized in that it is provided with means for performing.