JP2003218966A - Demodulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulation circuit with a simple configuration. <P>SOLUTION: The demodulation circuit characterized in that it includes: a control terminal to which an amplitude modulation signal of a binary digital signal is applied; a first terminal to be controlled for outputting a demodulated digital signal; and a second terminal to be controlled connected to a reference level, wherein the first and second terminals to be controlled configure a terminal pair to be controlled between which are switched by a signal given to the control terminal; a semiconductor switching element, wherein a switching delay time has a characteristic of a length unable to track a change in an amplitude modulation carrier signal, a turn-on delay time in the switching delay time has a characteristic of shorter than a turn-off delay time, switching is attained at a prescribed bias voltage; and a resistive element for interconnecting the first terminal to be controlled and a part having a potential with respect to the reference potential. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit for an amplitude modulation signal.

[0002]

2. Description of the Related Art The amplitude modulation method is one of signal modulation methods in digital communication. In this method, the amplitude of the carrier signal is changed according to the signal amplitude. Figure 7
When the binary digital signal Sd shown in (a) is amplitude-modulated, the digital signal Sd1 representing "1" and the digital signal Sd0 representing "0" are respectively determined by the presence or absence of a carrier signal as shown in FIG. 7B. Represented amplitude modulation signal Sm
1 and Sm0.

The demodulation of the amplitude modulation signal Sm is generally performed in the order of input terminal 5 → filter circuit 7 → amplification circuit 8 → demodulation circuit 9 → comparison circuit 10 → output terminal 5 as shown in FIG. . First, the filter circuit 7 removes unnecessary noise components of the amplitude modulation signal Sm input to the input terminal 5. Then, the amplifier circuit 8 amplifies the amplitude of the amplitude modulation signal Sm. Then, the demodulation circuit 9 extracts the binary digital signal Sd from the amplified amplitude modulation signal Sm. Further, the comparator circuit 10 shapes the waveform of the binary digital signal Sd by removing noise and adjusting the voltage level of the extracted binary digital signal Sd, and outputs the signal from the output terminal 6.

As the demodulation circuit 9, the diode demodulation circuit shown in FIG. 9 and the peak hold circuit shown in FIG. 10 are used.

The diode demodulation circuit of FIG. 9 comprises a diode D, a resistor R and a capacitor C1. This circuit inputs the amplitude modulation signal Sm input to the input terminal 5 to the diode D, passes only the forward signal of the diode D, and the capacitor C1 repeatedly charges and discharges to output the digital signal Sd. It is taken out to the terminal 6.

On the other hand, the peak hold circuit of FIG. 10 is constructed by using two operational amplifiers (U1A and U1B) in addition to the configuration of the diode demodulation circuit of FIG.
By using an operational amplifier, this circuit compensates for the forward voltage drop of the diode D and enables accurate demodulation operation.

[0007]

However, although the diode demodulation circuit of FIG. 9 has a simple structure, the forward voltage drop of the diode D occurs, so that it is possible to demodulate a small amplitude signal having an amplitude of about several hundred mV. Is not suitable for.

On the other hand, in the peak hold circuit of FIG. 10, an operational amplifier is used to compensate for the forward voltage drop of the diode D, so that a small amplitude signal can be demodulated. However, since the operational amplifier is used as a circuit component, the demodulation circuit becomes expensive. Become. Further, when the carrier frequency of the amplitude modulation becomes high, the slew rate becomes high, and a high-bandwidth operational amplifier is required, so that the demodulation circuit becomes expensive.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a demodulation circuit which performs a demodulation operation with a simple structure.

[0010]

The invention according to claim 1 is
A control terminal to which the amplitude modulation signal of the binary digital signal amplitude-modulated by the amplitude modulation circuit is input, a first controlled terminal to output the demodulated digital signal, and a second control terminal connected to the reference potential. A controlled terminal, and the first controlled terminal and the second controlled terminal constitute a controlled terminal pair whose terminals are opened and closed by a signal input to the control terminal, and have a turn-on delay time. And a turn-off delay time, the switching delay time has a characteristic of a length that does not follow the change of the carrier signal of the amplitude modulation, and the switching delay time has a characteristic that the turn-on delay time is shorter than the turn-off delay time. , A semiconductor switching element which is given a predetermined bias voltage and is capable of switching operation, the first controlled terminal, and a potential difference with respect to the reference potential. A resistive element for connecting the portion,
It is characterized by being a demodulation circuit having.

According to a second aspect of the present invention, in the structure according to the first aspect, the first controlled terminal of the semiconductor switching element has a signal inverting means.

According to a third aspect of the present invention, in the structure according to the first or second aspect, the input terminal of the semiconductor switching element and the control terminal of the semiconductor switching element compensate the temperature characteristic of the semiconductor switching element. It is characterized by having a temperature compensation means.

According to a fourth aspect of the present invention, in the structure according to the third aspect, the temperature compensating means includes a control terminal, a first controlled terminal, and a second controlled terminal connected to the reference potential. A semiconductor switching element having a temperature characteristic similar to that of the semiconductor switching element, the control terminal and the first controlled terminal being short-circuited, the first controlled terminal of the semiconductor switching element and the reference A first resistance element that connects a portion having a potential difference with respect to the potential and a second resistance element that connects the control terminal of the semiconductor switching element and the first controlled terminal of the semiconductor switching element. It is characterized by having.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) Next, a first embodiment of the present invention will be described with reference to FIG.

In the semiconductor switching device 1 (for example, N-channel metal oxide field effect transistor), the gate terminal 1a which is the control terminal thereof is the input terminal 5 of the demodulation circuit, and the drain terminal 1b which is the first controlled terminal is the demodulation circuit. The source terminal 1c, which is the second controlled terminal, is connected to the output terminal 6 of the circuit and the ground of the reference potential.

The semiconductor switching device 1 has a switching delay time of a length that does not follow a change in the carrier signal of amplitude modulation, and has a characteristic that the turn-on delay time is shorter than the turn-off delay time in the switching delay time. There is. Further, the semiconductor switching element 1 has a gate-
A predetermined bias voltage Vb is applied between the sources to enable the operation.

The resistance element 2 connects the DC voltage terminal V and the drain terminal 1b of the semiconductor switching element 1.
That is, the first embodiment constitutes a source-grounded switching circuit. Here, the semiconductor switching element 1
Between the gate-source voltage VGS and the output voltage V of the demodulation circuit
The relationship with OUT has a switching characteristic as shown by the curve Csw in FIG. 2, and the operating point P is defined by the bias voltage Vb applied between the gate and the source.

Next, the operation of the demodulation circuit will be described with reference to FIG. Here, the switching delay time of the semiconductor switching element 1 is about 1.2 μs, the turn-on delay time is about 0.2 μs, and the turn-off delay time is about 1.0 μs.

First, when the amplitude modulation signal Sm0 representing "0" is input to the input terminal 5, the output voltage So becomes So0.
As shown in, the voltage is a voltage obtained by subtracting the drain current determined by the bias voltage Vb between the gate and the source and the voltage drop generated by the resistance element 2 from the voltage VCC of the DC voltage terminal V.

On the other hand, when the amplitude modulation signal Sm1 representing "1" is input, the carrier frequency is low (for example, 10k).
3) and the switching delay time of the semiconductor switching element 1 is in a range that follows the change of the carrier signal of the amplitude modulation signal Sm, the output signal So is as shown in FIG.
It becomes like So1. That is, when the input signal is changing in the positive direction, the semiconductor switching element 1 is on,
When the output signal So becomes substantially zero and the input signal changes in the negative direction, the semiconductor switching element 1 is off, and the output signal So approaches the voltage VCC of the DC voltage terminal V. This is the operation of the switching circuit.

However, when the carrier frequency becomes high (for example, about 100 kHz) and the switching delay time of the semiconductor switching element 1 exceeds the range in which the change of the carrier signal of the amplitude modulation signal Sm can be followed, the amplitude modulation signal Sm.
The switching delay time becomes non-negligible compared with the period of the carrier signal. That is, since a phenomenon of switching between ON and OFF occurs during the change of the carrier signal, sufficient switching is not performed, and the amplitude of the output signal So is limited and becomes small.

Since the turn-on delay time of the semiconductor switching device 1 is shorter than the turn-off delay time,
The semiconductor switching element is more likely to turn on from off than on to off. In other words, in the output signal, the change to the reference potential side is faster than the change to the voltage VCC side of the DC voltage terminal, so the amplitude center of the output signal So moves to the reference potential side. That is, the amplitude becomes small and the center of the amplitude moves to the reference potential side as in So1 in FIG.

When the carrier frequency further increases (for example, about 1 MHz), the influence of the switching delay time increases, so that the amplitude of the output signal So becomes extremely small and the center voltage of the amplitude becomes substantially zero. Eventually, the output signal So from the demodulation circuit becomes as shown by So1 in FIG.

Looking at the output signal So of FIG. 3 (c), when the input signal is the digital signal Sd1 representing "1", the potential is low, and when it is the digital signal Sd0 representing "0", the potential is high. It can be seen that the demodulation circuit extracts the binary digital signal from the amplitude modulation signal Sm of the binary digital signal.

As described above, in the first embodiment,
Since the switching circuit using the semiconductor switching element 1 whose turn-on delay time is shorter than the turn-off delay time is used, it is possible to handle an amplitude modulation signal of a small amplitude without using an operational amplifier, and to construct an inexpensive demodulation circuit. it can.

Although the signal extracted by this demodulation circuit is inverted with respect to the original digital signal, whether the signal is inverted at the time of waveform shaping in the comparator 10 connected to the subsequent stage of the demodulation circuit. , By changing "1" to "0" and "0" to "1" in the signal processing system,
It can be used without inconvenience.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG.

This device has a signal inverting means (eg, an inverter) between the drain terminal 1b which is the first controlled terminal of the semiconductor switching element 1 and the output terminal 6 of the demodulation circuit in the configuration of the first embodiment. The other components are the same as those of the first embodiment.

As described in the description of the first embodiment, the digital signal taken out by the demodulation circuit may be inverted as compared with the original digital signal, but by providing the signal inversion means 3, the inversion is performed. The signal is restored and the digital signal at the time of modulation can be output as it is.

This makes it possible to construct a general-purpose demodulation circuit that does not need to consider the influence of signal inversion in post-processing.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG.

In this configuration, the temperature compensating means 4 for compensating the temperature characteristic of the semiconductor switching element 1 is provided in the configuration of the first embodiment, and the capacitor C for cutting the DC voltage of the input signal is provided at the input terminal. Is.

The temperature compensating means 4 includes a semiconductor switching element 4a, a first resistance element 4b, and a second resistance element 4c.
It is composed by.

This semiconductor switching element 4a is of the same kind as the semiconductor switching element 1 (for example, an N-channel metal oxide film field effect transistor), and has a gate terminal 4aa which is a control terminal and a drain which is a first controlled terminal. The terminal 4ab is short-circuited, and the source terminal 4ac that is the second controlled terminal is connected to the ground that is the reference potential. In addition, the semiconductor switching element 4a
Has a similar temperature characteristic by selecting a device housed in the same package as the semiconductor switching device 1. The semiconductor switching element 4a and the semiconductor switching element 1 are installed in the same package or are connected to each other by a heat radiating plate or the like so as to have substantially the same temperature.

The first resistance element 4b is the drain terminal 4a which is the first controlled terminal of the semiconductor switching element 4a.
b is connected to the DC voltage terminal V.

The second resistance element 4c is the drain terminal 4a which is the first controlled terminal of the semiconductor switching element 4a.
b and the gate 1a which is the control terminal of the semiconductor switching element 1 are connected.

Next, the operation of this demodulation circuit will be described.

First, when the voltage VCC at the DC voltage terminal is applied to the temperature compensating means 4, the semiconductor switching element 4a.
Drain current ID of the DC voltage terminal V of the voltage VCC,
Using the resistance value R2 of the first resistance element 4b and the drain-source voltage VDS, ID = (VCC-VDS) / R2
Becomes On the other hand, since the gate and the drain are short-circuited, the drain-source voltage VDS and the gate-source voltage VGS are VDS = VGS. That is, the drain current ID is ID = (VCC-VGS) / R2.
Further, the semiconductor switching element 4a has a characteristic of the semiconductor switching element such that ID- as shown by a curve Cd in FIG.
Since it has the VGS characteristic, the intersection of the two characteristics shown in FIG. 6 becomes the operating point P1. At this time, since the drain-source voltage is equal to the gate-source voltage, the semiconductor switching element 4a has an on-voltage. This drain-source voltage is the resistance value R of the first resistance element 4b.
Adjustment can be performed by changing 2 and the drain-source voltage decreases as the resistance value R2 increases.

On the other hand, since the semiconductor switching element 1 and the semiconductor switching element 4a are of the same kind and have similar temperature characteristics, the semiconductor switching element 4
The drain-source voltage of a is near the ON voltage of the semiconductor switching element 1. Therefore, the temperature compensation means 4
The semiconductor switching device 1 operates so that a voltage near the ON voltage of the semiconductor switching device 1 is always applied to the semiconductor switching device 1 as a bias voltage via the resistance device 4c.

The demodulation operation of the amplitude modulation signal by the semiconductor switching element 1 and the resistance element 2 is the same as the operation described in the first embodiment. However, when the temperature of the semiconductor switching element 1 rises due to the heat generation of the semiconductor switching element 1 or the rise of the ambient temperature, the drain current with respect to the gate-source voltage increases and the voltage drop in the resistance element 2 increases, so that the output The voltage drops. That is, the output voltage fluctuates depending on the temperature of the semiconductor switching element 1, and the circuit becomes unstable in an environment where the temperature changes greatly.

However, the semiconductor switching element 4a
Are in the same package as the semiconductor switching element 1 or are connected to each other by a heat sink or the like, and have almost the same temperature as the semiconductor switching element 1. As the temperature of the semiconductor switching element 1 rises, the semiconductor switching element 4a Temperature also rises.

Therefore, the I of the semiconductor switching element 4a is
The D-VGS characteristic changes from the curve Cd in FIG. 6 to a curve Cdt. Further, the semiconductor switching element 4a is
Since the semiconductor switching element 1 has similar temperature characteristics, the rate of change in the ID-VGS characteristics is almost the same as the change in characteristics of the semiconductor switching element 1.

Due to this change in characteristics, the operating point of the semiconductor switching element 4a changes to P2, and the drain-source voltage of the semiconductor switching element 4a decreases. Therefore, the bias voltage of the semiconductor switching element 1 is reduced and the drain current of the semiconductor switching element 1 is reduced, so that the output voltage is reduced. In other words, the temperature compensating means 4 uses the semiconductor switching element 1 due to temperature rise
The bias voltage of the semiconductor switching element 1 is changed so as to cancel the increase in the drain current of the semiconductor switching element 1. On the contrary, when the temperature decreases, a phenomenon opposite to the above occurs, and therefore the temperature compensating means 4 changes the bias voltage of the semiconductor switching element 1 so as to cancel the decrease in the drain current. That is, the temperature compensating means 4 operates as a temperature compensating circuit that automatically follows a temperature change.

As described above, in the third embodiment,
Since the temperature compensating means 4 is configured by including the semiconductor switching element 4a having a temperature characteristic similar to that of the semiconductor switching element 1 used for the demodulation operation, the temperature compensation is automatically performed even when the temperature of the semiconductor switching element 1 changes. Therefore, a demodulation circuit that performs stable operation can be configured.

The semiconductor switching element may use not only the N-channel metal oxide film field effect transistor but also other field effect transistors and bipolar transistors.

Although the switching delay time and the carrier frequency have been described by using numerical values, these numerical values can be changed without departing from the spirit of the invention.

[0047]

According to the invention of claim 1, a control terminal to which an amplitude modulation signal of a binary digital signal amplitude-modulated by the amplitude modulation circuit is inputted, and a first demodulated digital signal is outputted. It has a controlled terminal and a second controlled terminal connected to a reference potential, and the first controlled terminal and the second controlled terminal are connected between terminals by a signal input to the control terminal. A switching delay time, which constitutes a controlled terminal pair to be opened and closed, and which is composed of a turn-on delay time and a turn-off delay time, has a characteristic of a length that does not follow a change in a carrier signal of amplitude modulation, and among the switching delay times, A semiconductor switching device having a characteristic that a turn-on delay time is shorter than a turn-off delay time, and a predetermined bias voltage is applied to enable a switching operation; and the first controlled device. Since it has a terminal and a resistance element that connects a portion having a potential difference with respect to the reference potential, it is possible to configure a demodulation circuit capable of handling an amplitude modulation signal of a small amplitude without using an operational amplifier. Play. Therefore, it is possible to provide a demodulation circuit that performs a demodulation operation with a simple configuration.

According to the second aspect of the present invention, the first controlled terminal of the semiconductor switching element has the signal inverting means. Therefore, a general-purpose demodulation circuit which does not need to consider the influence of the signal inversion in the post-processing is provided. The effect is that it can be configured.

According to the invention of claim 3, since the control terminal of the semiconductor switching element has a temperature compensating means for compensating the temperature characteristic of the semiconductor switching element, even when the temperature of the semiconductor switching element changes. It is possible to construct a demodulation circuit that performs stable operation.

According to the invention of claim 4, the temperature compensating means has a control terminal, a first controlled terminal, and a second controlled terminal connected to the reference potential. The terminal and the first controlled terminal are short-circuited, and a semiconductor switching element having temperature characteristics similar to those of the semiconductor switching element, and a potential difference between the first controlled terminal of the semiconductor switching element and the reference potential. Since the first resistance element for connecting to the portion and the second resistance element for connecting the control terminal of the semiconductor switching element and the first controlled terminal of the semiconductor switching element are included, Even if a temperature change occurs, it is possible to configure a demodulation circuit that automatically performs temperature compensation and performs stable operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a demodulation circuit according to a first embodiment.

FIG. 2 is a switching characteristic diagram of the demodulation circuit according to the first embodiment.

FIG. 3 is a waveform diagram showing an input / output waveform of the demodulation circuit in the first embodiment, in which a carrier frequency of amplitude modulation is
(A) shows a low frequency and (b) and (c) show a high frequency.

FIG. 4 is a circuit diagram of a demodulation circuit according to a second embodiment.

FIG. 5 is a circuit diagram of a demodulation circuit according to a third embodiment.

FIG. 6 is a characteristic diagram showing operating points of a semiconductor switching element of the temperature compensating means in the third embodiment.

7A and 7B are explanatory diagrams showing amplitude modulation of a binary digital signal, FIG. 7A is a waveform diagram of a binary digital signal, and FIG. 7B is a waveform diagram of the amplitude modulated signal.

FIG. 8 is a connection diagram illustrating a procedure of demodulation processing.

FIG. 9 is a circuit diagram showing a diode demodulation circuit.

FIG. 10 is a circuit diagram showing a peak hold circuit.

[Explanation of symbols]

1 Semiconductor switching element 1a Control terminal 1b First controlled terminal 1c Second controlled terminal 2 resistance element 3 Signal inversion means 4 Temperature compensation means 4a Semiconductor switching element 4aa control terminal 4ab first controlled terminal 4ac Second controlled terminal 4b First resistance element 4c Second resistance element 5 input terminals 6 output terminals V DC voltage terminal Sd digital signal Sm amplitude modulation signal So output signal

Continued front page    (72) Inventor Takeyuki Suzuki             1048, Kadoma, Kadoma-shi, Osaka Matsushita Electric Works Co., Ltd.             Inside the company (72) Inventor Atsuhisa Nishimura             1048, Kadoma, Kadoma-shi, Osaka Matsushita Electric Works Co., Ltd.             Inside the company F-term (reference) 5K004 AA03 DF04 DG02

Claims (4)

[Claims] 1. A control terminal to which an amplitude modulation signal of a binary digital signal amplitude-modulated by an amplitude modulation circuit is input, a first controlled terminal for outputting a demodulated digital signal, and a reference potential. And a second controlled terminal, wherein the first controlled terminal and the second controlled terminal are
A controlled terminal pair that opens and closes between terminals according to the signal input to the control terminal, and the switching delay time consisting of turn-on delay time and turn-off delay time is a characteristic of a length that does not follow changes in the carrier signal of amplitude modulation. A semiconductor switching element having a characteristic that a turn-on delay time is shorter than a turn-off delay time among the switching delay times, and a predetermined bias voltage is applied to enable a switching operation; 2. A demodulation circuit, comprising: a controlled element that connects the controlled terminal to a portion having a potential difference with respect to the reference potential. 2. The demodulation circuit according to claim 1, wherein the first controlled terminal of the semiconductor switching element has a signal inverting means. 3. The control terminal of the semiconductor switching element has a temperature compensating means for compensating the temperature characteristic of the semiconductor switching element.
The described demodulation circuit. 4. The temperature compensating means includes a control terminal and a first terminal.
Controlled terminal and a second controlled terminal connected to the reference potential, the control terminal and the first controlled terminal are short-circuited, and have temperature characteristics similar to those of the semiconductor switching element. A semiconductor switching element, a first resistance element connecting a first controlled terminal of the semiconductor switching element and a portion having a potential difference with respect to the reference potential, a control terminal of the semiconductor switching element, and the semiconductor switching element 4. The demodulation circuit according to claim 3, further comprising: a second resistance element connected to the first controlled terminal of.