JP5601983B2 - Bias circuit - Google Patents

Description

  The present invention relates to a bias circuit that uses a high-frequency semiconductor element as a receiving amplifier, and more particularly to a technique for preventing destruction at the time of excessive input to the receiving amplifier and a technique for improving the electrical characteristic return speed after over-input is eliminated.

  Conventionally, as a bias circuit for a radar receiver module, a detector circuit and an amplitude limiter circuit have been provided in front of the receiving transistor, and the signal level detected by the detector circuit is compared by a comparator. There has been proposed a device including a control circuit that protects against being applied (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 4-130285, FIG.

  According to the configuration of the above-mentioned Patent Document 1, the conventional bias circuit is provided with the detection circuit and the amplitude limiting circuit in the preceding stage of the receiving transistor. There was a problem that the noise performance deteriorated. Further, since a complicated circuit including a comparator is required, there is a problem that the cost of the entire system increases.

  The present invention has been made to solve the above-described problems, and provides a bias circuit capable of preventing a receiving transistor from being destroyed by an excessive input with a simple configuration without deteriorating reception noise performance. For the purpose. It is another object of the present invention to provide a bias circuit that improves the time required to return to a steady operation after over-input is eliminated.

A bias circuit according to the present invention is a bias circuit used for a receiving amplifier having no over-input protection circuit, the gate bias circuit being connected to a gate terminal of a receiving transistor constituting the receiving amplifier, and a receiving circuit. And a drain bias circuit connected to the drain terminal of the transistor for use, and the gate bias circuit includes a change detection means for detecting a change in the gate current or gate voltage of the receiving transistor at the time of over-input and generating a change signal. And a drain bias circuit configured to reduce a drain output voltage to the receiving transistor in response to a change signal at the time of over-input , and the drain bias circuit is a buffer to which a change signal at the time of over-input is input The buffer circuit includes an output voltage value when a change signal is input. It is intended to switch from voltage to 0V.

  According to the present invention, in a bias circuit that protects a receiving amplifier, it is possible to prevent destruction of the receiving amplifier at the time of over-input without impairing noise performance by a small and simple configuration that does not use an over-input protection circuit. .

1 is a circuit configuration diagram showing a bias circuit according to a first embodiment of the present invention. It is a circuit block diagram which shows the bias circuit based on Embodiment 2 of this invention. It is a circuit block diagram which shows the bias circuit based on Embodiment 3 of this invention. It is a circuit block diagram which shows the bias circuit based on Embodiment 4 of this invention. It is a circuit block diagram which shows the bias circuit based on Embodiment 5 of this invention. It is a circuit block diagram which shows the bias circuit based on Embodiment 6 of this invention. It is explanatory drawing which shows the example of calculation in Embodiment 6 of this invention. It is an example of calculation in Embodiment 6 of this invention. It is a top view which shows the mounting state of the bias circuit based on Embodiment 7 of this invention. It is a top view which shows the inside of the broken-line frame in FIG. 9 in detail. It is explanatory drawing which shows the relationship between the element breakdown voltage in Embodiment 9 of this invention, and maximum withstand power.

Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram showing a bias circuit according to Embodiment 1 of the present invention together with a receiving circuit.
1, a receiving circuit to which the present invention is applied includes a receiving antenna 1 that acquires a received signal, a receiving transistor 2 that constitutes a receiving amplifier, a matching circuit 3 that also serves as a bias line, and an MIM (Metal Insulator Metal). ) A high-frequency short-circuit capacitor 4 composed of a capacitor and a reception signal output terminal 5 are provided.

In this case, the reception transistor 2 that amplifies the reception signal does not have an over-input protection circuit.
In the receiving transistor 2, the gate terminal is connected to the receiving antenna 1 and one matching circuit 3, the drain terminal is connected to the other matching circuit 3 and the received signal output terminal 5, and the source terminal is connected to the ground. Yes.
The other end of each matching circuit 3 is connected to the ground via an individual high-frequency short-circuit capacitor 4.

  In addition, the bias circuit according to the first embodiment of the present invention has a gate voltage application terminal 6 to which a gate bias voltage Vgg (= −2 [V]) is applied and a drain bias voltage Vdd (= 10 [V]) applied. A drain voltage application terminal 7, a gate bias circuit 8 that applies a gate voltage Vg to the gate terminal via one matching circuit 3, and a drain that applies a drain voltage Vd to the drain terminal via the other matching circuit 3 And a bias circuit 9. In addition, the value in the above parentheses is an example value, and may take other values. The same applies hereinafter.

  The gate bias circuit 8 includes a change detection means (not shown in FIG. 1) that detects a change in the gate current Ig flowing in the gate bias circuit 8 and generates a change signal, and is configured so that the drain bias circuit 9 can be feedback-controlled. ing.

  In the following description, in order to distinguish from the gate bias voltage Vgg and the drain bias voltage Vdd supplied to the gate bias circuit 8 and the drain bias circuit 9, it is actually applied to the gate bias circuit 8 and the drain bias circuit 9. The bias voltage is simply referred to as the gate voltage Vg and the drain voltage Vd.

  According to the configuration of the receiving circuit of FIG. 1, since the receiving antenna 1 and the receiving transistor 2 are directly connected, the receiving transistor is added without adding additional noise to the signal received by the receiving antenna 1. 2 can be amplified, and excellent noise performance can be realized.

Further, in the bias circuit of FIG. 1, since the gate bias circuit 8 and the drain bias circuit 9 are grounded via the high frequency short-circuit capacitor 4, respectively, a reception amplification unit composed of the reception transistor 2 and the matching circuit 3 is provided. On the other hand, the high-frequency signal path is separated.
Therefore, a noise signal generated in the gate bias circuit 8 and the drain bias circuit 9 is not amplified by the receiving transistor 2.

Next, the operation at the time of excessive input according to Embodiment 1 of the present invention shown in FIG. 1 will be described.
When an excessive input signal is input from the receiving antenna 1 to the receiving transistor 2, the gate current of the receiving transistor 2 changes greatly.
Since the gate current Ig of the receiving transistor 2 at the time of excessive input passes through the gate bias circuit 8, the gate bias circuit 8 outputs a change in the gate current Ig as a signal and controls the drain bias circuit 9.

That is, the drain bias circuit 9 switches the output voltage value in response to the change signal from the gate bias circuit 8 to reduce the drain voltage Vd.
Thereby, when the input is excessive, the drain voltage Vd applied to the receiving transistor 2 is lowered, so that the receiving transistor 2 can be prevented from being destroyed.

  In general, the time required to return to the steady state after over-input is eliminated is slower as the operating voltage is higher. However, according to the circuit configuration of FIG. 1, the drain voltage Vd is reduced at the time of over-input. As a result, it is possible to shorten the time until the steady state is restored after the excessive input is eliminated, and the recovery time delay due to the drain lag can be eliminated.

  As described above, the bias circuit according to Embodiment 1 (FIG. 1) of the present invention is a bias circuit used for a receiving amplifier that does not have an over-input protection circuit, and is a receiving circuit that constitutes a receiving amplifier. A gate bias circuit 8 connected to the gate terminal of the transistor 2 and a drain bias circuit 9 connected to the drain terminal of the receiving transistor 2 are provided.

  The gate bias circuit 8 has change detecting means for detecting a change in the gate current Ig or the gate voltage Vg of the receiving transistor 2 at the time of excessive input and generates a change signal. In response to the change signal, the drain voltage Vd for the receiving transistor 2 is reduced.

  As described above, the drain voltage Vd is lowered in response to the change in the gate current Ig or the gate voltage Vg of the receiving transistor 2 at the time of over-input, so that it does not have an over-input protection circuit. Also in the transistor 2, it is possible to prevent destruction due to excessive input without reducing the noise performance with a simple configuration and a small size.

Embodiment 2. FIG.
In the first embodiment (FIG. 1), the change detection means in the gate bias circuit 8 is not specifically mentioned, but the resistor 10 and the gate voltage detection point G are used as shown in FIG. Good.
FIG. 2 is a circuit configuration diagram showing a bias circuit according to Embodiment 2 of the present invention. The same components as those described above (see FIG. 1) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted.

2, the bias circuit according to the second embodiment of the present invention includes a resistor 10 and a gate voltage detection point G as the gate bias circuit 8 described above (FIG. 1).
One end of the resistor 10 is provided with a gate voltage detection point G for controlling the drain bias circuit 9.

  That is, the resistor 10 is inserted between the gate voltage application terminal 6 and the matching circuit 3, and the gate voltage detection point G is provided at the connection point between the resistor 10 and the matching circuit 3. The detection location G functions as a change detection means.

Next, the operation according to the second embodiment of the present invention shown in FIG. 2 will be described.
Here, the relationship between the gate bias voltage Vgg supplied to the gate voltage application terminal 6, the resistance value R (= several hundred Ω to several kΩ) of the resistor 10, and the gate current Ig flowing through the resistor 10 when over-input is considered. .
First, since the gate current Ig does not flow in the steady state, the gate voltage Vg at the gate voltage detection point G has the same value as the gate bias voltage Vgg.

  On the other hand, when the gate current Ig flows due to excessive input, a potential drop (= R × Ig) occurs in the resistor 10, so that the gate voltage Vg at the gate voltage detection point G is higher than the gate bias voltage Vgg in the steady state. Decrease by the drop (= R × Ig).

  Accordingly, a voltage drop at the gate voltage detection point G at the time of over-input is generated as a change signal, and the drain bias circuit 9 is controlled to reduce the drain voltage Vd applied to the receiving transistor 2 at the time of over-input, thereby The transistor 2 can be prevented from being destroyed.

Further, in this case, since the change detection circuit at the time of excessive input can be configured by only the single resistor 10, the circuit configuration can be made inexpensive and small.
Similarly to the above, the noise power generated in the resistor 10 is grounded via the high-frequency short-circuit capacitor 4, so that the high-frequency signal is transmitted to the reception amplification unit composed of the reception transistor 2 and the matching circuit 3. Since it is separated as a path, noise performance is not degraded.

  As described above, according to the second embodiment (FIG. 2) of the present invention, the change detecting means in the gate bias circuit includes the resistor 10 connected in series to the gate terminal of the receiving transistor 2, and the receiving transistor As a change in the gate voltage Vg of 2, the change in the gate current Ig flowing in the resistor 10 at the time of excessive input is detected.

  In this way, the change in the gate current Ig flowing at the time of over-input is detected by the resistor 10 and the drain voltage Vd is reduced, so that the receiving transistor 2 having no over-input protection circuit is small in size with a simple configuration. In addition, it is possible to prevent destruction due to excessive input without impairing noise performance.

Embodiment 3 FIG.
In the first and second embodiments (FIGS. 1 and 2), the specific configuration of the drain bias circuit 9 is not mentioned, but a buffer circuit 12 may be used as shown in FIG.
FIG. 3 is a circuit configuration diagram showing a bias circuit according to Embodiment 3 of the present invention. Components similar to those described above (see FIGS. 1 and 2) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted. To do.

3, the bias circuit according to the third embodiment of the present invention includes a buffer circuit 12 as the drain bias circuit 9 described above (FIG. 2).
When the input voltage from the gate voltage detection point G (gate bias circuit) is the same value as the gate bias voltage Vgg (= −2 [V]) (normal), the buffer circuit 12 uses the drain bias as the drain voltage Vd. When the voltage Vdd (= 10 [V]) is output and the input voltage is a value (= Vgg−R × Ig) that is reduced by the above-described voltage drop (at the time of excessive input), the buffer circuit 12 It is configured to output 0 [V] as Vd.

That is, the drain bias voltage Vdd is supplied from the buffer circuit 12 to the receiving transistor 2 in the steady state, and 0 [V] is supplied in the over-input state.
As a result, it is possible to prevent the receiving transistor 2 from being destroyed even during an excessive input.

  As described above, according to the third embodiment (FIG. 3) of the present invention, the drain bias circuit includes the buffer circuit 12 to which the change signal at the time of excessive input is input, and the buffer circuit 12 receives the change signal. In this case, the drain voltage Vd is switched from the normal drain bias voltage Vdd to 0 [V].

  In this way, by configuring the drain bias circuit with the buffer circuit 12 that responds to a change signal at the time of excessive input, the receiving transistor 2 that does not have an excessive input protection circuit can be reduced in size and noise performance with a simple configuration. It is possible to prevent destruction due to excessive input without damaging the power.

Embodiment 4 FIG.
In the third embodiment (FIG. 3), the specific configuration of the buffer circuit 12 is not mentioned, but a CMOS circuit may be used as shown in FIG.
FIG. 4 is a circuit configuration diagram showing a bias circuit according to Embodiment 4 of the present invention. The same components as those described above (see FIG. 3) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted.

4, the bias circuit according to the fourth embodiment of the present invention is a CMOS circuit comprising a depletion type NMOS transistor 13 and an enhancement type PMOS transistor 14 as the buffer circuit 12 described above (FIG. 3). It has.
The NMOS transistor 13 and the PMOS transistor 14 are manufactured so that each operation threshold voltage is an intermediate value between the gate bias voltage Vgg and the voltage value after voltage drop (= Vgg−R × Ig).

Next, the operation according to the fourth embodiment of the present invention shown in FIG. 4 will be described.
First, when the gate voltage Vg at the gate voltage detection point G is the gate bias voltage Vgg (steady state), the NMOS transistor 13 is in a conductive state (ON) and the PMOS transistor 14 is in a non-conductive state (OFF).

  Therefore, the drain voltage Vd output from the NMOS transistor 13 and the PMOS transistor 14 (buffer circuit) is equal to the drain bias voltage Vdd supplied to the drain voltage application terminal 7.

On the other hand, when the gate voltage Vg at the gate voltage detection point G is Vgg−R × Ig (over-input state), the NMOS transistor 13 is non-conductive, the PMOS transistor 14 is conductive, and the drain voltage Vd is 0 [V]. It becomes.
As a result, the receiving transistor 2 can be prevented from being destroyed as described above.

  As described above, according to the fourth embodiment (FIG. 4) of the present invention, the buffer circuit is constituted by the CMOS circuit composed of the NMOS transistor 13 and the PMOS transistor 14, and therefore does not have an over-input protection circuit. Also in the receiving amplifier, it is possible to prevent destruction due to excessive input without compromising noise performance with a simple configuration and a small size.

Embodiment 5 FIG.
In the fourth embodiment (FIG. 4), the buffer circuit is configured by a CMOS circuit, but may be configured by a two-stage inverter circuit connected in series as shown in FIG.
FIG. 5 is a circuit configuration diagram showing a bias circuit according to Embodiment 5 of the present invention. Components similar to those described above (see FIG. 4) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted.

  5, the bias circuit according to the fifth embodiment of the present invention includes a two-stage inverter circuit connected in series instead of the CMOS circuit described above (FIG. 4) as a buffer circuit constituting the drain bias circuit. ing.

The two-stage inverter circuit includes FETs (Field Effect Transistors) 16 and 17 connected in series and resistors 18 and 19 individually connected to the drain terminals of the FETs 16 and 17, respectively.
That is, the FET 16 and the resistor 18 constitute a front-stage inverter circuit, and the FET 17 and the resistor 19 constitute a rear-stage inverter circuit.

  The drain terminal of the FET 16 is grounded via a resistor 18, and the source terminal of the FET 16 is connected to a control voltage application terminal 20 to which a control voltage Vp (FET pinch-off voltage = −5 [V]) is applied.

  The source terminal of the FET 17 is grounded, and the drain terminal of the FET 17 is connected to the drain voltage application terminal 7 through the resistor 19 and is connected to the drain terminal of the receiving transistor 2 through the matching circuit 3.

Next, the operation according to the fifth embodiment of the present invention shown in FIG. 5 will be described.
First, in the steady state, when the gate voltage Vg detected at the gate voltage detection point G indicates the gate bias voltage Vgg (= −2 [V]), the input voltage (gate potential) of the FET 16 is the control voltage Vp ( = −5 [V]: source potential), the FET 16 is in a conductive state.

Therefore, the output voltage Vo of the inverter circuit composed of the FET 16 and the resistor 18 becomes equal to the control voltage Vp.
At this time, since the FET 17 is in a pinch-off state (non-conducting), the drain voltage Vd output from the inverter circuit including the FET 17 and the resistor 19 is equal to the drain bias voltage Vdd (= 10 [V]).

  On the other hand, when the gate voltage Vg at the gate voltage detection point G indicates the voltage value after the voltage drop (= Vgg−R × Ig <−10 [V]) in the over-input state, the gate potential of the FET 16 is the source potential. Since it is sufficiently lower than (−5 [V]), the FET 16 is in a pinch-off state (non-conductive).

Therefore, since the output voltage Vo of the FET 16 and the resistor 18 (previous stage inverter circuit) becomes 0 [V], the FET 17 becomes conductive, and the drain voltage Vd output from the FET 16 and the resistor 18 (rear stage inverter circuit) is 0 [V].
This can prevent the receiving transistor 2 from being destroyed.
Further, since the same transistors as the receiving transistor 2 can be used as the FETs 16 and 17, monolithic integration is facilitated when a compound semiconductor is used.

  As described above, according to the fifth embodiment (FIG. 5) of the present invention, the buffer circuit is constituted by the two-stage inverter circuit connected in series, and therefore, for reception without an over-input protection circuit. Also in the amplifier, it is possible to prevent destruction due to excessive input without reducing the noise performance with a simple configuration and a small size.

Embodiment 6 FIG.
In the fifth embodiment (FIG. 5), each load element of the two-stage inverter circuit is composed of resistors 18 and 19. However, as shown in FIG. Transistors) 22 and 23 may be used.
FIG. 6 is a circuit configuration diagram showing a bias circuit according to Embodiment 6 of the present invention. Components similar to those described above (see FIG. 5) are denoted by the same reference numerals as those described above, and detailed description thereof is omitted.

In FIG. 6, the bias circuit according to the sixth embodiment of the present invention includes FETs (field effect transistors) 22, instead of the resistors 18 and 19 described above (FIG. 5) as constituent elements of a two-stage inverter circuit. 23.
Each of the FETs 22 and 23 functions as a load transistor in the inverter circuit, and constitutes a two-stage inverter circuit together with the FETs 16 and 17.

The operation of the sixth embodiment of the present invention is the same as that described above (FIG. 5) except that the resistors 18 and 19 are replaced with FETs 22 and 23, respectively.
In general, in an integrated circuit, a load transistor can be made smaller than a resistor, and a load transistor has a higher nonlinearity than a resistor. The margin increases.

Next, a specific calculation example in the sixth embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is an explanatory diagram illustrating an example of a calculation result using a microwave circuit simulator, and FIG. 8 is an explanatory diagram illustrating the calculation result of FIG.

  In FIG. 7, in a steady state, the gate current Ig = 0 [mA], the gate voltage Vg = −2 [V] (= Vgg), and the output voltage Vo of the inverter circuit in the previous stage (FET 16 is on and FET 22 is off). = −5 [V] (= Vp), and the drain voltage Vd≈10 [V] (= Vdd) from the subsequent inverter circuit (FET 17 is OFF and FET 23 is ON).

  On the other hand, at the time of excessive input, the gate current Ig = 10 [mA] to 20 [mA], the gate voltage Vg (= Vgg−R × Ig) <− 10 [V], and the inverter circuit in the previous stage (FET 16 is OFF, FET 22 Output voltage Vo = 0 [V], and the drain voltage Vd≈0 [V] from the subsequent inverter circuit (FET 17 is on and FET 23 is off).

At this time, the gate current Ig, the gate voltage Vg, and the drain voltage Vd vary as shown in FIG. 8, for example, with respect to the input level (horizontal axis).
As is apparent from the calculation result of FIG. 8, over input of 25 [dBm] or more (refer to the horizontal axis) was input by using FETs 16, 17, 22, and 23 as the two-stage inverter circuit (drain bias circuit). In this case, the effect of reducing the drain voltage Vd of the receiving transistor 2 to about 1 [V] is recognized.

  Thereby, even at the time of over-input, for example, the drain voltage Vd of the receiving transistor 2 made of, for example, GaN LNA (Low Noise Amplifier) or GaN HEMT (High Electron Mobility Transistor) is automatically reduced. Thus, the voltage amplitude between the drain and the gate can be reduced, so that the receiving transistor 2 can be prevented from being destroyed.

  As described above, according to the sixth embodiment (FIG. 6) of the present invention, each load element of the two-stage inverter circuit is composed of FETs (bias transistors) 22 and 23 in which the gate and the source are short-circuited. Therefore, even in the receiving transistor 2 that does not have an over-input protection circuit, it is possible to prevent destruction due to over-input without reducing the noise performance with a simple configuration and a small size.

Embodiment 7 FIG.
In the sixth embodiment (FIG. 5), the mounting structure of the FETs 16, 17, 22, and 23 constituting the two-stage inverter circuit in the drain bias circuit is not mentioned, but as shown in FIGS. The monolithic molding may be performed on the same substrate together with the receiving transistor 2.

FIG. 9 is a plan view showing a mounted state of the bias circuit according to the seventh embodiment of the present invention, and shows an example in which the circuit described above (FIG. 6) is monolithically formed.
FIG. 10 is a plan view showing in detail the broken line frame in FIG.

9 and 10, the same components as those described above (see FIG. 6) are denoted by the same reference numerals as those described above and will not be described in detail.
In this case, the FETs 16, 17, 22, and 23 are assumed to have a gate finger structure.

  In the receiving transistor 2 and the FETs 16, 17, 22, and 23 in FIGS. 9 and 10, each bold line indicates a gate terminal. A hatched circle indicates a through hole.

As described above, according to the seventh embodiment (FIGS. 9 and 10) of the present invention, the gate bias circuit (gate voltage application terminal 6, resistor 10 and gate voltage detection point G) and the drain bias circuit (drain voltage) The application terminal 7, FETs 16, 17, 22, and 23 and the control voltage application terminal 20) are on the same substrate 24 together with the reception circuit (reception transistor 2, matching circuit 3, high-frequency short-circuit capacitor 4, and reception signal output terminal 5). Is monolithically molded.
Thereby, in addition to the above-mentioned effect, the entire bias circuit can be reduced in size by monolithic molding.

Embodiment 8 FIG.
Although not particularly mentioned in the seventh embodiment (FIGS. 9 and 10), the gate lengths of the FETs 16, 17, 22, and 23 (bias transistors) are longer than the gate length of the reception transistor 2. It may be set.

  In general, in FETs, it is desirable that the gate length be short in order to obtain good noise performance. However, if microfabrication is performed in order to shorten the gate length, there is a high possibility that the yield will decrease.

Therefore, in order to obtain good noise performance for the receiving transistor 2, the gate length is set short by fine processing, but the FETs 16, 17, 22, and 23 constituting the biasing transistor need to operate particularly fast. Therefore, in order to avoid fine processing (decrease in yield), the gate length is set longer than that of the receiving transistor 2.
The gate length is the thickness (several μm) of each gate terminal (thick line) in FIGS. 9 and 10, and is difficult to specify in the drawings.

  As described above, according to the eighth embodiment of the present invention, when each transistor is monolithically formed, the gate lengths of the FETs 16, 17, 22, and 23 (bias transistors) that do not require high-speed operation are set to high-speed operation. Since it is set longer than the gate length of the receiving transistor 2 that requires the above, good noise performance and yield can be realized at the same time.

Embodiment 9 FIG.
Although not particularly mentioned in the first to eighth embodiments (FIGS. 1 to 10), as shown in FIG. 11, the receiving transistor 2 or FETs 16, 17, 22, and 23 (bias transistors) are used. A gallium nitride (GaN) transistor may be used.

  FIG. 11 is an explanatory diagram showing the relationship between the breakdown voltage Vbr of the transistor element and the maximum withstand power Pmax according to the ninth embodiment of the present invention, and is described in a known document (for example, IEICE Technical Report MW 2008-84). The characteristic diagram is quoted.

Conventionally, a gallium arsenide (GaAs) transistor has been used as the receiving transistor 2 in the microwave region. However, the gallium arsenide transistor has a problem that it has a low breakdown voltage and is vulnerable to excessive input.
On the other hand, a gallium nitride transistor that has been developed in recent years has a high breakdown voltage, and therefore has an advantage that it can withstand a larger over-input than a gallium arsenide transistor.

  As apparent from FIG. 11, by using the gallium nitride (GaN) transistor according to the ninth embodiment of the present invention, in the case of the gallium arsenide (GaAs) transistor (Pmax <20 [dBm], Vbr = number [V]. It can be seen that a high withstand power 100 times or more (Pmax> 40 [dBm], Vbr = 150 [V]) can be obtained.

That is, by using the gallium nitride transistor, the endurance voltage at the time of excessive input is further improved.
In particular, when the FETs 16, 17, 22, and 23 (bias transistors) are monolithically formed on the same substrate 24 together with the receiving transistor 2 as in the seventh embodiment, all the transistors have the same configuration. Therefore, it is effective in manufacturing.

  As described above, according to the ninth embodiment of the present invention, the receiving transistor 2 or the FETs 16, 17, 22, and 23 (bias transistors) are formed of gallium nitride transistors. Thus, there is an advantage that it can withstand a larger over-input.

  1 receiving antenna, 2 receiving transistor, 3 matching circuit, 4 high frequency short-circuit capacitor, 5 receiving signal output terminal, 6 gate voltage applying terminal, 7 drain voltage applying terminal, 8 gate bias circuit, 9 drain bias circuit, 10, 18, 19 resistor, 12 buffer circuit, 13 NMOS transistor, 14 PMOS transistor, 15 drain voltage supply location from bias circuit, 16, 17, 22, 23 FET (field effect transistor), 20 control voltage application terminal, 24 same substrate, G Gate voltage detection location, Ig gate current, Vd drain voltage, Vdd drain bias voltage, Vg gate voltage, Vgg gate bias voltage.

Claims (8)

A bias circuit used for a receiving amplifier having no over-input protection circuit,
A gate bias circuit connected to a gate terminal of a receiving transistor constituting the receiving amplifier;
A drain bias circuit connected to a drain terminal of the receiving transistor,
The gate bias circuit has a change detection means for detecting a change in the gate current or gate voltage of the receiving transistor at the time of over-input and generating a change signal,
The drain bias circuit is configured to reduce a drain output voltage to the receiving transistor in response to a change signal at the time of the over-input ,
The drain bias circuit includes a buffer circuit to which a change signal at the time of excessive input is input,
The buffer circuit, wherein the output voltage value is switched from a normal drain voltage to 0 V when the change signal is input .   The change detection means includes a resistor connected in series to the gate terminal of the receiving transistor, and detects a change in the gate current flowing through the resistor at the time of the over-input as a change in the gate voltage of the receiving transistor. The bias circuit according to claim 1, wherein: The buffer circuit includes a bias circuit according to claim 1 or claim 2, characterized in that it is constituted by a CMOS circuit. The buffer circuit includes a bias circuit according to claim 1 or claim 2, characterized in that it is constituted by two stages of inverter circuits connected in series. 5. The bias circuit according to claim 4 , wherein each load element of the two-stage inverter circuit includes a bias transistor in which a gate and a source are short-circuited. 6. The bias circuit according to claim 5 , wherein the biasing transistor is monolithically formed on the same substrate together with the receiving transistor. The bias circuit according to claim 6 , wherein a gate length of the biasing transistor is set to be longer than a gate length of the receiving transistor. The bias circuit according to any one of claims 1 to 7, wherein the reception transistor or the bias transistor is formed of a gallium nitride transistor.

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